1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
6 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
9 #include <linux/delay.h>
10 #include <linux/slab.h>
11 #include <linux/sched/task_stack.h>
12 #include <linux/interrupt.h>
13 #include <linux/module.h>
14 #include <linux/mtd/partitions.h>
16 #include <linux/of_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/dma/mxs-dma.h>
19 #include "gpmi-nand.h"
20 #include "gpmi-regs.h"
23 /* Resource names for the GPMI NAND driver. */
24 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
25 #define GPMI_NAND_BCH_REGS_ADDR_RES_NAME "bch"
26 #define GPMI_NAND_BCH_INTERRUPT_RES_NAME "bch"
28 /* Converts time to clock cycles */
29 #define TO_CYCLES(duration, period) DIV_ROUND_UP_ULL(duration, period)
31 #define MXS_SET_ADDR 0x4
32 #define MXS_CLR_ADDR 0x8
34 * Clear the bit and poll it cleared. This is usually called with
35 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
38 static int clear_poll_bit(void __iomem *addr, u32 mask)
43 writel(mask, addr + MXS_CLR_ADDR);
46 * SFTRST needs 3 GPMI clocks to settle, the reference manual
47 * recommends to wait 1us.
51 /* poll the bit becoming clear */
52 while ((readl(addr) & mask) && --timeout)
58 #define MODULE_CLKGATE (1 << 30)
59 #define MODULE_SFTRST (1 << 31)
61 * The current mxs_reset_block() will do two things:
62 * [1] enable the module.
63 * [2] reset the module.
65 * In most of the cases, it's ok.
66 * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
67 * If you try to soft reset the BCH block, it becomes unusable until
68 * the next hard reset. This case occurs in the NAND boot mode. When the board
69 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
70 * So If the driver tries to reset the BCH again, the BCH will not work anymore.
71 * You will see a DMA timeout in this case. The bug has been fixed
72 * in the following chips, such as MX28.
74 * To avoid this bug, just add a new parameter `just_enable` for
75 * the mxs_reset_block(), and rewrite it here.
77 static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
82 /* clear and poll SFTRST */
83 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
88 writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
91 /* set SFTRST to reset the block */
92 writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
95 /* poll CLKGATE becoming set */
96 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
98 if (unlikely(!timeout))
102 /* clear and poll SFTRST */
103 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
107 /* clear and poll CLKGATE */
108 ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
115 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
119 static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
125 for (i = 0; i < GPMI_CLK_MAX; i++) {
126 clk = this->resources.clock[i];
131 ret = clk_prepare_enable(clk);
135 clk_disable_unprepare(clk);
142 clk_disable_unprepare(this->resources.clock[i - 1]);
146 static int gpmi_init(struct gpmi_nand_data *this)
148 struct resources *r = &this->resources;
151 ret = gpmi_reset_block(r->gpmi_regs, false);
156 * Reset BCH here, too. We got failures otherwise :(
157 * See later BCH reset for explanation of MX23 and MX28 handling
159 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this));
163 /* Choose NAND mode. */
164 writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
166 /* Set the IRQ polarity. */
167 writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
168 r->gpmi_regs + HW_GPMI_CTRL1_SET);
170 /* Disable Write-Protection. */
171 writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
173 /* Select BCH ECC. */
174 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
177 * Decouple the chip select from dma channel. We use dma0 for all
180 writel(BM_GPMI_CTRL1_DECOUPLE_CS, r->gpmi_regs + HW_GPMI_CTRL1_SET);
187 /* This function is very useful. It is called only when the bug occur. */
188 static void gpmi_dump_info(struct gpmi_nand_data *this)
190 struct resources *r = &this->resources;
191 struct bch_geometry *geo = &this->bch_geometry;
195 dev_err(this->dev, "Show GPMI registers :\n");
196 for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
197 reg = readl(r->gpmi_regs + i * 0x10);
198 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
201 /* start to print out the BCH info */
202 dev_err(this->dev, "Show BCH registers :\n");
203 for (i = 0; i <= HW_BCH_VERSION / 0x10 + 1; i++) {
204 reg = readl(r->bch_regs + i * 0x10);
205 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
207 dev_err(this->dev, "BCH Geometry :\n"
209 "ECC Strength : %u\n"
210 "Page Size in Bytes : %u\n"
211 "Metadata Size in Bytes : %u\n"
212 "ECC Chunk Size in Bytes: %u\n"
213 "ECC Chunk Count : %u\n"
214 "Payload Size in Bytes : %u\n"
215 "Auxiliary Size in Bytes: %u\n"
216 "Auxiliary Status Offset: %u\n"
217 "Block Mark Byte Offset : %u\n"
218 "Block Mark Bit Offset : %u\n",
224 geo->ecc_chunk_count,
227 geo->auxiliary_status_offset,
228 geo->block_mark_byte_offset,
229 geo->block_mark_bit_offset);
232 static inline bool gpmi_check_ecc(struct gpmi_nand_data *this)
234 struct bch_geometry *geo = &this->bch_geometry;
236 /* Do the sanity check. */
237 if (GPMI_IS_MXS(this)) {
238 /* The mx23/mx28 only support the GF13. */
239 if (geo->gf_len == 14)
242 return geo->ecc_strength <= this->devdata->bch_max_ecc_strength;
246 * If we can get the ECC information from the nand chip, we do not
247 * need to calculate them ourselves.
249 * We may have available oob space in this case.
251 static int set_geometry_by_ecc_info(struct gpmi_nand_data *this,
252 unsigned int ecc_strength,
253 unsigned int ecc_step)
255 struct bch_geometry *geo = &this->bch_geometry;
256 struct nand_chip *chip = &this->nand;
257 struct mtd_info *mtd = nand_to_mtd(chip);
258 unsigned int block_mark_bit_offset;
269 "unsupported nand chip. ecc bits : %d, ecc size : %d\n",
270 chip->base.eccreq.strength,
271 chip->base.eccreq.step_size);
274 geo->ecc_chunk_size = ecc_step;
275 geo->ecc_strength = round_up(ecc_strength, 2);
276 if (!gpmi_check_ecc(this))
279 /* Keep the C >= O */
280 if (geo->ecc_chunk_size < mtd->oobsize) {
282 "unsupported nand chip. ecc size: %d, oob size : %d\n",
283 ecc_step, mtd->oobsize);
287 /* The default value, see comment in the legacy_set_geometry(). */
288 geo->metadata_size = 10;
290 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
293 * Now, the NAND chip with 2K page(data chunk is 512byte) shows below:
296 * |<----------------------------------------------------->|
300 * |<-------------------------------------------->| D | | O' |
303 * +---+----------+-+----------+-+----------+-+----------+-+-----+
304 * | M | data |E| data |E| data |E| data |E| |
305 * +---+----------+-+----------+-+----------+-+----------+-+-----+
311 * P : the page size for BCH module.
312 * E : The ECC strength.
313 * G : the length of Galois Field.
314 * N : The chunk count of per page.
315 * M : the metasize of per page.
316 * C : the ecc chunk size, aka the "data" above.
317 * P': the nand chip's page size.
318 * O : the nand chip's oob size.
321 * The formula for P is :
324 * P = ------------ + P' + M
327 * The position of block mark moves forward in the ECC-based view
328 * of page, and the delta is:
331 * D = (---------------- + M)
334 * Please see the comment in legacy_set_geometry().
335 * With the condition C >= O , we still can get same result.
336 * So the bit position of the physical block mark within the ECC-based
337 * view of the page is :
340 geo->page_size = mtd->writesize + geo->metadata_size +
341 (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8;
343 geo->payload_size = mtd->writesize;
345 geo->auxiliary_status_offset = ALIGN(geo->metadata_size, 4);
346 geo->auxiliary_size = ALIGN(geo->metadata_size, 4)
347 + ALIGN(geo->ecc_chunk_count, 4);
349 if (!this->swap_block_mark)
353 block_mark_bit_offset = mtd->writesize * 8 -
354 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1)
355 + geo->metadata_size * 8);
357 geo->block_mark_byte_offset = block_mark_bit_offset / 8;
358 geo->block_mark_bit_offset = block_mark_bit_offset % 8;
363 * Calculate the ECC strength by hand:
364 * E : The ECC strength.
365 * G : the length of Galois Field.
366 * N : The chunk count of per page.
367 * O : the oobsize of the NAND chip.
368 * M : the metasize of per page.
372 * ------------ <= (O - M)
380 static inline int get_ecc_strength(struct gpmi_nand_data *this)
382 struct bch_geometry *geo = &this->bch_geometry;
383 struct mtd_info *mtd = nand_to_mtd(&this->nand);
386 ecc_strength = ((mtd->oobsize - geo->metadata_size) * 8)
387 / (geo->gf_len * geo->ecc_chunk_count);
389 /* We need the minor even number. */
390 return round_down(ecc_strength, 2);
393 static int legacy_set_geometry(struct gpmi_nand_data *this)
395 struct bch_geometry *geo = &this->bch_geometry;
396 struct mtd_info *mtd = nand_to_mtd(&this->nand);
397 unsigned int metadata_size;
398 unsigned int status_size;
399 unsigned int block_mark_bit_offset;
402 * The size of the metadata can be changed, though we set it to 10
403 * bytes now. But it can't be too large, because we have to save
404 * enough space for BCH.
406 geo->metadata_size = 10;
408 /* The default for the length of Galois Field. */
411 /* The default for chunk size. */
412 geo->ecc_chunk_size = 512;
413 while (geo->ecc_chunk_size < mtd->oobsize) {
414 geo->ecc_chunk_size *= 2; /* keep C >= O */
418 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
420 /* We use the same ECC strength for all chunks. */
421 geo->ecc_strength = get_ecc_strength(this);
422 if (!gpmi_check_ecc(this)) {
424 "ecc strength: %d cannot be supported by the controller (%d)\n"
425 "try to use minimum ecc strength that NAND chip required\n",
427 this->devdata->bch_max_ecc_strength);
431 geo->page_size = mtd->writesize + geo->metadata_size +
432 (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8;
433 geo->payload_size = mtd->writesize;
436 * The auxiliary buffer contains the metadata and the ECC status. The
437 * metadata is padded to the nearest 32-bit boundary. The ECC status
438 * contains one byte for every ECC chunk, and is also padded to the
439 * nearest 32-bit boundary.
441 metadata_size = ALIGN(geo->metadata_size, 4);
442 status_size = ALIGN(geo->ecc_chunk_count, 4);
444 geo->auxiliary_size = metadata_size + status_size;
445 geo->auxiliary_status_offset = metadata_size;
447 if (!this->swap_block_mark)
451 * We need to compute the byte and bit offsets of
452 * the physical block mark within the ECC-based view of the page.
454 * NAND chip with 2K page shows below:
460 * +---+----------+-+----------+-+----------+-+----------+-+
461 * | M | data |E| data |E| data |E| data |E|
462 * +---+----------+-+----------+-+----------+-+----------+-+
464 * The position of block mark moves forward in the ECC-based view
465 * of page, and the delta is:
468 * D = (---------------- + M)
471 * With the formula to compute the ECC strength, and the condition
472 * : C >= O (C is the ecc chunk size)
474 * It's easy to deduce to the following result:
476 * E * G (O - M) C - M C - M
477 * ----------- <= ------- <= -------- < ---------
483 * D = (---------------- + M) < C
486 * The above inequality means the position of block mark
487 * within the ECC-based view of the page is still in the data chunk,
488 * and it's NOT in the ECC bits of the chunk.
490 * Use the following to compute the bit position of the
491 * physical block mark within the ECC-based view of the page:
492 * (page_size - D) * 8
496 block_mark_bit_offset = mtd->writesize * 8 -
497 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1)
498 + geo->metadata_size * 8);
500 geo->block_mark_byte_offset = block_mark_bit_offset / 8;
501 geo->block_mark_bit_offset = block_mark_bit_offset % 8;
505 static int common_nfc_set_geometry(struct gpmi_nand_data *this)
507 struct nand_chip *chip = &this->nand;
509 if (chip->ecc.strength > 0 && chip->ecc.size > 0)
510 return set_geometry_by_ecc_info(this, chip->ecc.strength,
513 if ((of_property_read_bool(this->dev->of_node, "fsl,use-minimum-ecc"))
514 || legacy_set_geometry(this)) {
515 if (!(chip->base.eccreq.strength > 0 &&
516 chip->base.eccreq.step_size > 0))
519 return set_geometry_by_ecc_info(this,
520 chip->base.eccreq.strength,
521 chip->base.eccreq.step_size);
527 /* Configures the geometry for BCH. */
528 static int bch_set_geometry(struct gpmi_nand_data *this)
530 struct resources *r = &this->resources;
533 ret = common_nfc_set_geometry(this);
537 ret = pm_runtime_get_sync(this->dev);
542 * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
543 * chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
546 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this));
550 /* Set *all* chip selects to use layout 0. */
551 writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
555 pm_runtime_mark_last_busy(this->dev);
556 pm_runtime_put_autosuspend(this->dev);
562 * <1> Firstly, we should know what's the GPMI-clock means.
563 * The GPMI-clock is the internal clock in the gpmi nand controller.
564 * If you set 100MHz to gpmi nand controller, the GPMI-clock's period
565 * is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
567 * <2> Secondly, we should know what's the frequency on the nand chip pins.
568 * The frequency on the nand chip pins is derived from the GPMI-clock.
569 * We can get it from the following equation:
573 * F : the frequency on the nand chip pins.
574 * G : the GPMI clock, such as 100MHz.
575 * DS : GPMI_HW_GPMI_TIMING0:DATA_SETUP
576 * DH : GPMI_HW_GPMI_TIMING0:DATA_HOLD
578 * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
579 * the nand EDO(extended Data Out) timing could be applied.
580 * The GPMI implements a feedback read strobe to sample the read data.
581 * The feedback read strobe can be delayed to support the nand EDO timing
582 * where the read strobe may deasserts before the read data is valid, and
583 * read data is valid for some time after read strobe.
585 * The following figure illustrates some aspects of a NAND Flash read:
592 * __ ___|__________________________________
596 * Read Data --------------< >---------
600 * FeedbackRDN ________ ____________
603 * D stands for delay, set in the HW_GPMI_CTRL1:RDN_DELAY.
606 * <4> Now, we begin to describe how to compute the right RDN_DELAY.
608 * 4.1) From the aspect of the nand chip pins:
609 * Delay = (tREA + C - tRP) {1}
611 * tREA : the maximum read access time.
612 * C : a constant to adjust the delay. default is 4000ps.
613 * tRP : the read pulse width, which is exactly:
614 * tRP = (GPMI-clock-period) * DATA_SETUP
616 * 4.2) From the aspect of the GPMI nand controller:
617 * Delay = RDN_DELAY * 0.125 * RP {2}
619 * RP : the DLL reference period.
620 * if (GPMI-clock-period > DLL_THRETHOLD)
621 * RP = GPMI-clock-period / 2;
623 * RP = GPMI-clock-period;
625 * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
626 * is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
627 * is 16000ps, but in mx6q, we use 12000ps.
629 * 4.3) since {1} equals {2}, we get:
631 * (tREA + 4000 - tRP) * 8
632 * RDN_DELAY = ----------------------- {3}
635 static void gpmi_nfc_compute_timings(struct gpmi_nand_data *this,
636 const struct nand_sdr_timings *sdr)
638 struct gpmi_nfc_hardware_timing *hw = &this->hw;
639 unsigned int dll_threshold_ps = this->devdata->max_chain_delay;
640 unsigned int period_ps, reference_period_ps;
641 unsigned int data_setup_cycles, data_hold_cycles, addr_setup_cycles;
643 bool use_half_period;
644 int sample_delay_ps, sample_delay_factor;
645 u16 busy_timeout_cycles;
648 if (sdr->tRC_min >= 30000) {
649 /* ONFI non-EDO modes [0-3] */
650 hw->clk_rate = 22000000;
651 wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
652 } else if (sdr->tRC_min >= 25000) {
653 /* ONFI EDO mode 4 */
654 hw->clk_rate = 80000000;
655 wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
657 /* ONFI EDO mode 5 */
658 hw->clk_rate = 100000000;
659 wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_NO_DELAY;
662 /* SDR core timings are given in picoseconds */
663 period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate);
665 addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps);
666 data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps);
667 data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps);
668 busy_timeout_cycles = TO_CYCLES(sdr->tWB_max + sdr->tR_max, period_ps);
670 hw->timing0 = BF_GPMI_TIMING0_ADDRESS_SETUP(addr_setup_cycles) |
671 BF_GPMI_TIMING0_DATA_HOLD(data_hold_cycles) |
672 BF_GPMI_TIMING0_DATA_SETUP(data_setup_cycles);
673 hw->timing1 = BF_GPMI_TIMING1_BUSY_TIMEOUT(busy_timeout_cycles * 4096);
676 * Derive NFC ideal delay from {3}:
678 * (tREA + 4000 - tRP) * 8
679 * RDN_DELAY = -----------------------
682 if (period_ps > dll_threshold_ps) {
683 use_half_period = true;
684 reference_period_ps = period_ps / 2;
686 use_half_period = false;
687 reference_period_ps = period_ps;
690 tRP_ps = data_setup_cycles * period_ps;
691 sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8;
692 if (sample_delay_ps > 0)
693 sample_delay_factor = sample_delay_ps / reference_period_ps;
695 sample_delay_factor = 0;
697 hw->ctrl1n = BF_GPMI_CTRL1_WRN_DLY_SEL(wrn_dly_sel);
698 if (sample_delay_factor)
699 hw->ctrl1n |= BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) |
700 BM_GPMI_CTRL1_DLL_ENABLE |
701 (use_half_period ? BM_GPMI_CTRL1_HALF_PERIOD : 0);
704 static void gpmi_nfc_apply_timings(struct gpmi_nand_data *this)
706 struct gpmi_nfc_hardware_timing *hw = &this->hw;
707 struct resources *r = &this->resources;
708 void __iomem *gpmi_regs = r->gpmi_regs;
709 unsigned int dll_wait_time_us;
711 clk_set_rate(r->clock[0], hw->clk_rate);
713 writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0);
714 writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1);
717 * Clear several CTRL1 fields, DLL must be disabled when setting
718 * RDN_DELAY or HALF_PERIOD.
720 writel(BM_GPMI_CTRL1_CLEAR_MASK, gpmi_regs + HW_GPMI_CTRL1_CLR);
721 writel(hw->ctrl1n, gpmi_regs + HW_GPMI_CTRL1_SET);
723 /* Wait 64 clock cycles before using the GPMI after enabling the DLL */
724 dll_wait_time_us = USEC_PER_SEC / hw->clk_rate * 64;
725 if (!dll_wait_time_us)
726 dll_wait_time_us = 1;
728 /* Wait for the DLL to settle. */
729 udelay(dll_wait_time_us);
732 static int gpmi_setup_data_interface(struct nand_chip *chip, int chipnr,
733 const struct nand_data_interface *conf)
735 struct gpmi_nand_data *this = nand_get_controller_data(chip);
736 const struct nand_sdr_timings *sdr;
738 /* Retrieve required NAND timings */
739 sdr = nand_get_sdr_timings(conf);
743 /* Only MX6 GPMI controller can reach EDO timings */
744 if (sdr->tRC_min <= 25000 && !GPMI_IS_MX6(this))
747 /* Stop here if this call was just a check */
751 /* Do the actual derivation of the controller timings */
752 gpmi_nfc_compute_timings(this, sdr);
754 this->hw.must_apply_timings = true;
759 /* Clears a BCH interrupt. */
760 static void gpmi_clear_bch(struct gpmi_nand_data *this)
762 struct resources *r = &this->resources;
763 writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
766 static struct dma_chan *get_dma_chan(struct gpmi_nand_data *this)
768 /* We use the DMA channel 0 to access all the nand chips. */
769 return this->dma_chans[0];
772 /* This will be called after the DMA operation is finished. */
773 static void dma_irq_callback(void *param)
775 struct gpmi_nand_data *this = param;
776 struct completion *dma_c = &this->dma_done;
781 static irqreturn_t bch_irq(int irq, void *cookie)
783 struct gpmi_nand_data *this = cookie;
785 gpmi_clear_bch(this);
786 complete(&this->bch_done);
790 static int gpmi_raw_len_to_len(struct gpmi_nand_data *this, int raw_len)
793 * raw_len is the length to read/write including bch data which
794 * we are passed in exec_op. Calculate the data length from it.
797 return ALIGN_DOWN(raw_len, this->bch_geometry.ecc_chunk_size);
802 /* Can we use the upper's buffer directly for DMA? */
803 static bool prepare_data_dma(struct gpmi_nand_data *this, const void *buf,
804 int raw_len, struct scatterlist *sgl,
805 enum dma_data_direction dr)
808 int len = gpmi_raw_len_to_len(this, raw_len);
810 /* first try to map the upper buffer directly */
811 if (virt_addr_valid(buf) && !object_is_on_stack(buf)) {
812 sg_init_one(sgl, buf, len);
813 ret = dma_map_sg(this->dev, sgl, 1, dr);
821 /* We have to use our own DMA buffer. */
822 sg_init_one(sgl, this->data_buffer_dma, len);
824 if (dr == DMA_TO_DEVICE && buf != this->data_buffer_dma)
825 memcpy(this->data_buffer_dma, buf, len);
827 dma_map_sg(this->dev, sgl, 1, dr);
833 * gpmi_copy_bits - copy bits from one memory region to another
834 * @dst: destination buffer
835 * @dst_bit_off: bit offset we're starting to write at
836 * @src: source buffer
837 * @src_bit_off: bit offset we're starting to read from
838 * @nbits: number of bits to copy
840 * This functions copies bits from one memory region to another, and is used by
841 * the GPMI driver to copy ECC sections which are not guaranteed to be byte
844 * src and dst should not overlap.
847 static void gpmi_copy_bits(u8 *dst, size_t dst_bit_off, const u8 *src,
848 size_t src_bit_off, size_t nbits)
853 size_t bits_in_src_buffer = 0;
859 * Move src and dst pointers to the closest byte pointer and store bit
860 * offsets within a byte.
862 src += src_bit_off / 8;
865 dst += dst_bit_off / 8;
869 * Initialize the src_buffer value with bits available in the first
870 * byte of data so that we end up with a byte aligned src pointer.
873 src_buffer = src[0] >> src_bit_off;
874 if (nbits >= (8 - src_bit_off)) {
875 bits_in_src_buffer += 8 - src_bit_off;
877 src_buffer &= GENMASK(nbits - 1, 0);
878 bits_in_src_buffer += nbits;
880 nbits -= bits_in_src_buffer;
884 /* Calculate the number of bytes that can be copied from src to dst. */
887 /* Try to align dst to a byte boundary. */
889 if (bits_in_src_buffer < (8 - dst_bit_off) && nbytes) {
890 src_buffer |= src[0] << bits_in_src_buffer;
891 bits_in_src_buffer += 8;
896 if (bits_in_src_buffer >= (8 - dst_bit_off)) {
897 dst[0] &= GENMASK(dst_bit_off - 1, 0);
898 dst[0] |= src_buffer << dst_bit_off;
899 src_buffer >>= (8 - dst_bit_off);
900 bits_in_src_buffer -= (8 - dst_bit_off);
903 if (bits_in_src_buffer > 7) {
904 bits_in_src_buffer -= 8;
912 if (!bits_in_src_buffer && !dst_bit_off) {
914 * Both src and dst pointers are byte aligned, thus we can
915 * just use the optimized memcpy function.
918 memcpy(dst, src, nbytes);
921 * src buffer is not byte aligned, hence we have to copy each
922 * src byte to the src_buffer variable before extracting a byte
925 for (i = 0; i < nbytes; i++) {
926 src_buffer |= src[i] << bits_in_src_buffer;
931 /* Update dst and src pointers */
936 * nbits is the number of remaining bits. It should not exceed 8 as
937 * we've already copied as much bytes as possible.
942 * If there's no more bits to copy to the destination and src buffer
943 * was already byte aligned, then we're done.
945 if (!nbits && !bits_in_src_buffer)
948 /* Copy the remaining bits to src_buffer */
950 src_buffer |= (*src & GENMASK(nbits - 1, 0)) <<
952 bits_in_src_buffer += nbits;
955 * In case there were not enough bits to get a byte aligned dst buffer
956 * prepare the src_buffer variable to match the dst organization (shift
957 * src_buffer by dst_bit_off and retrieve the least significant bits
961 src_buffer = (src_buffer << dst_bit_off) |
962 (*dst & GENMASK(dst_bit_off - 1, 0));
963 bits_in_src_buffer += dst_bit_off;
966 * Keep most significant bits from dst if we end up with an unaligned
969 nbytes = bits_in_src_buffer / 8;
970 if (bits_in_src_buffer % 8) {
971 src_buffer |= (dst[nbytes] &
972 GENMASK(7, bits_in_src_buffer % 8)) <<
977 /* Copy the remaining bytes to dst */
978 for (i = 0; i < nbytes; i++) {
984 /* add our owner bbt descriptor */
985 static uint8_t scan_ff_pattern[] = { 0xff };
986 static struct nand_bbt_descr gpmi_bbt_descr = {
990 .pattern = scan_ff_pattern
994 * We may change the layout if we can get the ECC info from the datasheet,
995 * else we will use all the (page + OOB).
997 static int gpmi_ooblayout_ecc(struct mtd_info *mtd, int section,
998 struct mtd_oob_region *oobregion)
1000 struct nand_chip *chip = mtd_to_nand(mtd);
1001 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1002 struct bch_geometry *geo = &this->bch_geometry;
1007 oobregion->offset = 0;
1008 oobregion->length = geo->page_size - mtd->writesize;
1013 static int gpmi_ooblayout_free(struct mtd_info *mtd, int section,
1014 struct mtd_oob_region *oobregion)
1016 struct nand_chip *chip = mtd_to_nand(mtd);
1017 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1018 struct bch_geometry *geo = &this->bch_geometry;
1023 /* The available oob size we have. */
1024 if (geo->page_size < mtd->writesize + mtd->oobsize) {
1025 oobregion->offset = geo->page_size - mtd->writesize;
1026 oobregion->length = mtd->oobsize - oobregion->offset;
1032 static const char * const gpmi_clks_for_mx2x[] = {
1036 static const struct mtd_ooblayout_ops gpmi_ooblayout_ops = {
1037 .ecc = gpmi_ooblayout_ecc,
1038 .free = gpmi_ooblayout_free,
1041 static const struct gpmi_devdata gpmi_devdata_imx23 = {
1043 .bch_max_ecc_strength = 20,
1044 .max_chain_delay = 16000,
1045 .clks = gpmi_clks_for_mx2x,
1046 .clks_count = ARRAY_SIZE(gpmi_clks_for_mx2x),
1049 static const struct gpmi_devdata gpmi_devdata_imx28 = {
1051 .bch_max_ecc_strength = 20,
1052 .max_chain_delay = 16000,
1053 .clks = gpmi_clks_for_mx2x,
1054 .clks_count = ARRAY_SIZE(gpmi_clks_for_mx2x),
1057 static const char * const gpmi_clks_for_mx6[] = {
1058 "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_bch_apb", "per1_bch",
1061 static const struct gpmi_devdata gpmi_devdata_imx6q = {
1063 .bch_max_ecc_strength = 40,
1064 .max_chain_delay = 12000,
1065 .clks = gpmi_clks_for_mx6,
1066 .clks_count = ARRAY_SIZE(gpmi_clks_for_mx6),
1069 static const struct gpmi_devdata gpmi_devdata_imx6sx = {
1071 .bch_max_ecc_strength = 62,
1072 .max_chain_delay = 12000,
1073 .clks = gpmi_clks_for_mx6,
1074 .clks_count = ARRAY_SIZE(gpmi_clks_for_mx6),
1077 static const char * const gpmi_clks_for_mx7d[] = {
1078 "gpmi_io", "gpmi_bch_apb",
1081 static const struct gpmi_devdata gpmi_devdata_imx7d = {
1083 .bch_max_ecc_strength = 62,
1084 .max_chain_delay = 12000,
1085 .clks = gpmi_clks_for_mx7d,
1086 .clks_count = ARRAY_SIZE(gpmi_clks_for_mx7d),
1089 static int acquire_register_block(struct gpmi_nand_data *this,
1090 const char *res_name)
1092 struct platform_device *pdev = this->pdev;
1093 struct resources *res = &this->resources;
1097 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
1098 p = devm_ioremap_resource(&pdev->dev, r);
1102 if (!strcmp(res_name, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME))
1104 else if (!strcmp(res_name, GPMI_NAND_BCH_REGS_ADDR_RES_NAME))
1107 dev_err(this->dev, "unknown resource name : %s\n", res_name);
1112 static int acquire_bch_irq(struct gpmi_nand_data *this, irq_handler_t irq_h)
1114 struct platform_device *pdev = this->pdev;
1115 const char *res_name = GPMI_NAND_BCH_INTERRUPT_RES_NAME;
1119 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
1121 dev_err(this->dev, "Can't get resource for %s\n", res_name);
1125 err = devm_request_irq(this->dev, r->start, irq_h, 0, res_name, this);
1127 dev_err(this->dev, "error requesting BCH IRQ\n");
1132 static void release_dma_channels(struct gpmi_nand_data *this)
1135 for (i = 0; i < DMA_CHANS; i++)
1136 if (this->dma_chans[i]) {
1137 dma_release_channel(this->dma_chans[i]);
1138 this->dma_chans[i] = NULL;
1142 static int acquire_dma_channels(struct gpmi_nand_data *this)
1144 struct platform_device *pdev = this->pdev;
1145 struct dma_chan *dma_chan;
1147 /* request dma channel */
1148 dma_chan = dma_request_slave_channel(&pdev->dev, "rx-tx");
1150 dev_err(this->dev, "Failed to request DMA channel.\n");
1154 this->dma_chans[0] = dma_chan;
1158 release_dma_channels(this);
1162 static int gpmi_get_clks(struct gpmi_nand_data *this)
1164 struct resources *r = &this->resources;
1168 for (i = 0; i < this->devdata->clks_count; i++) {
1169 clk = devm_clk_get(this->dev, this->devdata->clks[i]);
1178 if (GPMI_IS_MX6(this))
1180 * Set the default value for the gpmi clock.
1182 * If you want to use the ONFI nand which is in the
1183 * Synchronous Mode, you should change the clock as you need.
1185 clk_set_rate(r->clock[0], 22000000);
1190 dev_dbg(this->dev, "failed in finding the clocks.\n");
1194 static int acquire_resources(struct gpmi_nand_data *this)
1198 ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME);
1202 ret = acquire_register_block(this, GPMI_NAND_BCH_REGS_ADDR_RES_NAME);
1206 ret = acquire_bch_irq(this, bch_irq);
1210 ret = acquire_dma_channels(this);
1214 ret = gpmi_get_clks(this);
1220 release_dma_channels(this);
1225 static void release_resources(struct gpmi_nand_data *this)
1227 release_dma_channels(this);
1230 static void gpmi_free_dma_buffer(struct gpmi_nand_data *this)
1232 struct device *dev = this->dev;
1233 struct bch_geometry *geo = &this->bch_geometry;
1235 if (this->auxiliary_virt && virt_addr_valid(this->auxiliary_virt))
1236 dma_free_coherent(dev, geo->auxiliary_size,
1237 this->auxiliary_virt,
1238 this->auxiliary_phys);
1239 kfree(this->data_buffer_dma);
1240 kfree(this->raw_buffer);
1242 this->data_buffer_dma = NULL;
1243 this->raw_buffer = NULL;
1246 /* Allocate the DMA buffers */
1247 static int gpmi_alloc_dma_buffer(struct gpmi_nand_data *this)
1249 struct bch_geometry *geo = &this->bch_geometry;
1250 struct device *dev = this->dev;
1251 struct mtd_info *mtd = nand_to_mtd(&this->nand);
1254 * [2] Allocate a read/write data buffer.
1255 * The gpmi_alloc_dma_buffer can be called twice.
1256 * We allocate a PAGE_SIZE length buffer if gpmi_alloc_dma_buffer
1257 * is called before the NAND identification; and we allocate a
1258 * buffer of the real NAND page size when the gpmi_alloc_dma_buffer
1261 this->data_buffer_dma = kzalloc(mtd->writesize ?: PAGE_SIZE,
1262 GFP_DMA | GFP_KERNEL);
1263 if (this->data_buffer_dma == NULL)
1266 this->auxiliary_virt = dma_alloc_coherent(dev, geo->auxiliary_size,
1267 &this->auxiliary_phys, GFP_DMA);
1268 if (!this->auxiliary_virt)
1271 this->raw_buffer = kzalloc((mtd->writesize ?: PAGE_SIZE) + mtd->oobsize, GFP_KERNEL);
1272 if (!this->raw_buffer)
1278 gpmi_free_dma_buffer(this);
1283 * Handles block mark swapping.
1284 * It can be called in swapping the block mark, or swapping it back,
1285 * because the the operations are the same.
1287 static void block_mark_swapping(struct gpmi_nand_data *this,
1288 void *payload, void *auxiliary)
1290 struct bch_geometry *nfc_geo = &this->bch_geometry;
1295 unsigned char from_data;
1296 unsigned char from_oob;
1298 if (!this->swap_block_mark)
1302 * If control arrives here, we're swapping. Make some convenience
1305 bit = nfc_geo->block_mark_bit_offset;
1306 p = payload + nfc_geo->block_mark_byte_offset;
1310 * Get the byte from the data area that overlays the block mark. Since
1311 * the ECC engine applies its own view to the bits in the page, the
1312 * physical block mark won't (in general) appear on a byte boundary in
1315 from_data = (p[0] >> bit) | (p[1] << (8 - bit));
1317 /* Get the byte from the OOB. */
1323 mask = (0x1 << bit) - 1;
1324 p[0] = (p[0] & mask) | (from_oob << bit);
1327 p[1] = (p[1] & mask) | (from_oob >> (8 - bit));
1330 static int gpmi_count_bitflips(struct nand_chip *chip, void *buf, int first,
1333 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1334 struct bch_geometry *nfc_geo = &this->bch_geometry;
1335 struct mtd_info *mtd = nand_to_mtd(chip);
1337 unsigned char *status;
1338 unsigned int max_bitflips = 0;
1340 /* Loop over status bytes, accumulating ECC status. */
1341 status = this->auxiliary_virt + ALIGN(meta, 4);
1343 for (i = first; i < last; i++, status++) {
1344 if ((*status == STATUS_GOOD) || (*status == STATUS_ERASED))
1347 if (*status == STATUS_UNCORRECTABLE) {
1348 int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len;
1349 u8 *eccbuf = this->raw_buffer;
1350 int offset, bitoffset;
1354 /* Read ECC bytes into our internal raw_buffer */
1355 offset = nfc_geo->metadata_size * 8;
1356 offset += ((8 * nfc_geo->ecc_chunk_size) + eccbits) * (i + 1);
1358 bitoffset = offset % 8;
1359 eccbytes = DIV_ROUND_UP(offset + eccbits, 8);
1362 nand_change_read_column_op(chip, offset, eccbuf,
1366 * ECC data are not byte aligned and we may have
1367 * in-band data in the first and last byte of
1368 * eccbuf. Set non-eccbits to one so that
1369 * nand_check_erased_ecc_chunk() does not count them
1373 eccbuf[0] |= GENMASK(bitoffset - 1, 0);
1375 bitoffset = (bitoffset + eccbits) % 8;
1377 eccbuf[eccbytes - 1] |= GENMASK(7, bitoffset);
1380 * The ECC hardware has an uncorrectable ECC status
1381 * code in case we have bitflips in an erased page. As
1382 * nothing was written into this subpage the ECC is
1383 * obviously wrong and we can not trust it. We assume
1384 * at this point that we are reading an erased page and
1385 * try to correct the bitflips in buffer up to
1386 * ecc_strength bitflips. If this is a page with random
1387 * data, we exceed this number of bitflips and have a
1388 * ECC failure. Otherwise we use the corrected buffer.
1391 /* The first block includes metadata */
1392 flips = nand_check_erased_ecc_chunk(
1393 buf + i * nfc_geo->ecc_chunk_size,
1394 nfc_geo->ecc_chunk_size,
1396 this->auxiliary_virt,
1397 nfc_geo->metadata_size,
1398 nfc_geo->ecc_strength);
1400 flips = nand_check_erased_ecc_chunk(
1401 buf + i * nfc_geo->ecc_chunk_size,
1402 nfc_geo->ecc_chunk_size,
1405 nfc_geo->ecc_strength);
1409 max_bitflips = max_t(unsigned int, max_bitflips,
1411 mtd->ecc_stats.corrected += flips;
1415 mtd->ecc_stats.failed++;
1419 mtd->ecc_stats.corrected += *status;
1420 max_bitflips = max_t(unsigned int, max_bitflips, *status);
1423 return max_bitflips;
1426 static void gpmi_bch_layout_std(struct gpmi_nand_data *this)
1428 struct bch_geometry *geo = &this->bch_geometry;
1429 unsigned int ecc_strength = geo->ecc_strength >> 1;
1430 unsigned int gf_len = geo->gf_len;
1431 unsigned int block_size = geo->ecc_chunk_size;
1433 this->bch_flashlayout0 =
1434 BF_BCH_FLASH0LAYOUT0_NBLOCKS(geo->ecc_chunk_count - 1) |
1435 BF_BCH_FLASH0LAYOUT0_META_SIZE(geo->metadata_size) |
1436 BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this) |
1437 BF_BCH_FLASH0LAYOUT0_GF(gf_len, this) |
1438 BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this);
1440 this->bch_flashlayout1 =
1441 BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(geo->page_size) |
1442 BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this) |
1443 BF_BCH_FLASH0LAYOUT1_GF(gf_len, this) |
1444 BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this);
1447 static int gpmi_ecc_read_page(struct nand_chip *chip, uint8_t *buf,
1448 int oob_required, int page)
1450 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1451 struct mtd_info *mtd = nand_to_mtd(chip);
1452 struct bch_geometry *geo = &this->bch_geometry;
1453 unsigned int max_bitflips;
1456 gpmi_bch_layout_std(this);
1459 ret = nand_read_page_op(chip, page, 0, buf, geo->page_size);
1463 max_bitflips = gpmi_count_bitflips(chip, buf, 0,
1464 geo->ecc_chunk_count,
1465 geo->auxiliary_status_offset);
1467 /* handle the block mark swapping */
1468 block_mark_swapping(this, buf, this->auxiliary_virt);
1472 * It's time to deliver the OOB bytes. See gpmi_ecc_read_oob()
1473 * for details about our policy for delivering the OOB.
1475 * We fill the caller's buffer with set bits, and then copy the
1476 * block mark to th caller's buffer. Note that, if block mark
1477 * swapping was necessary, it has already been done, so we can
1478 * rely on the first byte of the auxiliary buffer to contain
1481 memset(chip->oob_poi, ~0, mtd->oobsize);
1482 chip->oob_poi[0] = ((uint8_t *)this->auxiliary_virt)[0];
1485 return max_bitflips;
1488 /* Fake a virtual small page for the subpage read */
1489 static int gpmi_ecc_read_subpage(struct nand_chip *chip, uint32_t offs,
1490 uint32_t len, uint8_t *buf, int page)
1492 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1493 struct bch_geometry *geo = &this->bch_geometry;
1494 int size = chip->ecc.size; /* ECC chunk size */
1495 int meta, n, page_size;
1496 unsigned int max_bitflips;
1497 unsigned int ecc_strength;
1498 int first, last, marker_pos;
1499 int ecc_parity_size;
1503 /* The size of ECC parity */
1504 ecc_parity_size = geo->gf_len * geo->ecc_strength / 8;
1506 /* Align it with the chunk size */
1507 first = offs / size;
1508 last = (offs + len - 1) / size;
1510 if (this->swap_block_mark) {
1512 * Find the chunk which contains the Block Marker.
1513 * If this chunk is in the range of [first, last],
1514 * we have to read out the whole page.
1515 * Why? since we had swapped the data at the position of Block
1516 * Marker to the metadata which is bound with the chunk 0.
1518 marker_pos = geo->block_mark_byte_offset / size;
1519 if (last >= marker_pos && first <= marker_pos) {
1521 "page:%d, first:%d, last:%d, marker at:%d\n",
1522 page, first, last, marker_pos);
1523 return gpmi_ecc_read_page(chip, buf, 0, page);
1527 meta = geo->metadata_size;
1529 col = meta + (size + ecc_parity_size) * first;
1531 buf = buf + first * size;
1534 ecc_parity_size = geo->gf_len * geo->ecc_strength / 8;
1536 n = last - first + 1;
1537 page_size = meta + (size + ecc_parity_size) * n;
1538 ecc_strength = geo->ecc_strength >> 1;
1540 this->bch_flashlayout0 = BF_BCH_FLASH0LAYOUT0_NBLOCKS(n - 1) |
1541 BF_BCH_FLASH0LAYOUT0_META_SIZE(meta) |
1542 BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this) |
1543 BF_BCH_FLASH0LAYOUT0_GF(geo->gf_len, this) |
1544 BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(geo->ecc_chunk_size, this);
1546 this->bch_flashlayout1 = BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) |
1547 BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this) |
1548 BF_BCH_FLASH0LAYOUT1_GF(geo->gf_len, this) |
1549 BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(geo->ecc_chunk_size, this);
1553 ret = nand_read_page_op(chip, page, col, buf, page_size);
1557 dev_dbg(this->dev, "page:%d(%d:%d)%d, chunk:(%d:%d), BCH PG size:%d\n",
1558 page, offs, len, col, first, n, page_size);
1560 max_bitflips = gpmi_count_bitflips(chip, buf, first, last, meta);
1562 return max_bitflips;
1565 static int gpmi_ecc_write_page(struct nand_chip *chip, const uint8_t *buf,
1566 int oob_required, int page)
1568 struct mtd_info *mtd = nand_to_mtd(chip);
1569 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1570 struct bch_geometry *nfc_geo = &this->bch_geometry;
1573 dev_dbg(this->dev, "ecc write page.\n");
1575 gpmi_bch_layout_std(this);
1578 memcpy(this->auxiliary_virt, chip->oob_poi, nfc_geo->auxiliary_size);
1580 if (this->swap_block_mark) {
1582 * When doing bad block marker swapping we must always copy the
1583 * input buffer as we can't modify the const buffer.
1585 memcpy(this->data_buffer_dma, buf, mtd->writesize);
1586 buf = this->data_buffer_dma;
1587 block_mark_swapping(this, this->data_buffer_dma,
1588 this->auxiliary_virt);
1591 ret = nand_prog_page_op(chip, page, 0, buf, nfc_geo->page_size);
1597 * There are several places in this driver where we have to handle the OOB and
1598 * block marks. This is the function where things are the most complicated, so
1599 * this is where we try to explain it all. All the other places refer back to
1602 * These are the rules, in order of decreasing importance:
1604 * 1) Nothing the caller does can be allowed to imperil the block mark.
1606 * 2) In read operations, the first byte of the OOB we return must reflect the
1607 * true state of the block mark, no matter where that block mark appears in
1608 * the physical page.
1610 * 3) ECC-based read operations return an OOB full of set bits (since we never
1611 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
1614 * 4) "Raw" read operations return a direct view of the physical bytes in the
1615 * page, using the conventional definition of which bytes are data and which
1616 * are OOB. This gives the caller a way to see the actual, physical bytes
1617 * in the page, without the distortions applied by our ECC engine.
1620 * What we do for this specific read operation depends on two questions:
1622 * 1) Are we doing a "raw" read, or an ECC-based read?
1624 * 2) Are we using block mark swapping or transcription?
1626 * There are four cases, illustrated by the following Karnaugh map:
1628 * | Raw | ECC-based |
1629 * -------------+-------------------------+-------------------------+
1630 * | Read the conventional | |
1631 * | OOB at the end of the | |
1632 * Swapping | page and return it. It | |
1633 * | contains exactly what | |
1634 * | we want. | Read the block mark and |
1635 * -------------+-------------------------+ return it in a buffer |
1636 * | Read the conventional | full of set bits. |
1637 * | OOB at the end of the | |
1638 * | page and also the block | |
1639 * Transcribing | mark in the metadata. | |
1640 * | Copy the block mark | |
1641 * | into the first byte of | |
1643 * -------------+-------------------------+-------------------------+
1645 * Note that we break rule #4 in the Transcribing/Raw case because we're not
1646 * giving an accurate view of the actual, physical bytes in the page (we're
1647 * overwriting the block mark). That's OK because it's more important to follow
1650 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1651 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1652 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
1653 * ECC-based or raw view of the page is implicit in which function it calls
1654 * (there is a similar pair of ECC-based/raw functions for writing).
1656 static int gpmi_ecc_read_oob(struct nand_chip *chip, int page)
1658 struct mtd_info *mtd = nand_to_mtd(chip);
1659 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1662 /* clear the OOB buffer */
1663 memset(chip->oob_poi, ~0, mtd->oobsize);
1665 /* Read out the conventional OOB. */
1666 ret = nand_read_page_op(chip, page, mtd->writesize, chip->oob_poi,
1672 * Now, we want to make sure the block mark is correct. In the
1673 * non-transcribing case (!GPMI_IS_MX23()), we already have it.
1674 * Otherwise, we need to explicitly read it.
1676 if (GPMI_IS_MX23(this)) {
1677 /* Read the block mark into the first byte of the OOB buffer. */
1678 ret = nand_read_page_op(chip, page, 0, chip->oob_poi, 1);
1686 static int gpmi_ecc_write_oob(struct nand_chip *chip, int page)
1688 struct mtd_info *mtd = nand_to_mtd(chip);
1689 struct mtd_oob_region of = { };
1691 /* Do we have available oob area? */
1692 mtd_ooblayout_free(mtd, 0, &of);
1696 if (!nand_is_slc(chip))
1699 return nand_prog_page_op(chip, page, mtd->writesize + of.offset,
1700 chip->oob_poi + of.offset, of.length);
1704 * This function reads a NAND page without involving the ECC engine (no HW
1706 * The tricky part in the GPMI/BCH controller is that it stores ECC bits
1707 * inline (interleaved with payload DATA), and do not align data chunk on
1709 * We thus need to take care moving the payload data and ECC bits stored in the
1710 * page into the provided buffers, which is why we're using gpmi_copy_bits.
1712 * See set_geometry_by_ecc_info inline comments to have a full description
1713 * of the layout used by the GPMI controller.
1715 static int gpmi_ecc_read_page_raw(struct nand_chip *chip, uint8_t *buf,
1716 int oob_required, int page)
1718 struct mtd_info *mtd = nand_to_mtd(chip);
1719 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1720 struct bch_geometry *nfc_geo = &this->bch_geometry;
1721 int eccsize = nfc_geo->ecc_chunk_size;
1722 int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len;
1723 u8 *tmp_buf = this->raw_buffer;
1726 size_t oob_byte_off;
1727 uint8_t *oob = chip->oob_poi;
1731 ret = nand_read_page_op(chip, page, 0, tmp_buf,
1732 mtd->writesize + mtd->oobsize);
1737 * If required, swap the bad block marker and the data stored in the
1738 * metadata section, so that we don't wrongly consider a block as bad.
1740 * See the layout description for a detailed explanation on why this
1743 if (this->swap_block_mark)
1744 swap(tmp_buf[0], tmp_buf[mtd->writesize]);
1747 * Copy the metadata section into the oob buffer (this section is
1748 * guaranteed to be aligned on a byte boundary).
1751 memcpy(oob, tmp_buf, nfc_geo->metadata_size);
1753 oob_bit_off = nfc_geo->metadata_size * 8;
1754 src_bit_off = oob_bit_off;
1756 /* Extract interleaved payload data and ECC bits */
1757 for (step = 0; step < nfc_geo->ecc_chunk_count; step++) {
1759 gpmi_copy_bits(buf, step * eccsize * 8,
1760 tmp_buf, src_bit_off,
1762 src_bit_off += eccsize * 8;
1764 /* Align last ECC block to align a byte boundary */
1765 if (step == nfc_geo->ecc_chunk_count - 1 &&
1766 (oob_bit_off + eccbits) % 8)
1767 eccbits += 8 - ((oob_bit_off + eccbits) % 8);
1770 gpmi_copy_bits(oob, oob_bit_off,
1771 tmp_buf, src_bit_off,
1774 src_bit_off += eccbits;
1775 oob_bit_off += eccbits;
1779 oob_byte_off = oob_bit_off / 8;
1781 if (oob_byte_off < mtd->oobsize)
1782 memcpy(oob + oob_byte_off,
1783 tmp_buf + mtd->writesize + oob_byte_off,
1784 mtd->oobsize - oob_byte_off);
1791 * This function writes a NAND page without involving the ECC engine (no HW
1793 * The tricky part in the GPMI/BCH controller is that it stores ECC bits
1794 * inline (interleaved with payload DATA), and do not align data chunk on
1796 * We thus need to take care moving the OOB area at the right place in the
1797 * final page, which is why we're using gpmi_copy_bits.
1799 * See set_geometry_by_ecc_info inline comments to have a full description
1800 * of the layout used by the GPMI controller.
1802 static int gpmi_ecc_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1803 int oob_required, int page)
1805 struct mtd_info *mtd = nand_to_mtd(chip);
1806 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1807 struct bch_geometry *nfc_geo = &this->bch_geometry;
1808 int eccsize = nfc_geo->ecc_chunk_size;
1809 int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len;
1810 u8 *tmp_buf = this->raw_buffer;
1811 uint8_t *oob = chip->oob_poi;
1814 size_t oob_byte_off;
1818 * Initialize all bits to 1 in case we don't have a buffer for the
1819 * payload or oob data in order to leave unspecified bits of data
1820 * to their initial state.
1822 if (!buf || !oob_required)
1823 memset(tmp_buf, 0xff, mtd->writesize + mtd->oobsize);
1826 * First copy the metadata section (stored in oob buffer) at the
1827 * beginning of the page, as imposed by the GPMI layout.
1829 memcpy(tmp_buf, oob, nfc_geo->metadata_size);
1830 oob_bit_off = nfc_geo->metadata_size * 8;
1831 dst_bit_off = oob_bit_off;
1833 /* Interleave payload data and ECC bits */
1834 for (step = 0; step < nfc_geo->ecc_chunk_count; step++) {
1836 gpmi_copy_bits(tmp_buf, dst_bit_off,
1837 buf, step * eccsize * 8, eccsize * 8);
1838 dst_bit_off += eccsize * 8;
1840 /* Align last ECC block to align a byte boundary */
1841 if (step == nfc_geo->ecc_chunk_count - 1 &&
1842 (oob_bit_off + eccbits) % 8)
1843 eccbits += 8 - ((oob_bit_off + eccbits) % 8);
1846 gpmi_copy_bits(tmp_buf, dst_bit_off,
1847 oob, oob_bit_off, eccbits);
1849 dst_bit_off += eccbits;
1850 oob_bit_off += eccbits;
1853 oob_byte_off = oob_bit_off / 8;
1855 if (oob_required && oob_byte_off < mtd->oobsize)
1856 memcpy(tmp_buf + mtd->writesize + oob_byte_off,
1857 oob + oob_byte_off, mtd->oobsize - oob_byte_off);
1860 * If required, swap the bad block marker and the first byte of the
1861 * metadata section, so that we don't modify the bad block marker.
1863 * See the layout description for a detailed explanation on why this
1866 if (this->swap_block_mark)
1867 swap(tmp_buf[0], tmp_buf[mtd->writesize]);
1869 return nand_prog_page_op(chip, page, 0, tmp_buf,
1870 mtd->writesize + mtd->oobsize);
1873 static int gpmi_ecc_read_oob_raw(struct nand_chip *chip, int page)
1875 return gpmi_ecc_read_page_raw(chip, NULL, 1, page);
1878 static int gpmi_ecc_write_oob_raw(struct nand_chip *chip, int page)
1880 return gpmi_ecc_write_page_raw(chip, NULL, 1, page);
1883 static int gpmi_block_markbad(struct nand_chip *chip, loff_t ofs)
1885 struct mtd_info *mtd = nand_to_mtd(chip);
1886 struct gpmi_nand_data *this = nand_get_controller_data(chip);
1888 uint8_t *block_mark;
1889 int column, page, chipnr;
1891 chipnr = (int)(ofs >> chip->chip_shift);
1892 nand_select_target(chip, chipnr);
1894 column = !GPMI_IS_MX23(this) ? mtd->writesize : 0;
1896 /* Write the block mark. */
1897 block_mark = this->data_buffer_dma;
1898 block_mark[0] = 0; /* bad block marker */
1900 /* Shift to get page */
1901 page = (int)(ofs >> chip->page_shift);
1903 ret = nand_prog_page_op(chip, page, column, block_mark, 1);
1905 nand_deselect_target(chip);
1910 static int nand_boot_set_geometry(struct gpmi_nand_data *this)
1912 struct boot_rom_geometry *geometry = &this->rom_geometry;
1915 * Set the boot block stride size.
1917 * In principle, we should be reading this from the OTP bits, since
1918 * that's where the ROM is going to get it. In fact, we don't have any
1919 * way to read the OTP bits, so we go with the default and hope for the
1922 geometry->stride_size_in_pages = 64;
1925 * Set the search area stride exponent.
1927 * In principle, we should be reading this from the OTP bits, since
1928 * that's where the ROM is going to get it. In fact, we don't have any
1929 * way to read the OTP bits, so we go with the default and hope for the
1932 geometry->search_area_stride_exponent = 2;
1936 static const char *fingerprint = "STMP";
1937 static int mx23_check_transcription_stamp(struct gpmi_nand_data *this)
1939 struct boot_rom_geometry *rom_geo = &this->rom_geometry;
1940 struct device *dev = this->dev;
1941 struct nand_chip *chip = &this->nand;
1942 unsigned int search_area_size_in_strides;
1943 unsigned int stride;
1945 u8 *buffer = nand_get_data_buf(chip);
1946 int found_an_ncb_fingerprint = false;
1949 /* Compute the number of strides in a search area. */
1950 search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
1952 nand_select_target(chip, 0);
1955 * Loop through the first search area, looking for the NCB fingerprint.
1957 dev_dbg(dev, "Scanning for an NCB fingerprint...\n");
1959 for (stride = 0; stride < search_area_size_in_strides; stride++) {
1960 /* Compute the page addresses. */
1961 page = stride * rom_geo->stride_size_in_pages;
1963 dev_dbg(dev, "Looking for a fingerprint in page 0x%x\n", page);
1966 * Read the NCB fingerprint. The fingerprint is four bytes long
1967 * and starts in the 12th byte of the page.
1969 ret = nand_read_page_op(chip, page, 12, buffer,
1970 strlen(fingerprint));
1974 /* Look for the fingerprint. */
1975 if (!memcmp(buffer, fingerprint, strlen(fingerprint))) {
1976 found_an_ncb_fingerprint = true;
1982 nand_deselect_target(chip);
1984 if (found_an_ncb_fingerprint)
1985 dev_dbg(dev, "\tFound a fingerprint\n");
1987 dev_dbg(dev, "\tNo fingerprint found\n");
1988 return found_an_ncb_fingerprint;
1991 /* Writes a transcription stamp. */
1992 static int mx23_write_transcription_stamp(struct gpmi_nand_data *this)
1994 struct device *dev = this->dev;
1995 struct boot_rom_geometry *rom_geo = &this->rom_geometry;
1996 struct nand_chip *chip = &this->nand;
1997 struct mtd_info *mtd = nand_to_mtd(chip);
1998 unsigned int block_size_in_pages;
1999 unsigned int search_area_size_in_strides;
2000 unsigned int search_area_size_in_pages;
2001 unsigned int search_area_size_in_blocks;
2003 unsigned int stride;
2005 u8 *buffer = nand_get_data_buf(chip);
2008 /* Compute the search area geometry. */
2009 block_size_in_pages = mtd->erasesize / mtd->writesize;
2010 search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent;
2011 search_area_size_in_pages = search_area_size_in_strides *
2012 rom_geo->stride_size_in_pages;
2013 search_area_size_in_blocks =
2014 (search_area_size_in_pages + (block_size_in_pages - 1)) /
2015 block_size_in_pages;
2017 dev_dbg(dev, "Search Area Geometry :\n");
2018 dev_dbg(dev, "\tin Blocks : %u\n", search_area_size_in_blocks);
2019 dev_dbg(dev, "\tin Strides: %u\n", search_area_size_in_strides);
2020 dev_dbg(dev, "\tin Pages : %u\n", search_area_size_in_pages);
2022 nand_select_target(chip, 0);
2024 /* Loop over blocks in the first search area, erasing them. */
2025 dev_dbg(dev, "Erasing the search area...\n");
2027 for (block = 0; block < search_area_size_in_blocks; block++) {
2028 /* Erase this block. */
2029 dev_dbg(dev, "\tErasing block 0x%x\n", block);
2030 status = nand_erase_op(chip, block);
2032 dev_err(dev, "[%s] Erase failed.\n", __func__);
2035 /* Write the NCB fingerprint into the page buffer. */
2036 memset(buffer, ~0, mtd->writesize);
2037 memcpy(buffer + 12, fingerprint, strlen(fingerprint));
2039 /* Loop through the first search area, writing NCB fingerprints. */
2040 dev_dbg(dev, "Writing NCB fingerprints...\n");
2041 for (stride = 0; stride < search_area_size_in_strides; stride++) {
2042 /* Compute the page addresses. */
2043 page = stride * rom_geo->stride_size_in_pages;
2045 /* Write the first page of the current stride. */
2046 dev_dbg(dev, "Writing an NCB fingerprint in page 0x%x\n", page);
2048 status = chip->ecc.write_page_raw(chip, buffer, 0, page);
2050 dev_err(dev, "[%s] Write failed.\n", __func__);
2053 nand_deselect_target(chip);
2058 static int mx23_boot_init(struct gpmi_nand_data *this)
2060 struct device *dev = this->dev;
2061 struct nand_chip *chip = &this->nand;
2062 struct mtd_info *mtd = nand_to_mtd(chip);
2063 unsigned int block_count;
2072 * If control arrives here, we can't use block mark swapping, which
2073 * means we're forced to use transcription. First, scan for the
2074 * transcription stamp. If we find it, then we don't have to do
2075 * anything -- the block marks are already transcribed.
2077 if (mx23_check_transcription_stamp(this))
2081 * If control arrives here, we couldn't find a transcription stamp, so
2082 * so we presume the block marks are in the conventional location.
2084 dev_dbg(dev, "Transcribing bad block marks...\n");
2086 /* Compute the number of blocks in the entire medium. */
2087 block_count = nanddev_eraseblocks_per_target(&chip->base);
2090 * Loop over all the blocks in the medium, transcribing block marks as
2093 for (block = 0; block < block_count; block++) {
2095 * Compute the chip, page and byte addresses for this block's
2096 * conventional mark.
2098 chipnr = block >> (chip->chip_shift - chip->phys_erase_shift);
2099 page = block << (chip->phys_erase_shift - chip->page_shift);
2100 byte = block << chip->phys_erase_shift;
2102 /* Send the command to read the conventional block mark. */
2103 nand_select_target(chip, chipnr);
2104 ret = nand_read_page_op(chip, page, mtd->writesize, &block_mark,
2106 nand_deselect_target(chip);
2112 * Check if the block is marked bad. If so, we need to mark it
2113 * again, but this time the result will be a mark in the
2114 * location where we transcribe block marks.
2116 if (block_mark != 0xff) {
2117 dev_dbg(dev, "Transcribing mark in block %u\n", block);
2118 ret = chip->legacy.block_markbad(chip, byte);
2121 "Failed to mark block bad with ret %d\n",
2126 /* Write the stamp that indicates we've transcribed the block marks. */
2127 mx23_write_transcription_stamp(this);
2131 static int nand_boot_init(struct gpmi_nand_data *this)
2133 nand_boot_set_geometry(this);
2135 /* This is ROM arch-specific initilization before the BBT scanning. */
2136 if (GPMI_IS_MX23(this))
2137 return mx23_boot_init(this);
2141 static int gpmi_set_geometry(struct gpmi_nand_data *this)
2145 /* Free the temporary DMA memory for reading ID. */
2146 gpmi_free_dma_buffer(this);
2148 /* Set up the NFC geometry which is used by BCH. */
2149 ret = bch_set_geometry(this);
2151 dev_err(this->dev, "Error setting BCH geometry : %d\n", ret);
2155 /* Alloc the new DMA buffers according to the pagesize and oobsize */
2156 return gpmi_alloc_dma_buffer(this);
2159 static int gpmi_init_last(struct gpmi_nand_data *this)
2161 struct nand_chip *chip = &this->nand;
2162 struct mtd_info *mtd = nand_to_mtd(chip);
2163 struct nand_ecc_ctrl *ecc = &chip->ecc;
2164 struct bch_geometry *bch_geo = &this->bch_geometry;
2167 /* Set up the medium geometry */
2168 ret = gpmi_set_geometry(this);
2172 /* Init the nand_ecc_ctrl{} */
2173 ecc->read_page = gpmi_ecc_read_page;
2174 ecc->write_page = gpmi_ecc_write_page;
2175 ecc->read_oob = gpmi_ecc_read_oob;
2176 ecc->write_oob = gpmi_ecc_write_oob;
2177 ecc->read_page_raw = gpmi_ecc_read_page_raw;
2178 ecc->write_page_raw = gpmi_ecc_write_page_raw;
2179 ecc->read_oob_raw = gpmi_ecc_read_oob_raw;
2180 ecc->write_oob_raw = gpmi_ecc_write_oob_raw;
2181 ecc->mode = NAND_ECC_HW;
2182 ecc->size = bch_geo->ecc_chunk_size;
2183 ecc->strength = bch_geo->ecc_strength;
2184 mtd_set_ooblayout(mtd, &gpmi_ooblayout_ops);
2187 * We only enable the subpage read when:
2188 * (1) the chip is imx6, and
2189 * (2) the size of the ECC parity is byte aligned.
2191 if (GPMI_IS_MX6(this) &&
2192 ((bch_geo->gf_len * bch_geo->ecc_strength) % 8) == 0) {
2193 ecc->read_subpage = gpmi_ecc_read_subpage;
2194 chip->options |= NAND_SUBPAGE_READ;
2200 static int gpmi_nand_attach_chip(struct nand_chip *chip)
2202 struct gpmi_nand_data *this = nand_get_controller_data(chip);
2205 if (chip->bbt_options & NAND_BBT_USE_FLASH) {
2206 chip->bbt_options |= NAND_BBT_NO_OOB;
2208 if (of_property_read_bool(this->dev->of_node,
2209 "fsl,no-blockmark-swap"))
2210 this->swap_block_mark = false;
2212 dev_dbg(this->dev, "Blockmark swapping %sabled\n",
2213 this->swap_block_mark ? "en" : "dis");
2215 ret = gpmi_init_last(this);
2219 chip->options |= NAND_SKIP_BBTSCAN;
2224 static struct gpmi_transfer *get_next_transfer(struct gpmi_nand_data *this)
2226 struct gpmi_transfer *transfer = &this->transfers[this->ntransfers];
2230 if (this->ntransfers == GPMI_MAX_TRANSFERS)
2236 static struct dma_async_tx_descriptor *gpmi_chain_command(
2237 struct gpmi_nand_data *this, u8 cmd, const u8 *addr, int naddr)
2239 struct dma_chan *channel = get_dma_chan(this);
2240 struct dma_async_tx_descriptor *desc;
2241 struct gpmi_transfer *transfer;
2242 int chip = this->nand.cur_cs;
2245 /* [1] send out the PIO words */
2246 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
2247 | BM_GPMI_CTRL0_WORD_LENGTH
2248 | BF_GPMI_CTRL0_CS(chip, this)
2249 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
2250 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
2251 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
2252 | BF_GPMI_CTRL0_XFER_COUNT(naddr + 1);
2255 desc = mxs_dmaengine_prep_pio(channel, pio, ARRAY_SIZE(pio),
2260 transfer = get_next_transfer(this);
2264 transfer->cmdbuf[0] = cmd;
2266 memcpy(&transfer->cmdbuf[1], addr, naddr);
2268 sg_init_one(&transfer->sgl, transfer->cmdbuf, naddr + 1);
2269 dma_map_sg(this->dev, &transfer->sgl, 1, DMA_TO_DEVICE);
2271 transfer->direction = DMA_TO_DEVICE;
2273 desc = dmaengine_prep_slave_sg(channel, &transfer->sgl, 1, DMA_MEM_TO_DEV,
2274 MXS_DMA_CTRL_WAIT4END);
2278 static struct dma_async_tx_descriptor *gpmi_chain_wait_ready(
2279 struct gpmi_nand_data *this)
2281 struct dma_chan *channel = get_dma_chan(this);
2284 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY)
2285 | BM_GPMI_CTRL0_WORD_LENGTH
2286 | BF_GPMI_CTRL0_CS(this->nand.cur_cs, this)
2287 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
2288 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
2289 | BF_GPMI_CTRL0_XFER_COUNT(0);
2292 return mxs_dmaengine_prep_pio(channel, pio, 2, DMA_TRANS_NONE,
2293 MXS_DMA_CTRL_WAIT4END | MXS_DMA_CTRL_WAIT4RDY);
2296 static struct dma_async_tx_descriptor *gpmi_chain_data_read(
2297 struct gpmi_nand_data *this, void *buf, int raw_len, bool *direct)
2299 struct dma_async_tx_descriptor *desc;
2300 struct dma_chan *channel = get_dma_chan(this);
2301 struct gpmi_transfer *transfer;
2304 transfer = get_next_transfer(this);
2308 transfer->direction = DMA_FROM_DEVICE;
2310 *direct = prepare_data_dma(this, buf, raw_len, &transfer->sgl,
2313 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
2314 | BM_GPMI_CTRL0_WORD_LENGTH
2315 | BF_GPMI_CTRL0_CS(this->nand.cur_cs, this)
2316 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
2317 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
2318 | BF_GPMI_CTRL0_XFER_COUNT(raw_len);
2321 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
2322 | BF_GPMI_ECCCTRL_ECC_CMD(BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE)
2323 | BF_GPMI_ECCCTRL_BUFFER_MASK(BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
2324 | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY);
2326 pio[4] = transfer->sgl.dma_address;
2327 pio[5] = this->auxiliary_phys;
2330 desc = mxs_dmaengine_prep_pio(channel, pio, ARRAY_SIZE(pio),
2336 desc = dmaengine_prep_slave_sg(channel, &transfer->sgl, 1,
2338 MXS_DMA_CTRL_WAIT4END);
2343 static struct dma_async_tx_descriptor *gpmi_chain_data_write(
2344 struct gpmi_nand_data *this, const void *buf, int raw_len)
2346 struct dma_chan *channel = get_dma_chan(this);
2347 struct dma_async_tx_descriptor *desc;
2348 struct gpmi_transfer *transfer;
2351 transfer = get_next_transfer(this);
2355 transfer->direction = DMA_TO_DEVICE;
2357 prepare_data_dma(this, buf, raw_len, &transfer->sgl, DMA_TO_DEVICE);
2359 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
2360 | BM_GPMI_CTRL0_WORD_LENGTH
2361 | BF_GPMI_CTRL0_CS(this->nand.cur_cs, this)
2362 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
2363 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
2364 | BF_GPMI_CTRL0_XFER_COUNT(raw_len);
2367 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
2368 | BF_GPMI_ECCCTRL_ECC_CMD(BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE)
2369 | BF_GPMI_ECCCTRL_BUFFER_MASK(BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
2370 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY);
2372 pio[4] = transfer->sgl.dma_address;
2373 pio[5] = this->auxiliary_phys;
2376 desc = mxs_dmaengine_prep_pio(channel, pio, ARRAY_SIZE(pio),
2378 (this->bch ? MXS_DMA_CTRL_WAIT4END : 0));
2383 desc = dmaengine_prep_slave_sg(channel, &transfer->sgl, 1,
2385 MXS_DMA_CTRL_WAIT4END);
2390 static int gpmi_nfc_exec_op(struct nand_chip *chip,
2391 const struct nand_operation *op,
2394 const struct nand_op_instr *instr;
2395 struct gpmi_nand_data *this = nand_get_controller_data(chip);
2396 struct dma_async_tx_descriptor *desc = NULL;
2397 int i, ret, buf_len = 0, nbufs = 0;
2399 void *buf_read = NULL;
2400 const void *buf_write = NULL;
2401 bool direct = false;
2402 struct completion *completion;
2405 this->ntransfers = 0;
2406 for (i = 0; i < GPMI_MAX_TRANSFERS; i++)
2407 this->transfers[i].direction = DMA_NONE;
2409 ret = pm_runtime_get_sync(this->dev);
2414 * This driver currently supports only one NAND chip. Plus, dies share
2415 * the same configuration. So once timings have been applied on the
2416 * controller side, they will not change anymore. When the time will
2417 * come, the check on must_apply_timings will have to be dropped.
2419 if (this->hw.must_apply_timings) {
2420 this->hw.must_apply_timings = false;
2421 gpmi_nfc_apply_timings(this);
2424 dev_dbg(this->dev, "%s: %d instructions\n", __func__, op->ninstrs);
2426 for (i = 0; i < op->ninstrs; i++) {
2427 instr = &op->instrs[i];
2429 nand_op_trace(" ", instr);
2431 switch (instr->type) {
2432 case NAND_OP_WAITRDY_INSTR:
2433 desc = gpmi_chain_wait_ready(this);
2435 case NAND_OP_CMD_INSTR:
2436 cmd = instr->ctx.cmd.opcode;
2439 * When this command has an address cycle chain it
2440 * together with the address cycle
2442 if (i + 1 != op->ninstrs &&
2443 op->instrs[i + 1].type == NAND_OP_ADDR_INSTR)
2446 desc = gpmi_chain_command(this, cmd, NULL, 0);
2449 case NAND_OP_ADDR_INSTR:
2450 desc = gpmi_chain_command(this, cmd, instr->ctx.addr.addrs,
2451 instr->ctx.addr.naddrs);
2453 case NAND_OP_DATA_OUT_INSTR:
2454 buf_write = instr->ctx.data.buf.out;
2455 buf_len = instr->ctx.data.len;
2458 desc = gpmi_chain_data_write(this, buf_write, buf_len);
2461 case NAND_OP_DATA_IN_INSTR:
2462 if (!instr->ctx.data.len)
2464 buf_read = instr->ctx.data.buf.in;
2465 buf_len = instr->ctx.data.len;
2468 desc = gpmi_chain_data_read(this, buf_read, buf_len,
2479 dev_dbg(this->dev, "%s setup done\n", __func__);
2482 dev_err(this->dev, "Multiple data instructions not supported\n");
2488 writel(this->bch_flashlayout0,
2489 this->resources.bch_regs + HW_BCH_FLASH0LAYOUT0);
2490 writel(this->bch_flashlayout1,
2491 this->resources.bch_regs + HW_BCH_FLASH0LAYOUT1);
2494 if (this->bch && buf_read) {
2495 writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
2496 this->resources.bch_regs + HW_BCH_CTRL_SET);
2497 completion = &this->bch_done;
2499 desc->callback = dma_irq_callback;
2500 desc->callback_param = this;
2501 completion = &this->dma_done;
2504 init_completion(completion);
2506 dmaengine_submit(desc);
2507 dma_async_issue_pending(get_dma_chan(this));
2509 to = wait_for_completion_timeout(completion, msecs_to_jiffies(1000));
2511 dev_err(this->dev, "DMA timeout, last DMA\n");
2512 gpmi_dump_info(this);
2517 writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
2518 this->resources.bch_regs + HW_BCH_CTRL_CLR);
2519 gpmi_clear_bch(this);
2524 for (i = 0; i < this->ntransfers; i++) {
2525 struct gpmi_transfer *transfer = &this->transfers[i];
2527 if (transfer->direction != DMA_NONE)
2528 dma_unmap_sg(this->dev, &transfer->sgl, 1,
2529 transfer->direction);
2532 if (!ret && buf_read && !direct)
2533 memcpy(buf_read, this->data_buffer_dma,
2534 gpmi_raw_len_to_len(this, buf_len));
2538 pm_runtime_mark_last_busy(this->dev);
2539 pm_runtime_put_autosuspend(this->dev);
2544 static const struct nand_controller_ops gpmi_nand_controller_ops = {
2545 .attach_chip = gpmi_nand_attach_chip,
2546 .setup_data_interface = gpmi_setup_data_interface,
2547 .exec_op = gpmi_nfc_exec_op,
2550 static int gpmi_nand_init(struct gpmi_nand_data *this)
2552 struct nand_chip *chip = &this->nand;
2553 struct mtd_info *mtd = nand_to_mtd(chip);
2556 /* init the MTD data structures */
2557 mtd->name = "gpmi-nand";
2558 mtd->dev.parent = this->dev;
2560 /* init the nand_chip{}, we don't support a 16-bit NAND Flash bus. */
2561 nand_set_controller_data(chip, this);
2562 nand_set_flash_node(chip, this->pdev->dev.of_node);
2563 chip->legacy.block_markbad = gpmi_block_markbad;
2564 chip->badblock_pattern = &gpmi_bbt_descr;
2565 chip->options |= NAND_NO_SUBPAGE_WRITE;
2567 /* Set up swap_block_mark, must be set before the gpmi_set_geometry() */
2568 this->swap_block_mark = !GPMI_IS_MX23(this);
2571 * Allocate a temporary DMA buffer for reading ID in the
2572 * nand_scan_ident().
2574 this->bch_geometry.payload_size = 1024;
2575 this->bch_geometry.auxiliary_size = 128;
2576 ret = gpmi_alloc_dma_buffer(this);
2580 nand_controller_init(&this->base);
2581 this->base.ops = &gpmi_nand_controller_ops;
2582 chip->controller = &this->base;
2584 ret = nand_scan(chip, GPMI_IS_MX6(this) ? 2 : 1);
2588 ret = nand_boot_init(this);
2590 goto err_nand_cleanup;
2591 ret = nand_create_bbt(chip);
2593 goto err_nand_cleanup;
2595 ret = mtd_device_register(mtd, NULL, 0);
2597 goto err_nand_cleanup;
2603 gpmi_free_dma_buffer(this);
2607 static const struct of_device_id gpmi_nand_id_table[] = {
2609 .compatible = "fsl,imx23-gpmi-nand",
2610 .data = &gpmi_devdata_imx23,
2612 .compatible = "fsl,imx28-gpmi-nand",
2613 .data = &gpmi_devdata_imx28,
2615 .compatible = "fsl,imx6q-gpmi-nand",
2616 .data = &gpmi_devdata_imx6q,
2618 .compatible = "fsl,imx6sx-gpmi-nand",
2619 .data = &gpmi_devdata_imx6sx,
2621 .compatible = "fsl,imx7d-gpmi-nand",
2622 .data = &gpmi_devdata_imx7d,
2625 MODULE_DEVICE_TABLE(of, gpmi_nand_id_table);
2627 static int gpmi_nand_probe(struct platform_device *pdev)
2629 struct gpmi_nand_data *this;
2630 const struct of_device_id *of_id;
2633 this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL);
2637 of_id = of_match_device(gpmi_nand_id_table, &pdev->dev);
2639 this->devdata = of_id->data;
2641 dev_err(&pdev->dev, "Failed to find the right device id.\n");
2645 platform_set_drvdata(pdev, this);
2647 this->dev = &pdev->dev;
2649 ret = acquire_resources(this);
2651 goto exit_acquire_resources;
2653 ret = __gpmi_enable_clk(this, true);
2657 pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
2658 pm_runtime_use_autosuspend(&pdev->dev);
2659 pm_runtime_set_active(&pdev->dev);
2660 pm_runtime_enable(&pdev->dev);
2661 pm_runtime_get_sync(&pdev->dev);
2663 ret = gpmi_init(this);
2667 ret = gpmi_nand_init(this);
2671 pm_runtime_mark_last_busy(&pdev->dev);
2672 pm_runtime_put_autosuspend(&pdev->dev);
2674 dev_info(this->dev, "driver registered.\n");
2679 pm_runtime_put(&pdev->dev);
2680 pm_runtime_disable(&pdev->dev);
2681 release_resources(this);
2682 exit_acquire_resources:
2687 static int gpmi_nand_remove(struct platform_device *pdev)
2689 struct gpmi_nand_data *this = platform_get_drvdata(pdev);
2691 pm_runtime_put_sync(&pdev->dev);
2692 pm_runtime_disable(&pdev->dev);
2694 nand_release(&this->nand);
2695 gpmi_free_dma_buffer(this);
2696 release_resources(this);
2700 #ifdef CONFIG_PM_SLEEP
2701 static int gpmi_pm_suspend(struct device *dev)
2703 struct gpmi_nand_data *this = dev_get_drvdata(dev);
2705 release_dma_channels(this);
2709 static int gpmi_pm_resume(struct device *dev)
2711 struct gpmi_nand_data *this = dev_get_drvdata(dev);
2714 ret = acquire_dma_channels(this);
2718 /* re-init the GPMI registers */
2719 ret = gpmi_init(this);
2721 dev_err(this->dev, "Error setting GPMI : %d\n", ret);
2725 /* re-init the BCH registers */
2726 ret = bch_set_geometry(this);
2728 dev_err(this->dev, "Error setting BCH : %d\n", ret);
2734 #endif /* CONFIG_PM_SLEEP */
2736 static int __maybe_unused gpmi_runtime_suspend(struct device *dev)
2738 struct gpmi_nand_data *this = dev_get_drvdata(dev);
2740 return __gpmi_enable_clk(this, false);
2743 static int __maybe_unused gpmi_runtime_resume(struct device *dev)
2745 struct gpmi_nand_data *this = dev_get_drvdata(dev);
2747 return __gpmi_enable_clk(this, true);
2750 static const struct dev_pm_ops gpmi_pm_ops = {
2751 SET_SYSTEM_SLEEP_PM_OPS(gpmi_pm_suspend, gpmi_pm_resume)
2752 SET_RUNTIME_PM_OPS(gpmi_runtime_suspend, gpmi_runtime_resume, NULL)
2755 static struct platform_driver gpmi_nand_driver = {
2757 .name = "gpmi-nand",
2759 .of_match_table = gpmi_nand_id_table,
2761 .probe = gpmi_nand_probe,
2762 .remove = gpmi_nand_remove,
2764 module_platform_driver(gpmi_nand_driver);
2766 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
2767 MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");
2768 MODULE_LICENSE("GPL");