1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
10 #include <linux/ioport.h>
11 #include <linux/printk.h>
16 struct denali_dt_data {
17 unsigned int revision;
19 unsigned int oob_skip_bytes;
20 const struct nand_ecc_caps *ecc_caps;
23 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
25 static const struct denali_dt_data denali_socfpga_data = {
26 .caps = DENALI_CAP_HW_ECC_FIXUP,
28 .ecc_caps = &denali_socfpga_ecc_caps,
31 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
33 static const struct denali_dt_data denali_uniphier_v5a_data = {
34 .caps = DENALI_CAP_HW_ECC_FIXUP |
37 .ecc_caps = &denali_uniphier_v5a_ecc_caps,
40 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
42 static const struct denali_dt_data denali_uniphier_v5b_data = {
44 .caps = DENALI_CAP_HW_ECC_FIXUP |
47 .ecc_caps = &denali_uniphier_v5b_ecc_caps,
50 static const struct udevice_id denali_nand_dt_ids[] = {
52 .compatible = "altr,socfpga-denali-nand",
53 .data = (unsigned long)&denali_socfpga_data,
56 .compatible = "socionext,uniphier-denali-nand-v5a",
57 .data = (unsigned long)&denali_uniphier_v5a_data,
60 .compatible = "socionext,uniphier-denali-nand-v5b",
61 .data = (unsigned long)&denali_uniphier_v5b_data,
66 static int denali_dt_probe(struct udevice *dev)
68 struct denali_nand_info *denali = dev_get_priv(dev);
69 const struct denali_dt_data *data;
70 struct clk clk, clk_x, clk_ecc;
71 struct reset_ctl_bulk resets;
75 data = (void *)dev_get_driver_data(dev);
79 denali->revision = data->revision;
80 denali->caps = data->caps;
81 denali->oob_skip_bytes = data->oob_skip_bytes;
82 denali->ecc_caps = data->ecc_caps;
86 ret = dev_read_resource_byname(dev, "denali_reg", &res);
90 denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
92 ret = dev_read_resource_byname(dev, "nand_data", &res);
96 denali->host = devm_ioremap(dev, res.start, resource_size(&res));
98 ret = clk_get_by_name(dev, "nand", &clk);
100 ret = clk_get_by_index(dev, 0, &clk);
104 ret = clk_get_by_name(dev, "nand_x", &clk_x);
108 ret = clk_get_by_name(dev, "ecc", &clk_ecc);
113 ret = clk_enable(&clk);
119 ret = clk_enable(&clk_x);
125 ret = clk_enable(&clk_ecc);
131 denali->clk_rate = clk_get_rate(&clk);
132 denali->clk_x_rate = clk_get_rate(&clk_x);
135 * Hardcode the clock rates for the backward compatibility.
136 * This works for both SOCFPGA and UniPhier.
139 "necessary clock is missing. default clock rates are used.\n");
140 denali->clk_rate = 50000000;
141 denali->clk_x_rate = 200000000;
144 ret = reset_get_bulk(dev, &resets);
146 dev_warn(dev, "Can't get reset: %d\n", ret);
148 reset_deassert_bulk(&resets);
151 * When the reset is deasserted, the initialization sequence is
152 * kicked (bootstrap process). The driver must wait until it is
153 * finished. Otherwise, it will result in unpredictable behavior.
158 return denali_init(denali);
161 U_BOOT_DRIVER(denali_nand_dt) = {
162 .name = "denali-nand-dt",
164 .of_match = denali_nand_dt_ids,
165 .probe = denali_dt_probe,
166 .priv_auto_alloc_size = sizeof(struct denali_nand_info),
169 void board_nand_init(void)
174 ret = uclass_get_device_by_driver(UCLASS_MISC,
175 DM_GET_DRIVER(denali_nand_dt),
177 if (ret && ret != -ENODEV)
178 pr_err("Failed to initialize Denali NAND controller. (error %d)\n",