drivers/mtd/nand/raw/denali_dt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Socionext Inc.
   4  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   5  */
   6
   7 #include <clk.h>
   8 #include <dm.h>
   9 #include <dm/device_compat.h>
  10 #include <linux/io.h>
  11 #include <linux/ioport.h>
  12 #include <linux/printk.h>
  13 #include <reset.h>
  14
  15 #include "denali.h"
  16
  17 struct denali_dt_data {
  18         unsigned int revision;
  19         unsigned int caps;
  20         unsigned int oob_skip_bytes;
  21         const struct nand_ecc_caps *ecc_caps;
  22 };
  23
  24 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
  25                      512, 8, 15);
  26 static const struct denali_dt_data denali_socfpga_data = {
  27         .caps = DENALI_CAP_HW_ECC_FIXUP,
  28         .oob_skip_bytes = 2,
  29         .ecc_caps = &denali_socfpga_ecc_caps,
  30 };
  31
  32 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
  33                      1024, 8, 16, 24);
  34 static const struct denali_dt_data denali_uniphier_v5a_data = {
  35         .caps = DENALI_CAP_HW_ECC_FIXUP |
  36                 DENALI_CAP_DMA_64BIT,
  37         .oob_skip_bytes = 8,
  38         .ecc_caps = &denali_uniphier_v5a_ecc_caps,
  39 };
  40
  41 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
  42                      1024, 8, 16);
  43 static const struct denali_dt_data denali_uniphier_v5b_data = {
  44         .revision = 0x0501,
  45         .caps = DENALI_CAP_HW_ECC_FIXUP |
  46                 DENALI_CAP_DMA_64BIT,
  47         .oob_skip_bytes = 8,
  48         .ecc_caps = &denali_uniphier_v5b_ecc_caps,
  49 };
  50
  51 static const struct udevice_id denali_nand_dt_ids[] = {
  52         {
  53                 .compatible = "altr,socfpga-denali-nand",
  54                 .data = (unsigned long)&denali_socfpga_data,
  55         },
  56         {
  57                 .compatible = "socionext,uniphier-denali-nand-v5a",
  58                 .data = (unsigned long)&denali_uniphier_v5a_data,
  59         },
  60         {
  61                 .compatible = "socionext,uniphier-denali-nand-v5b",
  62                 .data = (unsigned long)&denali_uniphier_v5b_data,
  63         },
  64         { /* sentinel */ }
  65 };
  66
  67 static int denali_dt_probe(struct udevice *dev)
  68 {
  69         struct denali_nand_info *denali = dev_get_priv(dev);
  70         const struct denali_dt_data *data;
  71         struct clk clk, clk_x, clk_ecc;
  72         struct reset_ctl_bulk resets;
  73         struct resource res;
  74         int ret;
  75
  76         data = (void *)dev_get_driver_data(dev);
  77         if (WARN_ON(!data))
  78                 return -EINVAL;
  79
  80         denali->revision = data->revision;
  81         denali->caps = data->caps;
  82         denali->oob_skip_bytes = data->oob_skip_bytes;
  83         denali->ecc_caps = data->ecc_caps;
  84
  85         denali->dev = dev;
  86
  87         ret = dev_read_resource_byname(dev, "denali_reg", &res);
  88         if (ret)
  89                 return ret;
  90
  91         denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
  92
  93         ret = dev_read_resource_byname(dev, "nand_data", &res);
  94         if (ret)
  95                 return ret;
  96
  97         denali->host = devm_ioremap(dev, res.start, resource_size(&res));
  98
  99         ret = clk_get_by_name(dev, "nand", &clk);
 100         if (ret)
 101                 ret = clk_get_by_index(dev, 0, &clk);
 102         if (ret)
 103                 clk.dev = NULL;
 104
 105         ret = clk_get_by_name(dev, "nand_x", &clk_x);
 106         if (ret)
 107                 clk_x.dev = NULL;
 108
 109         ret = clk_get_by_name(dev, "ecc", &clk_ecc);
 110         if (ret)
 111                 clk_ecc.dev = NULL;
 112
 113         if (clk.dev) {
 114                 ret = clk_enable(&clk);
 115                 if (ret)
 116                         return ret;
 117         }
 118
 119         if (clk_x.dev) {
 120                 ret = clk_enable(&clk_x);
 121                 if (ret)
 122                         return ret;
 123         }
 124
 125         if (clk_ecc.dev) {
 126                 ret = clk_enable(&clk_ecc);
 127                 if (ret)
 128                         return ret;
 129         }
 130
 131         if (clk_x.dev) {
 132                 denali->clk_rate = clk_get_rate(&clk);
 133                 denali->clk_x_rate = clk_get_rate(&clk_x);
 134         } else {
 135                 /*
 136                  * Hardcode the clock rates for the backward compatibility.
 137                  * This works for both SOCFPGA and UniPhier.
 138                  */
 139                 dev_notice(dev,
 140                            "necessary clock is missing. default clock rates are used.\n");
 141                 denali->clk_rate = 50000000;
 142                 denali->clk_x_rate = 200000000;
 143         }
 144
 145         ret = reset_get_bulk(dev, &resets);
 146         if (ret) {
 147                 dev_warn(dev, "Can't get reset: %d\n", ret);
 148         } else {
 149                 reset_deassert_bulk(&resets);
 150
 151                 /*
 152                  * When the reset is deasserted, the initialization sequence is
 153                  * kicked (bootstrap process). The driver must wait until it is
 154                  * finished. Otherwise, it will result in unpredictable behavior.
 155                  */
 156                 udelay(200);
 157         }
 158
 159         return denali_init(denali);
 160 }
 161
 162 U_BOOT_DRIVER(denali_nand_dt) = {
 163         .name = "denali-nand-dt",
 164         .id = UCLASS_MTD,
 165         .of_match = denali_nand_dt_ids,
 166         .probe = denali_dt_probe,
 167         .priv_auto_alloc_size = sizeof(struct denali_nand_info),
 168 };
 169
 170 void board_nand_init(void)
 171 {
 172         struct udevice *dev;
 173         int ret;
 174
 175         ret = uclass_get_device_by_driver(UCLASS_MTD,
 176                                           DM_GET_DRIVER(denali_nand_dt),
 177                                           &dev);
 178         if (ret && ret != -ENODEV)
 179                 pr_err("Failed to initialize Denali NAND controller. (error %d)\n",
 180                        ret);
 181 }