1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
10 #include <linux/ioport.h>
11 #include <linux/printk.h>
16 struct denali_dt_data {
17 unsigned int revision;
19 const struct nand_ecc_caps *ecc_caps;
22 NAND_ECC_CAPS_SINGLE(denali_socfpga_ecc_caps, denali_calc_ecc_bytes,
24 static const struct denali_dt_data denali_socfpga_data = {
25 .caps = DENALI_CAP_HW_ECC_FIXUP,
26 .ecc_caps = &denali_socfpga_ecc_caps,
29 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5a_ecc_caps, denali_calc_ecc_bytes,
31 static const struct denali_dt_data denali_uniphier_v5a_data = {
32 .caps = DENALI_CAP_HW_ECC_FIXUP |
34 .ecc_caps = &denali_uniphier_v5a_ecc_caps,
37 NAND_ECC_CAPS_SINGLE(denali_uniphier_v5b_ecc_caps, denali_calc_ecc_bytes,
39 static const struct denali_dt_data denali_uniphier_v5b_data = {
41 .caps = DENALI_CAP_HW_ECC_FIXUP |
43 .ecc_caps = &denali_uniphier_v5b_ecc_caps,
46 static const struct udevice_id denali_nand_dt_ids[] = {
48 .compatible = "altr,socfpga-denali-nand",
49 .data = (unsigned long)&denali_socfpga_data,
52 .compatible = "socionext,uniphier-denali-nand-v5a",
53 .data = (unsigned long)&denali_uniphier_v5a_data,
56 .compatible = "socionext,uniphier-denali-nand-v5b",
57 .data = (unsigned long)&denali_uniphier_v5b_data,
62 static int denali_dt_probe(struct udevice *dev)
64 struct denali_nand_info *denali = dev_get_priv(dev);
65 const struct denali_dt_data *data;
66 struct clk clk, clk_x, clk_ecc;
67 struct reset_ctl_bulk resets;
71 data = (void *)dev_get_driver_data(dev);
73 denali->revision = data->revision;
74 denali->caps = data->caps;
75 denali->ecc_caps = data->ecc_caps;
80 ret = dev_read_resource_byname(dev, "denali_reg", &res);
84 denali->reg = devm_ioremap(dev, res.start, resource_size(&res));
86 ret = dev_read_resource_byname(dev, "nand_data", &res);
90 denali->host = devm_ioremap(dev, res.start, resource_size(&res));
92 ret = clk_get_by_name(dev, "nand", &clk);
94 ret = clk_get_by_index(dev, 0, &clk);
98 ret = clk_get_by_name(dev, "nand_x", &clk_x);
102 ret = clk_get_by_name(dev, "ecc", &clk_ecc);
107 ret = clk_enable(&clk);
113 ret = clk_enable(&clk_x);
119 ret = clk_enable(&clk_ecc);
125 denali->clk_rate = clk_get_rate(&clk);
126 denali->clk_x_rate = clk_get_rate(&clk_x);
129 * Hardcode the clock rates for the backward compatibility.
130 * This works for both SOCFPGA and UniPhier.
133 "necessary clock is missing. default clock rates are used.\n");
134 denali->clk_rate = 50000000;
135 denali->clk_x_rate = 200000000;
138 ret = reset_get_bulk(dev, &resets);
140 dev_warn(dev, "Can't get reset: %d\n", ret);
142 reset_deassert_bulk(&resets);
145 * When the reset is deasserted, the initialization sequence is
146 * kicked (bootstrap process). The driver must wait until it is
147 * finished. Otherwise, it will result in unpredictable behavior.
152 return denali_init(denali);
155 U_BOOT_DRIVER(denali_nand_dt) = {
156 .name = "denali-nand-dt",
158 .of_match = denali_nand_dt_ids,
159 .probe = denali_dt_probe,
160 .priv_auto_alloc_size = sizeof(struct denali_nand_info),
163 void board_nand_init(void)
168 ret = uclass_get_device_by_driver(UCLASS_MISC,
169 DM_GET_DRIVER(denali_nand_dt),
171 if (ret && ret != -ENODEV)
172 pr_err("Failed to initialize Denali NAND controller. (error %d)\n",