1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Panasonic Corporation
4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
10 #include <linux/bitfield.h>
11 #include <linux/dma-direction.h>
12 #include <linux/errno.h>
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/rawnand.h>
19 static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size,
20 enum dma_data_direction dir)
22 unsigned long addr = (unsigned long)ptr;
24 size = ALIGN(size, ARCH_DMA_MINALIGN);
26 if (dir == DMA_FROM_DEVICE)
27 invalidate_dcache_range(addr, addr + size);
29 flush_dcache_range(addr, addr + size);
34 static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size,
35 enum dma_data_direction dir)
37 size = ALIGN(size, ARCH_DMA_MINALIGN);
39 if (dir != DMA_TO_DEVICE)
40 invalidate_dcache_range(addr, addr + size);
43 static int dma_mapping_error(void *dev, dma_addr_t addr)
48 #define DENALI_NAND_NAME "denali-nand"
50 /* for Indexed Addressing */
51 #define DENALI_INDEXED_CTRL 0x00
52 #define DENALI_INDEXED_DATA 0x10
54 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
55 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
56 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
57 #define DENALI_MAP11 (3 << 26) /* direct controller access */
59 /* MAP11 access cycle type */
60 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
61 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
62 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
65 #define DENALI_ERASE 0x01
67 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
69 #define DENALI_INVALID_BANK -1
70 #define DENALI_NR_BANKS 4
73 * The bus interface clock, clk_x, is phase aligned with the core clock. The
74 * clk_x is an integral multiple N of the core clk. The value N is configured
75 * at IP delivery time, and its available value is 4, 5, or 6. We need to align
76 * to the largest value to make it work with any possible configuration.
78 #define DENALI_CLK_X_MULT 6
80 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
82 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
86 * Direct Addressing - the slave address forms the control information (command
87 * type, bank, block, and page address). The slave data is the actual data to
88 * be transferred. This mode requires 28 bits of address region allocated.
90 static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
92 return ioread32(denali->host + addr);
95 static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
98 iowrite32(data, denali->host + addr);
102 * Indexed Addressing - address translation module intervenes in passing the
103 * control information. This mode reduces the required address range. The
104 * control information and transferred data are latched by the registers in
105 * the translation module.
107 static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
109 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
110 return ioread32(denali->host + DENALI_INDEXED_DATA);
113 static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
116 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
117 iowrite32(data, denali->host + DENALI_INDEXED_DATA);
121 * Use the configuration feature register to determine the maximum number of
122 * banks that the hardware supports.
124 static void denali_detect_max_banks(struct denali_nand_info *denali)
126 uint32_t features = ioread32(denali->reg + FEATURES);
128 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
130 /* the encoding changed from rev 5.0 to 5.1 */
131 if (denali->revision < 0x0501)
132 denali->max_banks <<= 1;
135 static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali)
139 for (i = 0; i < DENALI_NR_BANKS; i++)
140 iowrite32(U32_MAX, denali->reg + INTR_EN(i));
141 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
144 static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali)
148 for (i = 0; i < DENALI_NR_BANKS; i++)
149 iowrite32(0, denali->reg + INTR_EN(i));
150 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
153 static void denali_clear_irq(struct denali_nand_info *denali,
154 int bank, uint32_t irq_status)
156 /* write one to clear bits */
157 iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
160 static void denali_clear_irq_all(struct denali_nand_info *denali)
164 for (i = 0; i < DENALI_NR_BANKS; i++)
165 denali_clear_irq(denali, i, U32_MAX);
168 static void __denali_check_irq(struct denali_nand_info *denali)
173 for (i = 0; i < DENALI_NR_BANKS; i++) {
174 irq_status = ioread32(denali->reg + INTR_STATUS(i));
175 denali_clear_irq(denali, i, irq_status);
177 if (i != denali->active_bank)
180 denali->irq_status |= irq_status;
184 static void denali_reset_irq(struct denali_nand_info *denali)
186 denali->irq_status = 0;
187 denali->irq_mask = 0;
190 static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
193 unsigned long time_left = 1000000;
196 __denali_check_irq(denali);
198 if (irq_mask & denali->irq_status)
199 return denali->irq_status;
205 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
210 return denali->irq_status;
213 static uint32_t denali_check_irq(struct denali_nand_info *denali)
215 __denali_check_irq(denali);
217 return denali->irq_status;
220 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
222 struct denali_nand_info *denali = mtd_to_denali(mtd);
223 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
226 for (i = 0; i < len; i++)
227 buf[i] = denali->host_read(denali, addr);
230 static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
232 struct denali_nand_info *denali = mtd_to_denali(mtd);
233 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
236 for (i = 0; i < len; i++)
237 denali->host_write(denali, addr, buf[i]);
240 static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
242 struct denali_nand_info *denali = mtd_to_denali(mtd);
243 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
244 uint16_t *buf16 = (uint16_t *)buf;
247 for (i = 0; i < len / 2; i++)
248 buf16[i] = denali->host_read(denali, addr);
251 static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
254 struct denali_nand_info *denali = mtd_to_denali(mtd);
255 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
256 const uint16_t *buf16 = (const uint16_t *)buf;
259 for (i = 0; i < len / 2; i++)
260 denali->host_write(denali, addr, buf16[i]);
263 static uint8_t denali_read_byte(struct mtd_info *mtd)
267 denali_read_buf(mtd, &byte, 1);
272 static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
274 denali_write_buf(mtd, &byte, 1);
277 static uint16_t denali_read_word(struct mtd_info *mtd)
281 denali_read_buf16(mtd, (uint8_t *)&word, 2);
286 static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
288 struct denali_nand_info *denali = mtd_to_denali(mtd);
292 type = DENALI_MAP11_CMD;
293 else if (ctrl & NAND_ALE)
294 type = DENALI_MAP11_ADDR;
299 * Some commands are followed by chip->dev_ready or chip->waitfunc.
300 * irq_status must be cleared here to catch the R/B# interrupt later.
302 if (ctrl & NAND_CTRL_CHANGE)
303 denali_reset_irq(denali);
305 denali->host_write(denali, DENALI_BANK(denali) | type, dat);
308 static int denali_dev_ready(struct mtd_info *mtd)
310 struct denali_nand_info *denali = mtd_to_denali(mtd);
312 return !!(denali_check_irq(denali) & INTR__INT_ACT);
315 static int denali_check_erased_page(struct mtd_info *mtd,
316 struct nand_chip *chip, uint8_t *buf,
317 unsigned long uncor_ecc_flags,
318 unsigned int max_bitflips)
320 uint8_t *ecc_code = chip->buffers->ecccode;
321 int ecc_steps = chip->ecc.steps;
322 int ecc_size = chip->ecc.size;
323 int ecc_bytes = chip->ecc.bytes;
326 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
331 for (i = 0; i < ecc_steps; i++) {
332 if (!(uncor_ecc_flags & BIT(i)))
335 stat = nand_check_erased_ecc_chunk(buf, ecc_size,
340 mtd->ecc_stats.failed++;
342 mtd->ecc_stats.corrected += stat;
343 max_bitflips = max_t(unsigned int, max_bitflips, stat);
347 ecc_code += ecc_bytes;
353 static int denali_hw_ecc_fixup(struct mtd_info *mtd,
354 struct denali_nand_info *denali,
355 unsigned long *uncor_ecc_flags)
357 struct nand_chip *chip = mtd_to_nand(mtd);
358 int bank = denali->active_bank;
360 unsigned int max_bitflips;
362 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
363 ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
365 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
367 * This flag is set when uncorrectable error occurs at least in
368 * one ECC sector. We can not know "how many sectors", or
369 * "which sector(s)". We need erase-page check for all sectors.
371 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
375 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
378 * The register holds the maximum of per-sector corrected bitflips.
379 * This is suitable for the return value of the ->read_page() callback.
380 * Unfortunately, we can not know the total number of corrected bits in
381 * the page. Increase the stats by max_bitflips. (compromised solution)
383 mtd->ecc_stats.corrected += max_bitflips;
388 static int denali_sw_ecc_fixup(struct mtd_info *mtd,
389 struct denali_nand_info *denali,
390 unsigned long *uncor_ecc_flags, uint8_t *buf)
392 unsigned int ecc_size = denali->nand.ecc.size;
393 unsigned int bitflips = 0;
394 unsigned int max_bitflips = 0;
395 uint32_t err_addr, err_cor_info;
396 unsigned int err_byte, err_sector, err_device;
397 uint8_t err_cor_value;
398 unsigned int prev_sector = 0;
401 denali_reset_irq(denali);
404 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
405 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
406 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
408 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
409 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
411 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
414 /* reset the bitflip counter when crossing ECC sector */
415 if (err_sector != prev_sector)
418 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
420 * Check later if this is a real ECC error, or
423 *uncor_ecc_flags |= BIT(err_sector);
424 } else if (err_byte < ecc_size) {
426 * If err_byte is larger than ecc_size, means error
427 * happened in OOB, so we ignore it. It's no need for
428 * us to correct it err_device is represented the NAND
429 * error bits are happened in if there are more than
430 * one NAND connected.
433 unsigned int flips_in_byte;
435 offset = (err_sector * ecc_size + err_byte) *
436 denali->devs_per_cs + err_device;
438 /* correct the ECC error */
439 flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
440 buf[offset] ^= err_cor_value;
441 mtd->ecc_stats.corrected += flips_in_byte;
442 bitflips += flips_in_byte;
444 max_bitflips = max(max_bitflips, bitflips);
447 prev_sector = err_sector;
448 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
451 * Once handle all ECC errors, controller will trigger an
452 * ECC_TRANSACTION_DONE interrupt.
454 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
455 if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
461 static void denali_setup_dma64(struct denali_nand_info *denali,
462 dma_addr_t dma_addr, int page, int write)
465 const int page_count = 1;
467 mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
469 /* DMA is a three step process */
472 * 1. setup transfer type, interrupt when complete,
473 * burst len = 64 bytes, the number of pages
475 denali->host_write(denali, mode,
476 0x01002000 | (64 << 16) | (write << 8) | page_count);
478 /* 2. set memory low address */
479 denali->host_write(denali, mode, lower_32_bits(dma_addr));
481 /* 3. set memory high address */
482 denali->host_write(denali, mode, upper_32_bits(dma_addr));
485 static void denali_setup_dma32(struct denali_nand_info *denali,
486 dma_addr_t dma_addr, int page, int write)
489 const int page_count = 1;
491 mode = DENALI_MAP10 | DENALI_BANK(denali);
493 /* DMA is a four step process */
495 /* 1. setup transfer type and # of pages */
496 denali->host_write(denali, mode | page,
497 0x2000 | (write << 8) | page_count);
499 /* 2. set memory high address bits 23:8 */
500 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
502 /* 3. set memory low address bits 23:8 */
503 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
505 /* 4. interrupt when complete, burst len = 64 bytes */
506 denali->host_write(denali, mode | 0x14000, 0x2400);
509 static int denali_pio_read(struct denali_nand_info *denali, void *buf,
510 size_t size, int page, int raw)
512 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
513 uint32_t *buf32 = (uint32_t *)buf;
514 uint32_t irq_status, ecc_err_mask;
517 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
518 ecc_err_mask = INTR__ECC_UNCOR_ERR;
520 ecc_err_mask = INTR__ECC_ERR;
522 denali_reset_irq(denali);
524 for (i = 0; i < size / 4; i++)
525 *buf32++ = denali->host_read(denali, addr);
527 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
528 if (!(irq_status & INTR__PAGE_XFER_INC))
531 if (irq_status & INTR__ERASED_PAGE)
532 memset(buf, 0xff, size);
534 return irq_status & ecc_err_mask ? -EBADMSG : 0;
537 static int denali_pio_write(struct denali_nand_info *denali,
538 const void *buf, size_t size, int page, int raw)
540 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
541 const uint32_t *buf32 = (uint32_t *)buf;
545 denali_reset_irq(denali);
547 for (i = 0; i < size / 4; i++)
548 denali->host_write(denali, addr, *buf32++);
550 irq_status = denali_wait_for_irq(denali,
551 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
552 if (!(irq_status & INTR__PROGRAM_COMP))
558 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
559 size_t size, int page, int raw, int write)
562 return denali_pio_write(denali, buf, size, page, raw);
564 return denali_pio_read(denali, buf, size, page, raw);
567 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
568 size_t size, int page, int raw, int write)
571 uint32_t irq_mask, irq_status, ecc_err_mask;
572 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
575 dma_addr = dma_map_single(denali->dev, buf, size, dir);
576 if (dma_mapping_error(denali->dev, dma_addr)) {
577 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
578 return denali_pio_xfer(denali, buf, size, page, raw, write);
583 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
584 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
585 * when the page program is completed.
587 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
589 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
590 irq_mask = INTR__DMA_CMD_COMP;
591 ecc_err_mask = INTR__ECC_UNCOR_ERR;
593 irq_mask = INTR__DMA_CMD_COMP;
594 ecc_err_mask = INTR__ECC_ERR;
597 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
599 denali_reset_irq(denali);
600 denali->setup_dma(denali, dma_addr, page, write);
602 irq_status = denali_wait_for_irq(denali, irq_mask);
603 if (!(irq_status & INTR__DMA_CMD_COMP))
605 else if (irq_status & ecc_err_mask)
608 iowrite32(0, denali->reg + DMA_ENABLE);
610 dma_unmap_single(denali->dev, dma_addr, size, dir);
612 if (irq_status & INTR__ERASED_PAGE)
613 memset(buf, 0xff, size);
618 static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
619 size_t size, int page, int raw, int write)
621 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
622 iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
623 denali->reg + TRANSFER_SPARE_REG);
625 if (denali->dma_avail)
626 return denali_dma_xfer(denali, buf, size, page, raw, write);
628 return denali_pio_xfer(denali, buf, size, page, raw, write);
631 static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
634 struct denali_nand_info *denali = mtd_to_denali(mtd);
635 unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
636 unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
637 int writesize = mtd->writesize;
638 int oobsize = mtd->oobsize;
639 uint8_t *bufpoi = chip->oob_poi;
640 int ecc_steps = chip->ecc.steps;
641 int ecc_size = chip->ecc.size;
642 int ecc_bytes = chip->ecc.bytes;
643 int oob_skip = denali->oob_skip_bytes;
644 size_t size = writesize + oobsize;
647 /* BBM at the beginning of the OOB area */
648 chip->cmdfunc(mtd, start_cmd, writesize, page);
650 chip->write_buf(mtd, bufpoi, oob_skip);
652 chip->read_buf(mtd, bufpoi, oob_skip);
656 for (i = 0; i < ecc_steps; i++) {
657 pos = ecc_size + i * (ecc_size + ecc_bytes);
660 if (pos >= writesize)
662 else if (pos + len > writesize)
663 len = writesize - pos;
665 chip->cmdfunc(mtd, rnd_cmd, pos, -1);
667 chip->write_buf(mtd, bufpoi, len);
669 chip->read_buf(mtd, bufpoi, len);
671 if (len < ecc_bytes) {
672 len = ecc_bytes - len;
673 chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
675 chip->write_buf(mtd, bufpoi, len);
677 chip->read_buf(mtd, bufpoi, len);
683 len = oobsize - (bufpoi - chip->oob_poi);
684 chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
686 chip->write_buf(mtd, bufpoi, len);
688 chip->read_buf(mtd, bufpoi, len);
691 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
692 uint8_t *buf, int oob_required, int page)
694 struct denali_nand_info *denali = mtd_to_denali(mtd);
695 int writesize = mtd->writesize;
696 int oobsize = mtd->oobsize;
697 int ecc_steps = chip->ecc.steps;
698 int ecc_size = chip->ecc.size;
699 int ecc_bytes = chip->ecc.bytes;
700 void *tmp_buf = denali->buf;
701 int oob_skip = denali->oob_skip_bytes;
702 size_t size = writesize + oobsize;
703 int ret, i, pos, len;
705 ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0);
709 /* Arrange the buffer for syndrome payload/ecc layout */
711 for (i = 0; i < ecc_steps; i++) {
712 pos = i * (ecc_size + ecc_bytes);
715 if (pos >= writesize)
717 else if (pos + len > writesize)
718 len = writesize - pos;
720 memcpy(buf, tmp_buf + pos, len);
722 if (len < ecc_size) {
723 len = ecc_size - len;
724 memcpy(buf, tmp_buf + writesize + oob_skip,
732 uint8_t *oob = chip->oob_poi;
734 /* BBM at the beginning of the OOB area */
735 memcpy(oob, tmp_buf + writesize, oob_skip);
739 for (i = 0; i < ecc_steps; i++) {
740 pos = ecc_size + i * (ecc_size + ecc_bytes);
743 if (pos >= writesize)
745 else if (pos + len > writesize)
746 len = writesize - pos;
748 memcpy(oob, tmp_buf + pos, len);
750 if (len < ecc_bytes) {
751 len = ecc_bytes - len;
752 memcpy(oob, tmp_buf + writesize + oob_skip,
759 len = oobsize - (oob - chip->oob_poi);
760 memcpy(oob, tmp_buf + size - len, len);
766 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
769 denali_oob_xfer(mtd, chip, page, 0);
774 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
777 struct denali_nand_info *denali = mtd_to_denali(mtd);
780 denali_reset_irq(denali);
782 denali_oob_xfer(mtd, chip, page, 1);
784 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
785 status = chip->waitfunc(mtd, chip);
787 return status & NAND_STATUS_FAIL ? -EIO : 0;
790 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
791 uint8_t *buf, int oob_required, int page)
793 struct denali_nand_info *denali = mtd_to_denali(mtd);
794 unsigned long uncor_ecc_flags = 0;
798 ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
799 if (ret && ret != -EBADMSG)
802 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
803 stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
804 else if (ret == -EBADMSG)
805 stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
810 if (uncor_ecc_flags) {
811 ret = denali_read_oob(mtd, chip, page);
815 stat = denali_check_erased_page(mtd, chip, buf,
816 uncor_ecc_flags, stat);
822 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
823 const uint8_t *buf, int oob_required, int page)
825 struct denali_nand_info *denali = mtd_to_denali(mtd);
826 int writesize = mtd->writesize;
827 int oobsize = mtd->oobsize;
828 int ecc_steps = chip->ecc.steps;
829 int ecc_size = chip->ecc.size;
830 int ecc_bytes = chip->ecc.bytes;
831 void *tmp_buf = denali->buf;
832 int oob_skip = denali->oob_skip_bytes;
833 size_t size = writesize + oobsize;
837 * Fill the buffer with 0xff first except the full page transfer.
838 * This simplifies the logic.
840 if (!buf || !oob_required)
841 memset(tmp_buf, 0xff, size);
843 /* Arrange the buffer for syndrome payload/ecc layout */
845 for (i = 0; i < ecc_steps; i++) {
846 pos = i * (ecc_size + ecc_bytes);
849 if (pos >= writesize)
851 else if (pos + len > writesize)
852 len = writesize - pos;
854 memcpy(tmp_buf + pos, buf, len);
856 if (len < ecc_size) {
857 len = ecc_size - len;
858 memcpy(tmp_buf + writesize + oob_skip, buf,
866 const uint8_t *oob = chip->oob_poi;
868 /* BBM at the beginning of the OOB area */
869 memcpy(tmp_buf + writesize, oob, oob_skip);
873 for (i = 0; i < ecc_steps; i++) {
874 pos = ecc_size + i * (ecc_size + ecc_bytes);
877 if (pos >= writesize)
879 else if (pos + len > writesize)
880 len = writesize - pos;
882 memcpy(tmp_buf + pos, oob, len);
884 if (len < ecc_bytes) {
885 len = ecc_bytes - len;
886 memcpy(tmp_buf + writesize + oob_skip, oob,
893 len = oobsize - (oob - chip->oob_poi);
894 memcpy(tmp_buf + size - len, oob, len);
897 return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
900 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
901 const uint8_t *buf, int oob_required, int page)
903 struct denali_nand_info *denali = mtd_to_denali(mtd);
905 return denali_data_xfer(denali, (void *)buf, mtd->writesize,
909 static void denali_select_chip(struct mtd_info *mtd, int chip)
911 struct denali_nand_info *denali = mtd_to_denali(mtd);
913 denali->active_bank = chip;
916 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
918 struct denali_nand_info *denali = mtd_to_denali(mtd);
921 /* R/B# pin transitioned from low to high? */
922 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
924 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
927 static int denali_erase(struct mtd_info *mtd, int page)
929 struct denali_nand_info *denali = mtd_to_denali(mtd);
932 denali_reset_irq(denali);
934 denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
937 /* wait for erase to complete or failure to occur */
938 irq_status = denali_wait_for_irq(denali,
939 INTR__ERASE_COMP | INTR__ERASE_FAIL);
941 return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
944 static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
945 const struct nand_data_interface *conf)
947 struct denali_nand_info *denali = mtd_to_denali(mtd);
948 const struct nand_sdr_timings *timings;
950 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
951 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
952 int addr_2_data_mask;
955 timings = nand_get_sdr_timings(conf);
957 return PTR_ERR(timings);
959 /* clk_x period in picoseconds */
960 t_clk = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
964 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
967 /* tREA -> ACC_CLKS */
968 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_clk);
969 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
971 tmp = ioread32(denali->reg + ACC_CLKS);
972 tmp &= ~ACC_CLKS__VALUE;
973 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
974 iowrite32(tmp, denali->reg + ACC_CLKS);
976 /* tRWH -> RE_2_WE */
977 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_clk);
978 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
980 tmp = ioread32(denali->reg + RE_2_WE);
981 tmp &= ~RE_2_WE__VALUE;
982 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
983 iowrite32(tmp, denali->reg + RE_2_WE);
985 /* tRHZ -> RE_2_RE */
986 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_clk);
987 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
989 tmp = ioread32(denali->reg + RE_2_RE);
990 tmp &= ~RE_2_RE__VALUE;
991 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
992 iowrite32(tmp, denali->reg + RE_2_RE);
995 * tCCS, tWHR -> WE_2_RE
997 * With WE_2_RE properly set, the Denali controller automatically takes
998 * care of the delay; the driver need not set NAND_WAIT_TCCS.
1000 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min),
1002 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
1004 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
1005 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
1006 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
1007 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
1009 /* tADL -> ADDR_2_DATA */
1011 /* for older versions, ADDR_2_DATA is only 6 bit wide */
1012 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
1013 if (denali->revision < 0x0501)
1014 addr_2_data_mask >>= 1;
1016 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_clk);
1017 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
1019 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
1020 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
1021 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
1022 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
1024 /* tREH, tWH -> RDWR_EN_HI_CNT */
1025 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
1027 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
1029 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
1030 tmp &= ~RDWR_EN_HI_CNT__VALUE;
1031 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
1032 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
1034 /* tRP, tWP -> RDWR_EN_LO_CNT */
1035 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min),
1037 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
1039 rdwr_en_lo_hi = max(rdwr_en_lo_hi, DENALI_CLK_X_MULT);
1040 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
1041 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
1043 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
1044 tmp &= ~RDWR_EN_LO_CNT__VALUE;
1045 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
1046 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
1048 /* tCS, tCEA -> CS_SETUP_CNT */
1049 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_clk) - rdwr_en_lo,
1050 (int)DIV_ROUND_UP(timings->tCEA_max, t_clk) - acc_clks,
1052 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
1054 tmp = ioread32(denali->reg + CS_SETUP_CNT);
1055 tmp &= ~CS_SETUP_CNT__VALUE;
1056 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
1057 iowrite32(tmp, denali->reg + CS_SETUP_CNT);
1062 static void denali_reset_banks(struct denali_nand_info *denali)
1067 for (i = 0; i < denali->max_banks; i++) {
1068 denali->active_bank = i;
1070 denali_reset_irq(denali);
1072 iowrite32(DEVICE_RESET__BANK(i),
1073 denali->reg + DEVICE_RESET);
1075 irq_status = denali_wait_for_irq(denali,
1076 INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
1077 if (!(irq_status & INTR__INT_ACT))
1081 dev_dbg(denali->dev, "%d chips connected\n", i);
1082 denali->max_banks = i;
1085 static void denali_hw_init(struct denali_nand_info *denali)
1088 * The REVISION register may not be reliable. Platforms are allowed to
1091 if (!denali->revision)
1092 denali->revision = swab16(ioread32(denali->reg + REVISION));
1095 * tell driver how many bit controller will skip before writing
1096 * ECC code in OOB. This is normally used for bad block marker
1098 denali->oob_skip_bytes = CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES;
1099 iowrite32(denali->oob_skip_bytes, denali->reg + SPARE_AREA_SKIP_BYTES);
1100 denali_detect_max_banks(denali);
1101 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
1102 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
1104 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
1107 int denali_calc_ecc_bytes(int step_size, int strength)
1109 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
1110 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
1112 EXPORT_SYMBOL(denali_calc_ecc_bytes);
1114 static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
1115 struct denali_nand_info *denali)
1117 int oobavail = mtd->oobsize - denali->oob_skip_bytes;
1121 * If .size and .strength are already set (usually by DT),
1122 * check if they are supported by this controller.
1124 if (chip->ecc.size && chip->ecc.strength)
1125 return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
1128 * We want .size and .strength closest to the chip's requirement
1129 * unless NAND_ECC_MAXIMIZE is requested.
1131 if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
1132 ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
1137 /* Max ECC strength is the last thing we can do */
1138 return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
1141 static struct nand_ecclayout nand_oob;
1143 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1144 struct mtd_oob_region *oobregion)
1146 struct denali_nand_info *denali = mtd_to_denali(mtd);
1147 struct nand_chip *chip = mtd_to_nand(mtd);
1152 oobregion->offset = denali->oob_skip_bytes;
1153 oobregion->length = chip->ecc.total;
1158 static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1159 struct mtd_oob_region *oobregion)
1161 struct denali_nand_info *denali = mtd_to_denali(mtd);
1162 struct nand_chip *chip = mtd_to_nand(mtd);
1167 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
1168 oobregion->length = mtd->oobsize - oobregion->offset;
1173 static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1174 .ecc = denali_ooblayout_ecc,
1175 .free = denali_ooblayout_free,
1178 static int denali_multidev_fixup(struct denali_nand_info *denali)
1180 struct nand_chip *chip = &denali->nand;
1181 struct mtd_info *mtd = nand_to_mtd(chip);
1184 * Support for multi device:
1185 * When the IP configuration is x16 capable and two x8 chips are
1186 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1187 * In this case, the core framework knows nothing about this fact,
1188 * so we should tell it the _logical_ pagesize and anything necessary.
1190 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
1193 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1194 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1196 if (denali->devs_per_cs == 0) {
1197 denali->devs_per_cs = 1;
1198 iowrite32(1, denali->reg + DEVICES_CONNECTED);
1201 if (denali->devs_per_cs == 1)
1204 if (denali->devs_per_cs != 2) {
1205 dev_err(denali->dev, "unsupported number of devices %d\n",
1206 denali->devs_per_cs);
1210 /* 2 chips in parallel */
1212 mtd->erasesize <<= 1;
1213 mtd->writesize <<= 1;
1215 chip->chipsize <<= 1;
1216 chip->page_shift += 1;
1217 chip->phys_erase_shift += 1;
1218 chip->bbt_erase_shift += 1;
1219 chip->chip_shift += 1;
1220 chip->pagemask <<= 1;
1221 chip->ecc.size <<= 1;
1222 chip->ecc.bytes <<= 1;
1223 chip->ecc.strength <<= 1;
1224 denali->oob_skip_bytes <<= 1;
1229 int denali_init(struct denali_nand_info *denali)
1231 struct nand_chip *chip = &denali->nand;
1232 struct mtd_info *mtd = nand_to_mtd(chip);
1233 u32 features = ioread32(denali->reg + FEATURES);
1236 denali_hw_init(denali);
1238 denali_clear_irq_all(denali);
1240 denali_reset_banks(denali);
1242 denali->active_bank = DENALI_INVALID_BANK;
1244 chip->flash_node = dev_of_offset(denali->dev);
1245 /* Fallback to the default name if DT did not give "label" property */
1247 mtd->name = "denali-nand";
1249 chip->select_chip = denali_select_chip;
1250 chip->read_byte = denali_read_byte;
1251 chip->write_byte = denali_write_byte;
1252 chip->read_word = denali_read_word;
1253 chip->cmd_ctrl = denali_cmd_ctrl;
1254 chip->dev_ready = denali_dev_ready;
1255 chip->waitfunc = denali_waitfunc;
1257 if (features & FEATURES__INDEX_ADDR) {
1258 denali->host_read = denali_indexed_read;
1259 denali->host_write = denali_indexed_write;
1261 denali->host_read = denali_direct_read;
1262 denali->host_write = denali_direct_write;
1265 /* clk rate info is needed for setup_data_interface */
1266 if (denali->clk_x_rate)
1267 chip->setup_data_interface = denali_setup_data_interface;
1269 ret = nand_scan_ident(mtd, denali->max_banks, NULL);
1273 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
1274 denali->dma_avail = 1;
1276 if (denali->dma_avail) {
1277 chip->buf_align = ARCH_DMA_MINALIGN;
1278 if (denali->caps & DENALI_CAP_DMA_64BIT)
1279 denali->setup_dma = denali_setup_dma64;
1281 denali->setup_dma = denali_setup_dma32;
1283 chip->buf_align = 4;
1286 chip->options |= NAND_USE_BOUNCE_BUFFER;
1287 chip->bbt_options |= NAND_BBT_USE_FLASH;
1288 chip->bbt_options |= NAND_BBT_NO_OOB;
1289 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1291 /* no subpage writes on denali */
1292 chip->options |= NAND_NO_SUBPAGE_WRITE;
1294 ret = denali_ecc_setup(mtd, chip, denali);
1296 dev_err(denali->dev, "Failed to setup ECC settings.\n");
1300 dev_dbg(denali->dev,
1301 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1302 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
1304 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
1305 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
1306 denali->reg + ECC_CORRECTION);
1307 iowrite32(mtd->erasesize / mtd->writesize,
1308 denali->reg + PAGES_PER_BLOCK);
1309 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
1310 denali->reg + DEVICE_WIDTH);
1311 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
1312 denali->reg + TWO_ROW_ADDR_CYCLES);
1313 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
1314 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
1316 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
1317 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
1318 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1319 iowrite32(mtd->writesize / chip->ecc.size,
1320 denali->reg + CFG_NUM_DATA_BLOCKS);
1322 mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
1324 nand_oob.eccbytes = denali->nand.ecc.bytes;
1325 denali->nand.ecc.layout = &nand_oob;
1327 if (chip->options & NAND_BUSWIDTH_16) {
1328 chip->read_buf = denali_read_buf16;
1329 chip->write_buf = denali_write_buf16;
1331 chip->read_buf = denali_read_buf;
1332 chip->write_buf = denali_write_buf;
1334 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1335 chip->ecc.read_page = denali_read_page;
1336 chip->ecc.read_page_raw = denali_read_page_raw;
1337 chip->ecc.write_page = denali_write_page;
1338 chip->ecc.write_page_raw = denali_write_page_raw;
1339 chip->ecc.read_oob = denali_read_oob;
1340 chip->ecc.write_oob = denali_write_oob;
1341 chip->erase = denali_erase;
1343 ret = denali_multidev_fixup(denali);
1348 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
1349 * use devm_kmalloc() because the memory allocated by devm_ does not
1350 * guarantee DMA-safe alignment.
1352 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
1356 ret = nand_scan_tail(mtd);
1360 ret = nand_register(0, mtd);
1362 dev_err(denali->dev, "Failed to register MTD: %d\n", ret);