1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Panasonic Corporation
4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
8 #include <asm/dma-mapping.h>
11 #include <dm/devres.h>
12 #include <linux/bitfield.h>
13 #include <linux/dma-direction.h>
14 #include <linux/err.h>
15 #include <linux/errno.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/rawnand.h>
22 #define DENALI_NAND_NAME "denali-nand"
24 /* for Indexed Addressing */
25 #define DENALI_INDEXED_CTRL 0x00
26 #define DENALI_INDEXED_DATA 0x10
28 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
29 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
30 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
31 #define DENALI_MAP11 (3 << 26) /* direct controller access */
33 /* MAP11 access cycle type */
34 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
35 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
36 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
39 #define DENALI_ERASE 0x01
41 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
43 #define DENALI_INVALID_BANK -1
44 #define DENALI_NR_BANKS 4
46 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
48 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
52 * Direct Addressing - the slave address forms the control information (command
53 * type, bank, block, and page address). The slave data is the actual data to
54 * be transferred. This mode requires 28 bits of address region allocated.
56 static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
58 return ioread32(denali->host + addr);
61 static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
64 iowrite32(data, denali->host + addr);
68 * Indexed Addressing - address translation module intervenes in passing the
69 * control information. This mode reduces the required address range. The
70 * control information and transferred data are latched by the registers in
71 * the translation module.
73 static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
75 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
76 return ioread32(denali->host + DENALI_INDEXED_DATA);
79 static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
82 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
83 iowrite32(data, denali->host + DENALI_INDEXED_DATA);
87 * Use the configuration feature register to determine the maximum number of
88 * banks that the hardware supports.
90 static void denali_detect_max_banks(struct denali_nand_info *denali)
92 uint32_t features = ioread32(denali->reg + FEATURES);
94 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
96 /* the encoding changed from rev 5.0 to 5.1 */
97 if (denali->revision < 0x0501)
98 denali->max_banks <<= 1;
101 static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali)
105 for (i = 0; i < DENALI_NR_BANKS; i++)
106 iowrite32(U32_MAX, denali->reg + INTR_EN(i));
107 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
110 static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali)
114 for (i = 0; i < DENALI_NR_BANKS; i++)
115 iowrite32(0, denali->reg + INTR_EN(i));
116 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
119 static void denali_clear_irq(struct denali_nand_info *denali,
120 int bank, uint32_t irq_status)
122 /* write one to clear bits */
123 iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
126 static void denali_clear_irq_all(struct denali_nand_info *denali)
130 for (i = 0; i < DENALI_NR_BANKS; i++)
131 denali_clear_irq(denali, i, U32_MAX);
134 static void __denali_check_irq(struct denali_nand_info *denali)
139 for (i = 0; i < DENALI_NR_BANKS; i++) {
140 irq_status = ioread32(denali->reg + INTR_STATUS(i));
141 denali_clear_irq(denali, i, irq_status);
143 if (i != denali->active_bank)
146 denali->irq_status |= irq_status;
150 static void denali_reset_irq(struct denali_nand_info *denali)
152 denali->irq_status = 0;
153 denali->irq_mask = 0;
156 static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
159 unsigned long time_left = 1000000;
162 __denali_check_irq(denali);
164 if (irq_mask & denali->irq_status)
165 return denali->irq_status;
171 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
176 return denali->irq_status;
179 static uint32_t denali_check_irq(struct denali_nand_info *denali)
181 __denali_check_irq(denali);
183 return denali->irq_status;
186 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
188 struct denali_nand_info *denali = mtd_to_denali(mtd);
189 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
192 for (i = 0; i < len; i++)
193 buf[i] = denali->host_read(denali, addr);
196 static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
198 struct denali_nand_info *denali = mtd_to_denali(mtd);
199 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
202 for (i = 0; i < len; i++)
203 denali->host_write(denali, addr, buf[i]);
206 static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
208 struct denali_nand_info *denali = mtd_to_denali(mtd);
209 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
210 uint16_t *buf16 = (uint16_t *)buf;
213 for (i = 0; i < len / 2; i++)
214 buf16[i] = denali->host_read(denali, addr);
217 static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
220 struct denali_nand_info *denali = mtd_to_denali(mtd);
221 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
222 const uint16_t *buf16 = (const uint16_t *)buf;
225 for (i = 0; i < len / 2; i++)
226 denali->host_write(denali, addr, buf16[i]);
229 static uint8_t denali_read_byte(struct mtd_info *mtd)
233 denali_read_buf(mtd, &byte, 1);
238 static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
240 denali_write_buf(mtd, &byte, 1);
243 static uint16_t denali_read_word(struct mtd_info *mtd)
247 denali_read_buf16(mtd, (uint8_t *)&word, 2);
252 static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
254 struct denali_nand_info *denali = mtd_to_denali(mtd);
258 type = DENALI_MAP11_CMD;
259 else if (ctrl & NAND_ALE)
260 type = DENALI_MAP11_ADDR;
265 * Some commands are followed by chip->dev_ready or chip->waitfunc.
266 * irq_status must be cleared here to catch the R/B# interrupt later.
268 if (ctrl & NAND_CTRL_CHANGE)
269 denali_reset_irq(denali);
271 denali->host_write(denali, DENALI_BANK(denali) | type, dat);
274 static int denali_dev_ready(struct mtd_info *mtd)
276 struct denali_nand_info *denali = mtd_to_denali(mtd);
278 return !!(denali_check_irq(denali) & INTR__INT_ACT);
281 static int denali_check_erased_page(struct mtd_info *mtd,
282 struct nand_chip *chip, uint8_t *buf,
283 unsigned long uncor_ecc_flags,
284 unsigned int max_bitflips)
286 uint8_t *ecc_code = chip->buffers->ecccode;
287 int ecc_steps = chip->ecc.steps;
288 int ecc_size = chip->ecc.size;
289 int ecc_bytes = chip->ecc.bytes;
292 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
297 for (i = 0; i < ecc_steps; i++) {
298 if (!(uncor_ecc_flags & BIT(i)))
301 stat = nand_check_erased_ecc_chunk(buf, ecc_size,
306 mtd->ecc_stats.failed++;
308 mtd->ecc_stats.corrected += stat;
309 max_bitflips = max_t(unsigned int, max_bitflips, stat);
313 ecc_code += ecc_bytes;
319 static int denali_hw_ecc_fixup(struct mtd_info *mtd,
320 struct denali_nand_info *denali,
321 unsigned long *uncor_ecc_flags)
323 struct nand_chip *chip = mtd_to_nand(mtd);
324 int bank = denali->active_bank;
326 unsigned int max_bitflips;
328 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
329 ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
331 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
333 * This flag is set when uncorrectable error occurs at least in
334 * one ECC sector. We can not know "how many sectors", or
335 * "which sector(s)". We need erase-page check for all sectors.
337 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
341 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
344 * The register holds the maximum of per-sector corrected bitflips.
345 * This is suitable for the return value of the ->read_page() callback.
346 * Unfortunately, we can not know the total number of corrected bits in
347 * the page. Increase the stats by max_bitflips. (compromised solution)
349 mtd->ecc_stats.corrected += max_bitflips;
354 static int denali_sw_ecc_fixup(struct mtd_info *mtd,
355 struct denali_nand_info *denali,
356 unsigned long *uncor_ecc_flags, uint8_t *buf)
358 unsigned int ecc_size = denali->nand.ecc.size;
359 unsigned int bitflips = 0;
360 unsigned int max_bitflips = 0;
361 uint32_t err_addr, err_cor_info;
362 unsigned int err_byte, err_sector, err_device;
363 uint8_t err_cor_value;
364 unsigned int prev_sector = 0;
367 denali_reset_irq(denali);
370 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
371 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
372 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
374 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
375 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
377 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
380 /* reset the bitflip counter when crossing ECC sector */
381 if (err_sector != prev_sector)
384 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
386 * Check later if this is a real ECC error, or
389 *uncor_ecc_flags |= BIT(err_sector);
390 } else if (err_byte < ecc_size) {
392 * If err_byte is larger than ecc_size, means error
393 * happened in OOB, so we ignore it. It's no need for
394 * us to correct it err_device is represented the NAND
395 * error bits are happened in if there are more than
396 * one NAND connected.
399 unsigned int flips_in_byte;
401 offset = (err_sector * ecc_size + err_byte) *
402 denali->devs_per_cs + err_device;
404 /* correct the ECC error */
405 flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
406 buf[offset] ^= err_cor_value;
407 mtd->ecc_stats.corrected += flips_in_byte;
408 bitflips += flips_in_byte;
410 max_bitflips = max(max_bitflips, bitflips);
413 prev_sector = err_sector;
414 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
417 * Once handle all ECC errors, controller will trigger an
418 * ECC_TRANSACTION_DONE interrupt.
420 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
421 if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
427 static void denali_setup_dma64(struct denali_nand_info *denali,
428 dma_addr_t dma_addr, int page, int write)
431 const int page_count = 1;
433 mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
435 /* DMA is a three step process */
438 * 1. setup transfer type, interrupt when complete,
439 * burst len = 64 bytes, the number of pages
441 denali->host_write(denali, mode,
442 0x01002000 | (64 << 16) | (write << 8) | page_count);
444 /* 2. set memory low address */
445 denali->host_write(denali, mode, lower_32_bits(dma_addr));
447 /* 3. set memory high address */
448 denali->host_write(denali, mode, upper_32_bits(dma_addr));
451 static void denali_setup_dma32(struct denali_nand_info *denali,
452 dma_addr_t dma_addr, int page, int write)
455 const int page_count = 1;
457 mode = DENALI_MAP10 | DENALI_BANK(denali);
459 /* DMA is a four step process */
461 /* 1. setup transfer type and # of pages */
462 denali->host_write(denali, mode | page,
463 0x2000 | (write << 8) | page_count);
465 /* 2. set memory high address bits 23:8 */
466 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
468 /* 3. set memory low address bits 23:8 */
469 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
471 /* 4. interrupt when complete, burst len = 64 bytes */
472 denali->host_write(denali, mode | 0x14000, 0x2400);
475 static int denali_pio_read(struct denali_nand_info *denali, void *buf,
476 size_t size, int page, int raw)
478 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
479 uint32_t *buf32 = (uint32_t *)buf;
480 uint32_t irq_status, ecc_err_mask;
483 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
484 ecc_err_mask = INTR__ECC_UNCOR_ERR;
486 ecc_err_mask = INTR__ECC_ERR;
488 denali_reset_irq(denali);
490 for (i = 0; i < size / 4; i++)
491 *buf32++ = denali->host_read(denali, addr);
493 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
494 if (!(irq_status & INTR__PAGE_XFER_INC))
497 if (irq_status & INTR__ERASED_PAGE)
498 memset(buf, 0xff, size);
500 return irq_status & ecc_err_mask ? -EBADMSG : 0;
503 static int denali_pio_write(struct denali_nand_info *denali,
504 const void *buf, size_t size, int page, int raw)
506 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
507 const uint32_t *buf32 = (uint32_t *)buf;
511 denali_reset_irq(denali);
513 for (i = 0; i < size / 4; i++)
514 denali->host_write(denali, addr, *buf32++);
516 irq_status = denali_wait_for_irq(denali,
517 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
518 if (!(irq_status & INTR__PROGRAM_COMP))
524 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
525 size_t size, int page, int raw, int write)
528 return denali_pio_write(denali, buf, size, page, raw);
530 return denali_pio_read(denali, buf, size, page, raw);
533 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
534 size_t size, int page, int raw, int write)
537 uint32_t irq_mask, irq_status, ecc_err_mask;
538 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
541 dma_addr = dma_map_single(buf, size, dir);
542 if (dma_mapping_error(denali->dev, dma_addr)) {
543 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
544 return denali_pio_xfer(denali, buf, size, page, raw, write);
549 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
550 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
551 * when the page program is completed.
553 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
555 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
556 irq_mask = INTR__DMA_CMD_COMP;
557 ecc_err_mask = INTR__ECC_UNCOR_ERR;
559 irq_mask = INTR__DMA_CMD_COMP;
560 ecc_err_mask = INTR__ECC_ERR;
563 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
565 * The ->setup_dma() hook kicks DMA by using the data/command
566 * interface, which belongs to a different AXI port from the
567 * register interface. Read back the register to avoid a race.
569 ioread32(denali->reg + DMA_ENABLE);
571 denali_reset_irq(denali);
572 denali->setup_dma(denali, dma_addr, page, write);
574 irq_status = denali_wait_for_irq(denali, irq_mask);
575 if (!(irq_status & INTR__DMA_CMD_COMP))
577 else if (irq_status & ecc_err_mask)
580 iowrite32(0, denali->reg + DMA_ENABLE);
582 dma_unmap_single(buf, size, dir);
584 if (irq_status & INTR__ERASED_PAGE)
585 memset(buf, 0xff, size);
590 static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
591 size_t size, int page, int raw, int write)
593 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
594 iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
595 denali->reg + TRANSFER_SPARE_REG);
597 if (denali->dma_avail)
598 return denali_dma_xfer(denali, buf, size, page, raw, write);
600 return denali_pio_xfer(denali, buf, size, page, raw, write);
603 static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
606 struct denali_nand_info *denali = mtd_to_denali(mtd);
607 unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
608 unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
609 int writesize = mtd->writesize;
610 int oobsize = mtd->oobsize;
611 uint8_t *bufpoi = chip->oob_poi;
612 int ecc_steps = chip->ecc.steps;
613 int ecc_size = chip->ecc.size;
614 int ecc_bytes = chip->ecc.bytes;
615 int oob_skip = denali->oob_skip_bytes;
616 size_t size = writesize + oobsize;
619 /* BBM at the beginning of the OOB area */
620 chip->cmdfunc(mtd, start_cmd, writesize, page);
622 chip->write_buf(mtd, bufpoi, oob_skip);
624 chip->read_buf(mtd, bufpoi, oob_skip);
628 for (i = 0; i < ecc_steps; i++) {
629 pos = ecc_size + i * (ecc_size + ecc_bytes);
632 if (pos >= writesize)
634 else if (pos + len > writesize)
635 len = writesize - pos;
637 chip->cmdfunc(mtd, rnd_cmd, pos, -1);
639 chip->write_buf(mtd, bufpoi, len);
641 chip->read_buf(mtd, bufpoi, len);
643 if (len < ecc_bytes) {
644 len = ecc_bytes - len;
645 chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
647 chip->write_buf(mtd, bufpoi, len);
649 chip->read_buf(mtd, bufpoi, len);
655 len = oobsize - (bufpoi - chip->oob_poi);
656 chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
658 chip->write_buf(mtd, bufpoi, len);
660 chip->read_buf(mtd, bufpoi, len);
663 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
664 uint8_t *buf, int oob_required, int page)
666 struct denali_nand_info *denali = mtd_to_denali(mtd);
667 int writesize = mtd->writesize;
668 int oobsize = mtd->oobsize;
669 int ecc_steps = chip->ecc.steps;
670 int ecc_size = chip->ecc.size;
671 int ecc_bytes = chip->ecc.bytes;
672 void *tmp_buf = denali->buf;
673 int oob_skip = denali->oob_skip_bytes;
674 size_t size = writesize + oobsize;
675 int ret, i, pos, len;
677 ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0);
681 /* Arrange the buffer for syndrome payload/ecc layout */
683 for (i = 0; i < ecc_steps; i++) {
684 pos = i * (ecc_size + ecc_bytes);
687 if (pos >= writesize)
689 else if (pos + len > writesize)
690 len = writesize - pos;
692 memcpy(buf, tmp_buf + pos, len);
694 if (len < ecc_size) {
695 len = ecc_size - len;
696 memcpy(buf, tmp_buf + writesize + oob_skip,
704 uint8_t *oob = chip->oob_poi;
706 /* BBM at the beginning of the OOB area */
707 memcpy(oob, tmp_buf + writesize, oob_skip);
711 for (i = 0; i < ecc_steps; i++) {
712 pos = ecc_size + i * (ecc_size + ecc_bytes);
715 if (pos >= writesize)
717 else if (pos + len > writesize)
718 len = writesize - pos;
720 memcpy(oob, tmp_buf + pos, len);
722 if (len < ecc_bytes) {
723 len = ecc_bytes - len;
724 memcpy(oob, tmp_buf + writesize + oob_skip,
731 len = oobsize - (oob - chip->oob_poi);
732 memcpy(oob, tmp_buf + size - len, len);
738 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
741 denali_oob_xfer(mtd, chip, page, 0);
746 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
749 struct denali_nand_info *denali = mtd_to_denali(mtd);
752 denali_reset_irq(denali);
754 denali_oob_xfer(mtd, chip, page, 1);
756 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
757 status = chip->waitfunc(mtd, chip);
759 return status & NAND_STATUS_FAIL ? -EIO : 0;
762 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
763 uint8_t *buf, int oob_required, int page)
765 struct denali_nand_info *denali = mtd_to_denali(mtd);
766 unsigned long uncor_ecc_flags = 0;
770 ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
771 if (ret && ret != -EBADMSG)
774 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
775 stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
776 else if (ret == -EBADMSG)
777 stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
782 if (uncor_ecc_flags) {
783 ret = denali_read_oob(mtd, chip, page);
787 stat = denali_check_erased_page(mtd, chip, buf,
788 uncor_ecc_flags, stat);
794 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
795 const uint8_t *buf, int oob_required, int page)
797 struct denali_nand_info *denali = mtd_to_denali(mtd);
798 int writesize = mtd->writesize;
799 int oobsize = mtd->oobsize;
800 int ecc_steps = chip->ecc.steps;
801 int ecc_size = chip->ecc.size;
802 int ecc_bytes = chip->ecc.bytes;
803 void *tmp_buf = denali->buf;
804 int oob_skip = denali->oob_skip_bytes;
805 size_t size = writesize + oobsize;
809 * Fill the buffer with 0xff first except the full page transfer.
810 * This simplifies the logic.
812 if (!buf || !oob_required)
813 memset(tmp_buf, 0xff, size);
815 /* Arrange the buffer for syndrome payload/ecc layout */
817 for (i = 0; i < ecc_steps; i++) {
818 pos = i * (ecc_size + ecc_bytes);
821 if (pos >= writesize)
823 else if (pos + len > writesize)
824 len = writesize - pos;
826 memcpy(tmp_buf + pos, buf, len);
828 if (len < ecc_size) {
829 len = ecc_size - len;
830 memcpy(tmp_buf + writesize + oob_skip, buf,
838 const uint8_t *oob = chip->oob_poi;
840 /* BBM at the beginning of the OOB area */
841 memcpy(tmp_buf + writesize, oob, oob_skip);
845 for (i = 0; i < ecc_steps; i++) {
846 pos = ecc_size + i * (ecc_size + ecc_bytes);
849 if (pos >= writesize)
851 else if (pos + len > writesize)
852 len = writesize - pos;
854 memcpy(tmp_buf + pos, oob, len);
856 if (len < ecc_bytes) {
857 len = ecc_bytes - len;
858 memcpy(tmp_buf + writesize + oob_skip, oob,
865 len = oobsize - (oob - chip->oob_poi);
866 memcpy(tmp_buf + size - len, oob, len);
869 return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
872 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
873 const uint8_t *buf, int oob_required, int page)
875 struct denali_nand_info *denali = mtd_to_denali(mtd);
877 return denali_data_xfer(denali, (void *)buf, mtd->writesize,
881 static void denali_select_chip(struct mtd_info *mtd, int chip)
883 struct denali_nand_info *denali = mtd_to_denali(mtd);
885 denali->active_bank = chip;
888 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
890 struct denali_nand_info *denali = mtd_to_denali(mtd);
893 /* R/B# pin transitioned from low to high? */
894 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
896 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
899 static int denali_erase(struct mtd_info *mtd, int page)
901 struct denali_nand_info *denali = mtd_to_denali(mtd);
904 denali_reset_irq(denali);
906 denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
909 /* wait for erase to complete or failure to occur */
910 irq_status = denali_wait_for_irq(denali,
911 INTR__ERASE_COMP | INTR__ERASE_FAIL);
913 return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
916 static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
917 const struct nand_data_interface *conf)
919 struct denali_nand_info *denali = mtd_to_denali(mtd);
920 const struct nand_sdr_timings *timings;
921 unsigned long t_x, mult_x;
922 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
923 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
924 int addr_2_data_mask;
927 timings = nand_get_sdr_timings(conf);
929 return PTR_ERR(timings);
931 /* clk_x period in picoseconds */
932 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
937 * The bus interface clock, clk_x, is phase aligned with the core clock.
938 * The clk_x is an integral multiple N of the core clk. The value N is
939 * configured at IP delivery time, and its available value is 4, 5, 6.
941 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
942 if (mult_x < 4 || mult_x > 6)
945 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
948 /* tREA -> ACC_CLKS */
949 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
950 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
952 tmp = ioread32(denali->reg + ACC_CLKS);
953 tmp &= ~ACC_CLKS__VALUE;
954 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
955 iowrite32(tmp, denali->reg + ACC_CLKS);
957 /* tRWH -> RE_2_WE */
958 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
959 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
961 tmp = ioread32(denali->reg + RE_2_WE);
962 tmp &= ~RE_2_WE__VALUE;
963 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
964 iowrite32(tmp, denali->reg + RE_2_WE);
966 /* tRHZ -> RE_2_RE */
967 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
968 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
970 tmp = ioread32(denali->reg + RE_2_RE);
971 tmp &= ~RE_2_RE__VALUE;
972 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
973 iowrite32(tmp, denali->reg + RE_2_RE);
976 * tCCS, tWHR -> WE_2_RE
978 * With WE_2_RE properly set, the Denali controller automatically takes
979 * care of the delay; the driver need not set NAND_WAIT_TCCS.
981 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
982 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
984 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
985 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
986 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
987 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
989 /* tADL -> ADDR_2_DATA */
991 /* for older versions, ADDR_2_DATA is only 6 bit wide */
992 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
993 if (denali->revision < 0x0501)
994 addr_2_data_mask >>= 1;
996 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
997 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
999 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
1000 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
1001 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
1002 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
1004 /* tREH, tWH -> RDWR_EN_HI_CNT */
1005 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
1007 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
1009 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
1010 tmp &= ~RDWR_EN_HI_CNT__VALUE;
1011 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
1012 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
1014 /* tRP, tWP -> RDWR_EN_LO_CNT */
1015 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
1016 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
1018 rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x);
1019 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
1020 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
1022 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
1023 tmp &= ~RDWR_EN_LO_CNT__VALUE;
1024 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
1025 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
1027 /* tCS, tCEA -> CS_SETUP_CNT */
1028 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
1029 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
1031 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
1033 tmp = ioread32(denali->reg + CS_SETUP_CNT);
1034 tmp &= ~CS_SETUP_CNT__VALUE;
1035 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
1036 iowrite32(tmp, denali->reg + CS_SETUP_CNT);
1041 static void denali_reset_banks(struct denali_nand_info *denali)
1046 for (i = 0; i < denali->max_banks; i++) {
1047 denali->active_bank = i;
1049 denali_reset_irq(denali);
1051 iowrite32(DEVICE_RESET__BANK(i),
1052 denali->reg + DEVICE_RESET);
1054 irq_status = denali_wait_for_irq(denali,
1055 INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
1056 if (!(irq_status & INTR__INT_ACT))
1060 dev_dbg(denali->dev, "%d chips connected\n", i);
1061 denali->max_banks = i;
1064 static void denali_hw_init(struct denali_nand_info *denali)
1067 * The REVISION register may not be reliable. Platforms are allowed to
1070 if (!denali->revision)
1071 denali->revision = swab16(ioread32(denali->reg + REVISION));
1074 * Set how many bytes should be skipped before writing data in OOB.
1075 * If a platform requests a non-zero value, set it to the register.
1076 * Otherwise, read the value out, expecting it has already been set up
1079 if (denali->oob_skip_bytes)
1080 iowrite32(denali->oob_skip_bytes,
1081 denali->reg + SPARE_AREA_SKIP_BYTES);
1083 denali->oob_skip_bytes = ioread32(denali->reg +
1084 SPARE_AREA_SKIP_BYTES);
1086 denali_detect_max_banks(denali);
1087 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
1088 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
1090 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
1093 int denali_calc_ecc_bytes(int step_size, int strength)
1095 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
1096 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
1098 EXPORT_SYMBOL(denali_calc_ecc_bytes);
1100 static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
1101 struct denali_nand_info *denali)
1103 int oobavail = mtd->oobsize - denali->oob_skip_bytes;
1107 * If .size and .strength are already set (usually by DT),
1108 * check if they are supported by this controller.
1110 if (chip->ecc.size && chip->ecc.strength)
1111 return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
1114 * We want .size and .strength closest to the chip's requirement
1115 * unless NAND_ECC_MAXIMIZE is requested.
1117 if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
1118 ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
1123 /* Max ECC strength is the last thing we can do */
1124 return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
1127 static struct nand_ecclayout nand_oob;
1129 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1130 struct mtd_oob_region *oobregion)
1132 struct denali_nand_info *denali = mtd_to_denali(mtd);
1133 struct nand_chip *chip = mtd_to_nand(mtd);
1138 oobregion->offset = denali->oob_skip_bytes;
1139 oobregion->length = chip->ecc.total;
1144 static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1145 struct mtd_oob_region *oobregion)
1147 struct denali_nand_info *denali = mtd_to_denali(mtd);
1148 struct nand_chip *chip = mtd_to_nand(mtd);
1153 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
1154 oobregion->length = mtd->oobsize - oobregion->offset;
1159 static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1160 .ecc = denali_ooblayout_ecc,
1161 .rfree = denali_ooblayout_free,
1164 static int denali_multidev_fixup(struct denali_nand_info *denali)
1166 struct nand_chip *chip = &denali->nand;
1167 struct mtd_info *mtd = nand_to_mtd(chip);
1170 * Support for multi device:
1171 * When the IP configuration is x16 capable and two x8 chips are
1172 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1173 * In this case, the core framework knows nothing about this fact,
1174 * so we should tell it the _logical_ pagesize and anything necessary.
1176 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
1179 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1180 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1182 if (denali->devs_per_cs == 0) {
1183 denali->devs_per_cs = 1;
1184 iowrite32(1, denali->reg + DEVICES_CONNECTED);
1187 if (denali->devs_per_cs == 1)
1190 if (denali->devs_per_cs != 2) {
1191 dev_err(denali->dev, "unsupported number of devices %d\n",
1192 denali->devs_per_cs);
1196 /* 2 chips in parallel */
1198 mtd->erasesize <<= 1;
1199 mtd->writesize <<= 1;
1201 chip->chipsize <<= 1;
1202 chip->page_shift += 1;
1203 chip->phys_erase_shift += 1;
1204 chip->bbt_erase_shift += 1;
1205 chip->chip_shift += 1;
1206 chip->pagemask <<= 1;
1207 chip->ecc.size <<= 1;
1208 chip->ecc.bytes <<= 1;
1209 chip->ecc.strength <<= 1;
1210 denali->oob_skip_bytes <<= 1;
1215 int denali_init(struct denali_nand_info *denali)
1217 struct nand_chip *chip = &denali->nand;
1218 struct mtd_info *mtd = nand_to_mtd(chip);
1219 u32 features = ioread32(denali->reg + FEATURES);
1222 denali_hw_init(denali);
1224 denali_clear_irq_all(denali);
1226 denali_reset_banks(denali);
1228 denali->active_bank = DENALI_INVALID_BANK;
1230 chip->flash_node = dev_of_offset(denali->dev);
1231 /* Fallback to the default name if DT did not give "label" property */
1233 mtd->name = "denali-nand";
1235 chip->select_chip = denali_select_chip;
1236 chip->read_byte = denali_read_byte;
1237 chip->write_byte = denali_write_byte;
1238 chip->read_word = denali_read_word;
1239 chip->cmd_ctrl = denali_cmd_ctrl;
1240 chip->dev_ready = denali_dev_ready;
1241 chip->waitfunc = denali_waitfunc;
1243 if (features & FEATURES__INDEX_ADDR) {
1244 denali->host_read = denali_indexed_read;
1245 denali->host_write = denali_indexed_write;
1247 denali->host_read = denali_direct_read;
1248 denali->host_write = denali_direct_write;
1251 /* clk rate info is needed for setup_data_interface */
1252 if (denali->clk_x_rate)
1253 chip->setup_data_interface = denali_setup_data_interface;
1255 ret = nand_scan_ident(mtd, denali->max_banks, NULL);
1259 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
1260 denali->dma_avail = 1;
1262 if (denali->dma_avail) {
1263 chip->buf_align = ARCH_DMA_MINALIGN;
1264 if (denali->caps & DENALI_CAP_DMA_64BIT)
1265 denali->setup_dma = denali_setup_dma64;
1267 denali->setup_dma = denali_setup_dma32;
1269 chip->buf_align = 4;
1272 chip->options |= NAND_USE_BOUNCE_BUFFER;
1273 chip->bbt_options |= NAND_BBT_USE_FLASH;
1274 chip->bbt_options |= NAND_BBT_NO_OOB;
1275 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1277 /* no subpage writes on denali */
1278 chip->options |= NAND_NO_SUBPAGE_WRITE;
1280 ret = denali_ecc_setup(mtd, chip, denali);
1282 dev_err(denali->dev, "Failed to setup ECC settings.\n");
1286 dev_dbg(denali->dev,
1287 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1288 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
1290 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
1291 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
1292 denali->reg + ECC_CORRECTION);
1293 iowrite32(mtd->erasesize / mtd->writesize,
1294 denali->reg + PAGES_PER_BLOCK);
1295 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
1296 denali->reg + DEVICE_WIDTH);
1297 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
1298 denali->reg + TWO_ROW_ADDR_CYCLES);
1299 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
1300 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
1302 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
1303 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
1304 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1305 iowrite32(mtd->writesize / chip->ecc.size,
1306 denali->reg + CFG_NUM_DATA_BLOCKS);
1308 mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
1310 nand_oob.eccbytes = denali->nand.ecc.bytes;
1311 denali->nand.ecc.layout = &nand_oob;
1313 if (chip->options & NAND_BUSWIDTH_16) {
1314 chip->read_buf = denali_read_buf16;
1315 chip->write_buf = denali_write_buf16;
1317 chip->read_buf = denali_read_buf;
1318 chip->write_buf = denali_write_buf;
1320 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1321 chip->ecc.read_page = denali_read_page;
1322 chip->ecc.read_page_raw = denali_read_page_raw;
1323 chip->ecc.write_page = denali_write_page;
1324 chip->ecc.write_page_raw = denali_write_page_raw;
1325 chip->ecc.read_oob = denali_read_oob;
1326 chip->ecc.write_oob = denali_write_oob;
1327 chip->erase = denali_erase;
1329 ret = denali_multidev_fixup(denali);
1334 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
1335 * use devm_kmalloc() because the memory allocated by devm_ does not
1336 * guarantee DMA-safe alignment.
1338 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
1342 ret = nand_scan_tail(mtd);
1346 ret = nand_register(0, mtd);
1348 dev_err(denali->dev, "Failed to register MTD: %d\n", ret);