1 // SPDX-License-Identifier: GPL-2.0+
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2015 Xilinx, Inc.
11 #include <linux/errno.h>
12 #include <linux/mtd/mtd.h>
13 #include <linux/mtd/rawnand.h>
14 #include <linux/mtd/partitions.h>
15 #include <linux/mtd/nand_ecc.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/sys_proto.h>
20 struct arasan_nand_info {
21 void __iomem *nand_base;
23 bool on_die_ecc_enabled;
57 #define arasan_nand_base ((struct nand_regs __iomem *)ARASAN_NAND_BASEADDR)
59 struct arasan_nand_command_format {
66 #define ONDIE_ECC_FEATURE_ADDR 0x90
67 #define ENABLE_ONDIE_ECC 0x08
69 #define ARASAN_PROG_RD_MASK 0x00000001
70 #define ARASAN_PROG_BLK_ERS_MASK 0x00000004
71 #define ARASAN_PROG_RD_ID_MASK 0x00000040
72 #define ARASAN_PROG_RD_STS_MASK 0x00000008
73 #define ARASAN_PROG_PG_PROG_MASK 0x00000010
74 #define ARASAN_PROG_RD_PARAM_PG_MASK 0x00000080
75 #define ARASAN_PROG_RST_MASK 0x00000100
76 #define ARASAN_PROG_GET_FTRS_MASK 0x00000200
77 #define ARASAN_PROG_SET_FTRS_MASK 0x00000400
78 #define ARASAN_PROG_CHNG_ROWADR_END_MASK 0x00400000
80 #define ARASAN_NAND_CMD_ECC_ON_MASK 0x80000000
81 #define ARASAN_NAND_CMD_CMD12_MASK 0xFFFF
82 #define ARASAN_NAND_CMD_PG_SIZE_MASK 0x3800000
83 #define ARASAN_NAND_CMD_PG_SIZE_SHIFT 23
84 #define ARASAN_NAND_CMD_CMD2_SHIFT 8
85 #define ARASAN_NAND_CMD_ADDR_CYCL_MASK 0x70000000
86 #define ARASAN_NAND_CMD_ADDR_CYCL_SHIFT 28
88 #define ARASAN_NAND_MEM_ADDR1_PAGE_MASK 0xFFFF0000
89 #define ARASAN_NAND_MEM_ADDR1_COL_MASK 0xFFFF
90 #define ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT 16
91 #define ARASAN_NAND_MEM_ADDR2_PAGE_MASK 0xFF
92 #define ARASAN_NAND_MEM_ADDR2_CS_MASK 0xC0000000
93 #define ARASAN_NAND_MEM_ADDR2_BCH_MASK 0xE000000
94 #define ARASAN_NAND_MEM_ADDR2_BCH_SHIFT 25
96 #define ARASAN_NAND_INT_STS_ERR_EN_MASK 0x10
97 #define ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK 0x08
98 #define ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK 0x02
99 #define ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK 0x01
100 #define ARASAN_NAND_INT_STS_XFR_CMPLT_MASK 0x04
102 #define ARASAN_NAND_PKT_REG_PKT_CNT_MASK 0xFFF000
103 #define ARASAN_NAND_PKT_REG_PKT_SIZE_MASK 0x7FF
104 #define ARASAN_NAND_PKT_REG_PKT_CNT_SHFT 12
106 #define ARASAN_NAND_ROW_ADDR_CYCL_MASK 0x0F
107 #define ARASAN_NAND_COL_ADDR_CYCL_MASK 0xF0
108 #define ARASAN_NAND_COL_ADDR_CYCL_SHIFT 4
110 #define ARASAN_NAND_ECC_SIZE_SHIFT 16
111 #define ARASAN_NAND_ECC_BCH_SHIFT 27
113 #define ARASAN_NAND_PKTSIZE_1K 1024
114 #define ARASAN_NAND_PKTSIZE_512 512
116 #define ARASAN_NAND_POLL_TIMEOUT 1000000
117 #define ARASAN_NAND_INVALID_ADDR_CYCL 0xFF
119 #define ERR_ADDR_CYCLE -1
120 #define READ_BUFF_SIZE 0x4000
122 static struct arasan_nand_command_format *curr_cmd;
132 static struct arasan_nand_command_format arasan_nand_commands[] = {
133 {NAND_CMD_READ0, NAND_CMD_READSTART, NAND_ADDR_CYCL_BOTH,
134 ARASAN_PROG_RD_MASK},
135 {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, NAND_ADDR_CYCL_COL,
136 ARASAN_PROG_RD_MASK},
137 {NAND_CMD_READID, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
138 ARASAN_PROG_RD_ID_MASK},
139 {NAND_CMD_STATUS, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
140 ARASAN_PROG_RD_STS_MASK},
141 {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, NAND_ADDR_CYCL_BOTH,
142 ARASAN_PROG_PG_PROG_MASK},
143 {NAND_CMD_RNDIN, NAND_CMD_NONE, NAND_ADDR_CYCL_COL,
144 ARASAN_PROG_CHNG_ROWADR_END_MASK},
145 {NAND_CMD_ERASE1, NAND_CMD_ERASE2, NAND_ADDR_CYCL_ROW,
146 ARASAN_PROG_BLK_ERS_MASK},
147 {NAND_CMD_RESET, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE,
148 ARASAN_PROG_RST_MASK},
149 {NAND_CMD_PARAM, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
150 ARASAN_PROG_RD_PARAM_PG_MASK},
151 {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
152 ARASAN_PROG_GET_FTRS_MASK},
153 {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, NAND_ADDR_CYCL_ONE,
154 ARASAN_PROG_SET_FTRS_MASK},
155 {NAND_CMD_NONE, NAND_CMD_NONE, NAND_ADDR_CYCL_NONE, 0},
158 struct arasan_ecc_matrix {
160 u32 ecc_codeword_size;
168 static const struct arasan_ecc_matrix ecc_matrix[] = {
169 {512, 512, 1, 0, 0, 0x20D, 0x3},
170 {512, 512, 4, 1, 3, 0x209, 0x7},
171 {512, 512, 8, 1, 2, 0x203, 0xD},
175 {2048, 512, 1, 0, 0, 0x834, 0xC},
176 {2048, 512, 4, 1, 3, 0x826, 0x1A},
177 {2048, 512, 8, 1, 2, 0x80c, 0x34},
178 {2048, 512, 12, 1, 1, 0x822, 0x4E},
179 {2048, 512, 16, 1, 0, 0x808, 0x68},
180 {2048, 1024, 24, 1, 4, 0x81c, 0x54},
184 {4096, 512, 1, 0, 0, 0x1068, 0x18},
185 {4096, 512, 4, 1, 3, 0x104c, 0x34},
186 {4096, 512, 8, 1, 2, 0x1018, 0x68},
187 {4096, 512, 12, 1, 1, 0x1044, 0x9C},
188 {4096, 512, 16, 1, 0, 0x1010, 0xD0},
189 {4096, 1024, 24, 1, 4, 0x1038, 0xA8},
193 {8192, 512, 1, 0, 0, 0x20d0, 0x30},
194 {8192, 512, 4, 1, 3, 0x2098, 0x68},
195 {8192, 512, 8, 1, 2, 0x2030, 0xD0},
196 {8192, 512, 12, 1, 1, 0x2088, 0x138},
197 {8192, 512, 16, 1, 0, 0x2020, 0x1A0},
198 {8192, 1024, 24, 1, 4, 0x2070, 0x150},
202 {16384, 512, 1, 0, 0, 0x4460, 0x60},
203 {16384, 512, 4, 1, 3, 0x43f0, 0xD0},
204 {16384, 512, 8, 1, 2, 0x4320, 0x1A0},
205 {16384, 512, 12, 1, 1, 0x4250, 0x270},
206 {16384, 512, 16, 1, 0, 0x4180, 0x340},
207 {16384, 1024, 24, 1, 4, 0x4220, 0x2A0}
210 static struct nand_ecclayout ondie_nand_oob_64 = {
214 8, 9, 10, 11, 12, 13, 14, 15,
215 24, 25, 26, 27, 28, 29, 30, 31,
216 40, 41, 42, 43, 44, 45, 46, 47,
217 56, 57, 58, 59, 60, 61, 62, 63
221 { .offset = 4, .length = 4 },
222 { .offset = 20, .length = 4 },
223 { .offset = 36, .length = 4 },
224 { .offset = 52, .length = 4 }
229 * bbt decriptors for chips with on-die ECC and
230 * chips with 64-byte OOB
232 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
233 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
235 static struct nand_bbt_descr bbt_main_descr = {
236 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
237 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
242 .pattern = bbt_pattern
245 static struct nand_bbt_descr bbt_mirror_descr = {
246 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
247 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
252 .pattern = mirror_pattern
255 static u8 buf_data[READ_BUFF_SIZE];
256 static u32 buf_index;
258 static struct nand_ecclayout nand_oob;
260 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
262 static void arasan_nand_select_chip(struct mtd_info *mtd, int chip)
266 static void arasan_nand_enable_ecc(void)
270 reg_val = readl(&arasan_nand_base->cmd_reg);
271 reg_val |= ARASAN_NAND_CMD_ECC_ON_MASK;
273 writel(reg_val, &arasan_nand_base->cmd_reg);
276 static u8 arasan_nand_get_addrcycle(struct mtd_info *mtd)
279 struct nand_chip *chip = mtd_to_nand(mtd);
281 switch (curr_cmd->addr_cycles) {
282 case NAND_ADDR_CYCL_NONE:
285 case NAND_ADDR_CYCL_ONE:
288 case NAND_ADDR_CYCL_ROW:
289 addrcycles = chip->onfi_params.addr_cycles &
290 ARASAN_NAND_ROW_ADDR_CYCL_MASK;
292 case NAND_ADDR_CYCL_COL:
293 addrcycles = (chip->onfi_params.addr_cycles &
294 ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
295 ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
297 case NAND_ADDR_CYCL_BOTH:
298 addrcycles = chip->onfi_params.addr_cycles &
299 ARASAN_NAND_ROW_ADDR_CYCL_MASK;
300 addrcycles += (chip->onfi_params.addr_cycles &
301 ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
302 ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
305 addrcycles = ARASAN_NAND_INVALID_ADDR_CYCL;
311 static int arasan_nand_read_page(struct mtd_info *mtd, u8 *buf, u32 size)
313 struct nand_chip *chip = mtd_to_nand(mtd);
314 struct arasan_nand_info *nand = nand_get_controller_data(chip);
315 u32 reg_val, i, pktsize, pktnum;
316 u32 *bufptr = (u32 *)buf;
321 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
322 pktsize = ARASAN_NAND_PKTSIZE_1K;
324 pktsize = ARASAN_NAND_PKTSIZE_512;
327 pktnum = size/pktsize + 1;
329 pktnum = size/pktsize;
331 reg_val = readl(&arasan_nand_base->intsts_enr);
332 reg_val |= ARASAN_NAND_INT_STS_ERR_EN_MASK |
333 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK;
334 writel(reg_val, &arasan_nand_base->intsts_enr);
336 reg_val = readl(&arasan_nand_base->pkt_reg);
337 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
338 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
339 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) |
341 writel(reg_val, &arasan_nand_base->pkt_reg);
343 if (!nand->on_die_ecc_enabled) {
344 arasan_nand_enable_ecc();
345 addr_cycles = arasan_nand_get_addrcycle(mtd);
346 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
347 return ERR_ADDR_CYCLE;
349 writel((NAND_CMD_RNDOUTSTART << ARASAN_NAND_CMD_CMD2_SHIFT) |
350 NAND_CMD_RNDOUT | (addr_cycles <<
351 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT),
352 &arasan_nand_base->ecc_sprcmd_reg);
354 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
356 while (rdcount < pktnum) {
357 timeout = ARASAN_NAND_POLL_TIMEOUT;
358 while (!(readl(&arasan_nand_base->intsts_reg) &
359 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
364 puts("arasan_read_page: timedout:Buff RDY\n");
370 if (pktnum == rdcount) {
371 reg_val = readl(&arasan_nand_base->intsts_enr);
372 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
373 writel(reg_val, &arasan_nand_base->intsts_enr);
375 reg_val = readl(&arasan_nand_base->intsts_enr);
376 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
377 &arasan_nand_base->intsts_enr);
379 reg_val = readl(&arasan_nand_base->intsts_reg);
380 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
381 &arasan_nand_base->intsts_reg);
383 for (i = 0; i < pktsize/4; i++)
384 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
389 if (rdcount >= pktnum)
392 writel(ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
393 &arasan_nand_base->intsts_enr);
396 timeout = ARASAN_NAND_POLL_TIMEOUT;
398 while (!(readl(&arasan_nand_base->intsts_reg) &
399 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
404 puts("arasan rd_page timedout:Xfer CMPLT\n");
408 reg_val = readl(&arasan_nand_base->intsts_enr);
409 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
410 &arasan_nand_base->intsts_enr);
411 reg_val = readl(&arasan_nand_base->intsts_reg);
412 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
413 &arasan_nand_base->intsts_reg);
415 if (!nand->on_die_ecc_enabled) {
416 if (readl(&arasan_nand_base->intsts_reg) &
417 ARASAN_NAND_INT_STS_MUL_BIT_ERR_MASK) {
418 printf("arasan rd_page:sbiterror\n");
422 if (readl(&arasan_nand_base->intsts_reg) &
423 ARASAN_NAND_INT_STS_ERR_EN_MASK) {
424 mtd->ecc_stats.failed++;
425 printf("arasan rd_page:multibiterror\n");
433 static int arasan_nand_read_page_hwecc(struct mtd_info *mtd,
434 struct nand_chip *chip, u8 *buf, int oob_required, int page)
438 status = arasan_nand_read_page(mtd, buf, (mtd->writesize));
441 chip->ecc.read_oob(mtd, chip, page);
446 static void arasan_nand_fill_tx(const u8 *buf, int len)
448 u32 __iomem *nand = &arasan_nand_base->buf_dataport;
450 if (((unsigned long)buf & 0x3) != 0) {
451 if (((unsigned long)buf & 0x1) != 0) {
459 if (((unsigned long)buf & 0x3) != 0) {
461 writew(*(u16 *)buf, nand);
469 writel(*(u32 *)buf, nand);
476 writew(*(u16 *)buf, nand);
486 static int arasan_nand_write_page_hwecc(struct mtd_info *mtd,
487 struct nand_chip *chip, const u8 *buf, int oob_required,
490 u32 reg_val, i, pktsize, pktnum;
491 const u32 *bufptr = (const u32 *)buf;
492 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
493 u32 size = mtd->writesize;
495 u8 column_addr_cycles;
496 struct arasan_nand_info *nand = nand_get_controller_data(chip);
498 if (chip->ecc_step_ds >= ARASAN_NAND_PKTSIZE_1K)
499 pktsize = ARASAN_NAND_PKTSIZE_1K;
501 pktsize = ARASAN_NAND_PKTSIZE_512;
504 pktnum = size/pktsize + 1;
506 pktnum = size/pktsize;
508 reg_val = readl(&arasan_nand_base->pkt_reg);
509 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
510 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
511 reg_val |= (pktnum << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | pktsize;
512 writel(reg_val, &arasan_nand_base->pkt_reg);
514 if (!nand->on_die_ecc_enabled) {
515 arasan_nand_enable_ecc();
516 column_addr_cycles = (chip->onfi_params.addr_cycles &
517 ARASAN_NAND_COL_ADDR_CYCL_MASK) >>
518 ARASAN_NAND_COL_ADDR_CYCL_SHIFT;
519 writel((NAND_CMD_RNDIN | (column_addr_cycles << 28)),
520 &arasan_nand_base->ecc_sprcmd_reg);
522 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
524 while (rdcount < pktnum) {
525 timeout = ARASAN_NAND_POLL_TIMEOUT;
526 while (!(readl(&arasan_nand_base->intsts_reg) &
527 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
533 puts("arasan_write_page: timedout:Buff RDY\n");
539 if (pktnum == rdcount) {
540 reg_val = readl(&arasan_nand_base->intsts_enr);
541 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
542 writel(reg_val, &arasan_nand_base->intsts_enr);
544 reg_val = readl(&arasan_nand_base->intsts_enr);
545 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
546 &arasan_nand_base->intsts_enr);
549 reg_val = readl(&arasan_nand_base->intsts_reg);
550 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
551 &arasan_nand_base->intsts_reg);
553 for (i = 0; i < pktsize/4; i++)
554 writel(bufptr[i], &arasan_nand_base->buf_dataport);
558 if (rdcount >= pktnum)
561 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
562 &arasan_nand_base->intsts_enr);
565 timeout = ARASAN_NAND_POLL_TIMEOUT;
567 while (!(readl(&arasan_nand_base->intsts_reg) &
568 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
573 puts("arasan write_page timedout:Xfer CMPLT\n");
577 reg_val = readl(&arasan_nand_base->intsts_enr);
578 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
579 &arasan_nand_base->intsts_enr);
580 reg_val = readl(&arasan_nand_base->intsts_reg);
581 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
582 &arasan_nand_base->intsts_reg);
585 chip->ecc.write_oob(mtd, chip, nand->page);
590 static int arasan_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
593 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
594 chip->read_buf(mtd, chip->oob_poi, (mtd->oobsize));
599 static int arasan_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
603 const u8 *buf = chip->oob_poi;
605 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
606 chip->write_buf(mtd, buf, mtd->oobsize);
611 static int arasan_nand_reset(struct arasan_nand_command_format *curr_cmd)
613 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
616 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
617 &arasan_nand_base->intsts_enr);
618 cmd_reg = readl(&arasan_nand_base->cmd_reg);
619 cmd_reg &= ~ARASAN_NAND_CMD_CMD12_MASK;
621 cmd_reg |= curr_cmd->cmd1 |
622 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
623 writel(cmd_reg, &arasan_nand_base->cmd_reg);
624 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
626 while (!(readl(&arasan_nand_base->intsts_reg) &
627 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
632 printf("ERROR:%s timedout\n", __func__);
636 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
637 &arasan_nand_base->intsts_enr);
639 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
640 &arasan_nand_base->intsts_reg);
645 static u8 arasan_nand_page(struct mtd_info *mtd)
649 switch (mtd->writesize) {
669 printf("%s:Pagesize>16K\n", __func__);
676 static int arasan_nand_send_wrcmd(struct arasan_nand_command_format *curr_cmd,
677 int column, int page_addr, struct mtd_info *mtd)
680 u8 page_val, addr_cycles;
682 writel(ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
683 &arasan_nand_base->intsts_enr);
684 reg_val = readl(&arasan_nand_base->cmd_reg);
685 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
686 reg_val |= curr_cmd->cmd1 |
687 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
688 if (curr_cmd->cmd1 == NAND_CMD_SEQIN) {
689 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
690 page_val = arasan_nand_page(mtd);
691 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
694 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
695 addr_cycles = arasan_nand_get_addrcycle(mtd);
697 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
698 return ERR_ADDR_CYCLE;
700 reg_val |= (addr_cycles <<
701 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
702 writel(reg_val, &arasan_nand_base->cmd_reg);
707 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
708 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
709 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
710 writel(page|column, &arasan_nand_base->memadr_reg1);
712 reg_val = readl(&arasan_nand_base->memadr_reg2);
713 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
714 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
715 writel(reg_val, &arasan_nand_base->memadr_reg2);
716 reg_val = readl(&arasan_nand_base->memadr_reg2);
717 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
718 writel(reg_val, &arasan_nand_base->memadr_reg2);
723 static void arasan_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
726 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
728 reg_val = readl(&arasan_nand_base->pkt_reg);
729 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
730 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
732 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | len;
733 writel(reg_val, &arasan_nand_base->pkt_reg);
734 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
736 while (!(readl(&arasan_nand_base->intsts_reg) &
737 ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK) && timeout) {
743 puts("ERROR:arasan_nand_write_buf timedout:Buff RDY\n");
745 reg_val = readl(&arasan_nand_base->intsts_enr);
746 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
747 writel(reg_val, &arasan_nand_base->intsts_enr);
748 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
749 &arasan_nand_base->intsts_enr);
750 reg_val = readl(&arasan_nand_base->intsts_reg);
751 writel(reg_val | ARASAN_NAND_INT_STS_BUF_WR_RDY_MASK,
752 &arasan_nand_base->intsts_reg);
754 arasan_nand_fill_tx(buf, len);
756 timeout = ARASAN_NAND_POLL_TIMEOUT;
757 while (!(readl(&arasan_nand_base->intsts_reg) &
758 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
763 puts("ERROR:arasan_nand_write_buf timedout:Xfer CMPLT\n");
765 writel(readl(&arasan_nand_base->intsts_enr) |
766 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
767 &arasan_nand_base->intsts_enr);
768 writel(readl(&arasan_nand_base->intsts_reg) |
769 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
770 &arasan_nand_base->intsts_reg);
773 static int arasan_nand_erase(struct arasan_nand_command_format *curr_cmd,
774 int column, int page_addr, struct mtd_info *mtd)
777 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
780 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
781 &arasan_nand_base->intsts_enr);
782 reg_val = readl(&arasan_nand_base->cmd_reg);
783 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
784 reg_val |= curr_cmd->cmd1 |
785 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
786 row_addr_cycles = arasan_nand_get_addrcycle(mtd);
788 if (row_addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
789 return ERR_ADDR_CYCLE;
791 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
792 reg_val |= (row_addr_cycles <<
793 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
795 writel(reg_val, &arasan_nand_base->cmd_reg);
797 page = (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
798 ARASAN_NAND_MEM_ADDR1_COL_MASK;
799 column = page_addr & ARASAN_NAND_MEM_ADDR1_COL_MASK;
800 writel(column | (page << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT),
801 &arasan_nand_base->memadr_reg1);
803 reg_val = readl(&arasan_nand_base->memadr_reg2);
804 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
805 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
806 writel(reg_val, &arasan_nand_base->memadr_reg2);
807 reg_val = readl(&arasan_nand_base->memadr_reg2);
808 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
809 writel(reg_val, &arasan_nand_base->memadr_reg2);
810 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
812 while (!(readl(&arasan_nand_base->intsts_reg) &
813 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
818 printf("ERROR:%s timedout:Xfer CMPLT\n", __func__);
822 reg_val = readl(&arasan_nand_base->intsts_enr);
823 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
824 &arasan_nand_base->intsts_enr);
825 reg_val = readl(&arasan_nand_base->intsts_reg);
826 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
827 &arasan_nand_base->intsts_reg);
832 static int arasan_nand_read_status(struct arasan_nand_command_format *curr_cmd,
833 int column, int page_addr, struct mtd_info *mtd)
836 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
839 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
840 &arasan_nand_base->intsts_enr);
841 reg_val = readl(&arasan_nand_base->cmd_reg);
842 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
843 reg_val |= curr_cmd->cmd1 |
844 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
845 addr_cycles = arasan_nand_get_addrcycle(mtd);
847 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
848 return ERR_ADDR_CYCLE;
850 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
851 reg_val |= (addr_cycles <<
852 ARASAN_NAND_CMD_ADDR_CYCL_SHIFT);
854 writel(reg_val, &arasan_nand_base->cmd_reg);
856 reg_val = readl(&arasan_nand_base->pkt_reg);
857 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
858 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
859 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | 1;
860 writel(reg_val, &arasan_nand_base->pkt_reg);
862 reg_val = readl(&arasan_nand_base->memadr_reg2);
863 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
864 writel(reg_val, &arasan_nand_base->memadr_reg2);
866 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
867 while (!(readl(&arasan_nand_base->intsts_reg) &
868 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
874 printf("ERROR:%s: timedout:Xfer CMPLT\n", __func__);
878 reg_val = readl(&arasan_nand_base->intsts_enr);
879 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
880 &arasan_nand_base->intsts_enr);
881 reg_val = readl(&arasan_nand_base->intsts_reg);
882 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
883 &arasan_nand_base->intsts_reg);
888 static int arasan_nand_send_rdcmd(struct arasan_nand_command_format *curr_cmd,
889 int column, int page_addr, struct mtd_info *mtd)
891 u32 reg_val, addr_cycles, page;
894 reg_val = readl(&arasan_nand_base->intsts_enr);
895 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
896 &arasan_nand_base->intsts_enr);
898 reg_val = readl(&arasan_nand_base->cmd_reg);
899 reg_val &= ~ARASAN_NAND_CMD_CMD12_MASK;
900 reg_val |= curr_cmd->cmd1 |
901 (curr_cmd->cmd2 << ARASAN_NAND_CMD_CMD2_SHIFT);
903 if (curr_cmd->cmd1 == NAND_CMD_RNDOUT ||
904 curr_cmd->cmd1 == NAND_CMD_READ0) {
905 reg_val &= ~ARASAN_NAND_CMD_PG_SIZE_MASK;
906 page_val = arasan_nand_page(mtd);
907 reg_val |= (page_val << ARASAN_NAND_CMD_PG_SIZE_SHIFT);
910 reg_val &= ~ARASAN_NAND_CMD_ECC_ON_MASK;
912 reg_val &= ~ARASAN_NAND_CMD_ADDR_CYCL_MASK;
914 addr_cycles = arasan_nand_get_addrcycle(mtd);
916 if (addr_cycles == ARASAN_NAND_INVALID_ADDR_CYCL)
917 return ERR_ADDR_CYCLE;
919 reg_val |= (addr_cycles << 28);
920 writel(reg_val, &arasan_nand_base->cmd_reg);
925 page = (page_addr << ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT) &
926 ARASAN_NAND_MEM_ADDR1_PAGE_MASK;
927 column &= ARASAN_NAND_MEM_ADDR1_COL_MASK;
928 writel(page | column, &arasan_nand_base->memadr_reg1);
930 reg_val = readl(&arasan_nand_base->memadr_reg2);
931 reg_val &= ~ARASAN_NAND_MEM_ADDR2_PAGE_MASK;
932 reg_val |= (page_addr >> ARASAN_NAND_MEM_ADDR1_PAGE_SHIFT);
933 writel(reg_val, &arasan_nand_base->memadr_reg2);
935 reg_val = readl(&arasan_nand_base->memadr_reg2);
936 reg_val &= ~ARASAN_NAND_MEM_ADDR2_CS_MASK;
937 writel(reg_val, &arasan_nand_base->memadr_reg2);
943 static void arasan_nand_read_buf(struct mtd_info *mtd, u8 *buf, int size)
946 u32 *bufptr = (u32 *)buf;
947 u32 timeout = ARASAN_NAND_POLL_TIMEOUT;
949 reg_val = readl(&arasan_nand_base->pkt_reg);
950 reg_val &= ~(ARASAN_NAND_PKT_REG_PKT_CNT_MASK |
951 ARASAN_NAND_PKT_REG_PKT_SIZE_MASK);
952 reg_val |= (1 << ARASAN_NAND_PKT_REG_PKT_CNT_SHFT) | size;
953 writel(reg_val, &arasan_nand_base->pkt_reg);
955 writel(curr_cmd->pgm, &arasan_nand_base->pgm_reg);
957 while (!(readl(&arasan_nand_base->intsts_reg) &
958 ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK) && timeout) {
964 puts("ERROR:arasan_nand_read_buf timedout:Buff RDY\n");
966 reg_val = readl(&arasan_nand_base->intsts_enr);
967 reg_val |= ARASAN_NAND_INT_STS_XFR_CMPLT_MASK;
968 writel(reg_val, &arasan_nand_base->intsts_enr);
970 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
971 &arasan_nand_base->intsts_enr);
972 reg_val = readl(&arasan_nand_base->intsts_reg);
973 writel(reg_val | ARASAN_NAND_INT_STS_BUF_RD_RDY_MASK,
974 &arasan_nand_base->intsts_reg);
977 for (i = 0; i < size / 4; i++)
978 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
981 bufptr[i] = readl(&arasan_nand_base->buf_dataport);
983 timeout = ARASAN_NAND_POLL_TIMEOUT;
985 while (!(readl(&arasan_nand_base->intsts_reg) &
986 ARASAN_NAND_INT_STS_XFR_CMPLT_MASK) && timeout) {
992 puts("ERROR:arasan_nand_read_buf timedout:Xfer CMPLT\n");
994 reg_val = readl(&arasan_nand_base->intsts_enr);
995 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
996 &arasan_nand_base->intsts_enr);
997 reg_val = readl(&arasan_nand_base->intsts_reg);
998 writel(reg_val | ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
999 &arasan_nand_base->intsts_reg);
1002 static u8 arasan_nand_read_byte(struct mtd_info *mtd)
1004 struct nand_chip *chip = mtd_to_nand(mtd);
1007 struct nand_onfi_params *p;
1009 if (buf_index == 0) {
1010 p = &chip->onfi_params;
1011 if (curr_cmd->cmd1 == NAND_CMD_READID)
1013 else if (curr_cmd->cmd1 == NAND_CMD_PARAM)
1014 size = sizeof(struct nand_onfi_params);
1015 else if (curr_cmd->cmd1 == NAND_CMD_RNDOUT)
1016 size = le16_to_cpu(p->ext_param_page_length) * 16;
1017 else if (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES)
1019 else if (curr_cmd->cmd1 == NAND_CMD_STATUS)
1020 return readb(&arasan_nand_base->flash_sts_reg);
1023 chip->read_buf(mtd, &buf_data[0], size);
1026 val = *(&buf_data[0] + buf_index);
1032 static void arasan_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
1033 int column, int page_addr)
1036 struct nand_chip *chip = mtd_to_nand(mtd);
1037 struct arasan_nand_info *nand = nand_get_controller_data(chip);
1040 writel(ARASAN_NAND_INT_STS_XFR_CMPLT_MASK,
1041 &arasan_nand_base->intsts_enr);
1043 if ((command == NAND_CMD_READOOB) &&
1044 (mtd->writesize > 512)) {
1045 column += mtd->writesize;
1046 command = NAND_CMD_READ0;
1049 /* Get the command format */
1050 for (i = 0; (arasan_nand_commands[i].cmd1 != NAND_CMD_NONE ||
1051 arasan_nand_commands[i].cmd2 != NAND_CMD_NONE); i++) {
1052 if (command == arasan_nand_commands[i].cmd1) {
1053 curr_cmd = &arasan_nand_commands[i];
1058 if (curr_cmd == NULL) {
1059 printf("Unsupported Command; 0x%x\n", command);
1063 if (curr_cmd->cmd1 == NAND_CMD_RESET)
1064 ret = arasan_nand_reset(curr_cmd);
1066 if ((curr_cmd->cmd1 == NAND_CMD_READID) ||
1067 (curr_cmd->cmd1 == NAND_CMD_PARAM) ||
1068 (curr_cmd->cmd1 == NAND_CMD_RNDOUT) ||
1069 (curr_cmd->cmd1 == NAND_CMD_GET_FEATURES) ||
1070 (curr_cmd->cmd1 == NAND_CMD_READ0))
1071 ret = arasan_nand_send_rdcmd(curr_cmd, column, page_addr, mtd);
1073 if ((curr_cmd->cmd1 == NAND_CMD_SET_FEATURES) ||
1074 (curr_cmd->cmd1 == NAND_CMD_SEQIN)) {
1075 nand->page = page_addr;
1076 ret = arasan_nand_send_wrcmd(curr_cmd, column, page_addr, mtd);
1079 if (curr_cmd->cmd1 == NAND_CMD_ERASE1)
1080 ret = arasan_nand_erase(curr_cmd, column, page_addr, mtd);
1082 if (curr_cmd->cmd1 == NAND_CMD_STATUS)
1083 ret = arasan_nand_read_status(curr_cmd, column, page_addr, mtd);
1086 printf("ERROR:%s:command:0x%x\n", __func__, curr_cmd->cmd1);
1089 static void arasan_check_ondie(struct mtd_info *mtd)
1091 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1092 struct arasan_nand_info *nand = nand_get_controller_data(nand_chip);
1095 u8 set_feature[4] = {ENABLE_ONDIE_ECC, 0x00, 0x00, 0x00};
1098 /* Send the command for reading device ID */
1099 nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1100 nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0, -1);
1102 /* Read manufacturer and device IDs */
1103 maf_id = nand_chip->read_byte(mtd);
1104 dev_id = nand_chip->read_byte(mtd);
1106 if ((maf_id == NAND_MFR_MICRON) &&
1107 ((dev_id == 0xf1) || (dev_id == 0xa1) || (dev_id == 0xb1) ||
1108 (dev_id == 0xaa) || (dev_id == 0xba) || (dev_id == 0xda) ||
1109 (dev_id == 0xca) || (dev_id == 0xac) || (dev_id == 0xbc) ||
1110 (dev_id == 0xdc) || (dev_id == 0xcc) || (dev_id == 0xa3) ||
1111 (dev_id == 0xb3) || (dev_id == 0xd3) || (dev_id == 0xc3))) {
1112 nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
1113 ONDIE_ECC_FEATURE_ADDR, -1);
1115 nand_chip->write_buf(mtd, &set_feature[0], 4);
1116 nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
1117 ONDIE_ECC_FEATURE_ADDR, -1);
1119 for (i = 0; i < 4; i++)
1120 get_feature[i] = nand_chip->read_byte(mtd);
1122 if (get_feature[0] & ENABLE_ONDIE_ECC)
1123 nand->on_die_ecc_enabled = true;
1125 printf("%s: Unable to enable OnDie ECC\n", __func__);
1127 /* Use the BBT pattern descriptors */
1128 nand_chip->bbt_td = &bbt_main_descr;
1129 nand_chip->bbt_md = &bbt_mirror_descr;
1133 static int arasan_nand_ecc_init(struct mtd_info *mtd)
1136 u32 regval, eccpos_start, i, eccaddr;
1137 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1139 for (i = 0; i < ARRAY_SIZE(ecc_matrix); i++) {
1140 if ((ecc_matrix[i].pagesize == mtd->writesize) &&
1141 (ecc_matrix[i].ecc_codeword_size >=
1142 nand_chip->ecc_step_ds)) {
1143 if (ecc_matrix[i].eccbits >=
1144 nand_chip->ecc_strength_ds) {
1155 eccaddr = mtd->writesize + mtd->oobsize -
1156 ecc_matrix[found].eccsize;
1159 (ecc_matrix[found].eccsize << ARASAN_NAND_ECC_SIZE_SHIFT) |
1160 (ecc_matrix[found].bch << ARASAN_NAND_ECC_BCH_SHIFT);
1161 writel(regval, &arasan_nand_base->ecc_reg);
1163 if (ecc_matrix[found].bch) {
1164 regval = readl(&arasan_nand_base->memadr_reg2);
1165 regval &= ~ARASAN_NAND_MEM_ADDR2_BCH_MASK;
1166 regval |= (ecc_matrix[found].bchval <<
1167 ARASAN_NAND_MEM_ADDR2_BCH_SHIFT);
1168 writel(regval, &arasan_nand_base->memadr_reg2);
1171 nand_oob.eccbytes = ecc_matrix[found].eccsize;
1172 eccpos_start = mtd->oobsize - nand_oob.eccbytes;
1174 for (i = 0; i < nand_oob.eccbytes; i++)
1175 nand_oob.eccpos[i] = eccpos_start + i;
1177 nand_oob.oobfree[0].offset = 2;
1178 nand_oob.oobfree[0].length = eccpos_start - 2;
1180 nand_chip->ecc.size = ecc_matrix[found].ecc_codeword_size;
1181 nand_chip->ecc.strength = ecc_matrix[found].eccbits;
1182 nand_chip->ecc.bytes = ecc_matrix[found].eccsize;
1183 nand_chip->ecc.layout = &nand_oob;
1188 static int arasan_nand_init(struct nand_chip *nand_chip, int devnum)
1190 struct arasan_nand_info *nand;
1191 struct mtd_info *mtd;
1194 nand = calloc(1, sizeof(struct arasan_nand_info));
1196 printf("%s: failed to allocate\n", __func__);
1200 nand->nand_base = arasan_nand_base;
1201 mtd = nand_to_mtd(nand_chip);
1202 nand_set_controller_data(nand_chip, nand);
1204 /* Set the driver entry points for MTD */
1205 nand_chip->cmdfunc = arasan_nand_cmd_function;
1206 nand_chip->select_chip = arasan_nand_select_chip;
1207 nand_chip->read_byte = arasan_nand_read_byte;
1209 /* Buffer read/write routines */
1210 nand_chip->read_buf = arasan_nand_read_buf;
1211 nand_chip->write_buf = arasan_nand_write_buf;
1212 nand_chip->bbt_options = NAND_BBT_USE_FLASH;
1214 writel(0x0, &arasan_nand_base->cmd_reg);
1215 writel(0x0, &arasan_nand_base->pgm_reg);
1217 /* first scan to find the device and get the page size */
1218 if (nand_scan_ident(mtd, 1, NULL)) {
1219 printf("%s: nand_scan_ident failed\n", __func__);
1223 nand_chip->ecc.mode = NAND_ECC_HW;
1224 nand_chip->ecc.hwctl = NULL;
1225 nand_chip->ecc.read_page = arasan_nand_read_page_hwecc;
1226 nand_chip->ecc.write_page = arasan_nand_write_page_hwecc;
1227 nand_chip->ecc.read_oob = arasan_nand_read_oob;
1228 nand_chip->ecc.write_oob = arasan_nand_write_oob;
1230 arasan_check_ondie(mtd);
1233 * If on die supported, then give priority to on-die ecc and use
1234 * it instead of controller ecc.
1236 if (nand->on_die_ecc_enabled) {
1237 nand_chip->ecc.strength = 1;
1238 nand_chip->ecc.size = mtd->writesize;
1239 nand_chip->ecc.bytes = 0;
1240 nand_chip->ecc.layout = &ondie_nand_oob_64;
1242 if (arasan_nand_ecc_init(mtd)) {
1243 printf("%s: nand_ecc_init failed\n", __func__);
1248 if (nand_scan_tail(mtd)) {
1249 printf("%s: nand_scan_tail failed\n", __func__);
1253 if (nand_register(devnum, mtd)) {
1254 printf("Nand Register Fail\n");
1264 void board_nand_init(void)
1266 struct nand_chip *nand = &nand_chip[0];
1268 if (arasan_nand_init(nand, 0))
1269 puts("NAND init failed\n");