drivers/mtd/nand/omap_gpmc.c

   1 /*
   2  * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
   3  * Rohit Choraria <rohitkc@ti.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/errno.h>
  11 #include <asm/arch/mem.h>
  12 #include <linux/mtd/omap_gpmc.h>
  13 #include <linux/mtd/nand_ecc.h>
  14 #include <linux/bch.h>
  15 #include <linux/compiler.h>
  16 #include <nand.h>
  17 #include <linux/mtd/omap_elm.h>
  18
  19 #define BADBLOCK_MARKER_LENGTH  2
  20 #define SECTOR_BYTES            512
  21 #define ECCCLEAR                (0x1 << 8)
  22 #define ECCRESULTREG1           (0x1 << 0)
  23 /* 4 bit padding to make byte aligned, 56 = 52 + 4 */
  24 #define BCH4_BIT_PAD            4
  25
  26 #ifdef CONFIG_BCH
  27 static u8  bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2,
  28                                 0x97, 0x79, 0xe5, 0x24, 0xb5};
  29 #endif
  30 static uint8_t cs_next;
  31 static __maybe_unused struct nand_ecclayout omap_ecclayout;
  32
  33 #if defined(CONFIG_NAND_OMAP_GPMC_WSCFG)
  34 static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE] =
  35         { CONFIG_NAND_OMAP_GPMC_WSCFG };
  36 #else
  37 /* wscfg is preset to zero since its a static variable */
  38 static const int8_t wscfg[CONFIG_SYS_MAX_NAND_DEVICE];
  39 #endif
  40
  41 /*
  42  * Driver configurations
  43  */
  44 struct omap_nand_info {
  45         struct bch_control *control;
  46         enum omap_ecc ecc_scheme;
  47         uint8_t cs;
  48         uint8_t ws;             /* wait status pin (0,1) */
  49 };
  50
  51 /* We are wasting a bit of memory but al least we are safe */
  52 static struct omap_nand_info omap_nand_info[GPMC_MAX_CS];
  53
  54 /*
  55  * omap_nand_hwcontrol - Set the address pointers corretly for the
  56  *                      following address/data/command operation
  57  */
  58 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
  59                                 uint32_t ctrl)
  60 {
  61         register struct nand_chip *this = mtd->priv;
  62         struct omap_nand_info *info = this->priv;
  63         int cs = info->cs;
  64
  65         /*
  66          * Point the IO_ADDR to DATA and ADDRESS registers instead
  67          * of chip address
  68          */
  69         switch (ctrl) {
  70         case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
  71                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
  72                 break;
  73         case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
  74                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
  75                 break;
  76         case NAND_CTRL_CHANGE | NAND_NCE:
  77                 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
  78                 break;
  79         }
  80
  81         if (cmd != NAND_CMD_NONE)
  82                 writeb(cmd, this->IO_ADDR_W);
  83 }
  84
  85 /* Check wait pin as dev ready indicator */
  86 static int omap_dev_ready(struct mtd_info *mtd)
  87 {
  88         register struct nand_chip *this = mtd->priv;
  89         struct omap_nand_info *info = this->priv;
  90         return gpmc_cfg->status & (1 << (8 + info->ws));
  91 }
  92
  93 /*
  94  * gen_true_ecc - This function will generate true ECC value, which
  95  * can be used when correcting data read from NAND flash memory core
  96  *
  97  * @ecc_buf:    buffer to store ecc code
  98  *
  99  * @return:     re-formatted ECC value
 100  */
 101 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
 102 {
 103         return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
 104                 ((ecc_buf[2] & 0x0F) << 8);
 105 }
 106
 107 /*
 108  * omap_correct_data - Compares the ecc read from nand spare area with ECC
 109  * registers values and corrects one bit error if it has occured
 110  * Further details can be had from OMAP TRM and the following selected links:
 111  * http://en.wikipedia.org/wiki/Hamming_code
 112  * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
 113  *
 114  * @mtd:                 MTD device structure
 115  * @dat:                 page data
 116  * @read_ecc:            ecc read from nand flash
 117  * @calc_ecc:            ecc read from ECC registers
 118  *
 119  * @return 0 if data is OK or corrected, else returns -1
 120  */
 121 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 122                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 123 {
 124         uint32_t orig_ecc, new_ecc, res, hm;
 125         uint16_t parity_bits, byte;
 126         uint8_t bit;
 127
 128         /* Regenerate the orginal ECC */
 129         orig_ecc = gen_true_ecc(read_ecc);
 130         new_ecc = gen_true_ecc(calc_ecc);
 131         /* Get the XOR of real ecc */
 132         res = orig_ecc ^ new_ecc;
 133         if (res) {
 134                 /* Get the hamming width */
 135                 hm = hweight32(res);
 136                 /* Single bit errors can be corrected! */
 137                 if (hm == 12) {
 138                         /* Correctable data! */
 139                         parity_bits = res >> 16;
 140                         bit = (parity_bits & 0x7);
 141                         byte = (parity_bits >> 3) & 0x1FF;
 142                         /* Flip the bit to correct */
 143                         dat[byte] ^= (0x1 << bit);
 144                 } else if (hm == 1) {
 145                         printf("Error: Ecc is wrong\n");
 146                         /* ECC itself is corrupted */
 147                         return 2;
 148                 } else {
 149                         /*
 150                          * hm distance != parity pairs OR one, could mean 2 bit
 151                          * error OR potentially be on a blank page..
 152                          * orig_ecc: contains spare area data from nand flash.
 153                          * new_ecc: generated ecc while reading data area.
 154                          * Note: if the ecc = 0, all data bits from which it was
 155                          * generated are 0xFF.
 156                          * The 3 byte(24 bits) ecc is generated per 512byte
 157                          * chunk of a page. If orig_ecc(from spare area)
 158                          * is 0xFF && new_ecc(computed now from data area)=0x0,
 159                          * this means that data area is 0xFF and spare area is
 160                          * 0xFF. A sure sign of a erased page!
 161                          */
 162                         if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
 163                                 return 0;
 164                         printf("Error: Bad compare! failed\n");
 165                         /* detected 2 bit error */
 166                         return -1;
 167                 }
 168         }
 169         return 0;
 170 }
 171
 172 /*
 173  * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write
 174  * @mtd:        MTD device structure
 175  * @mode:       Read/Write mode
 176  */
 177 __maybe_unused
 178 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
 179 {
 180         struct nand_chip        *nand   = mtd->priv;
 181         struct omap_nand_info   *info   = nand->priv;
 182         unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
 183         unsigned int ecc_algo = 0;
 184         unsigned int bch_type = 0;
 185         unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00;
 186         u32 ecc_size_config_val = 0;
 187         u32 ecc_config_val = 0;
 188         int cs = info->cs;
 189
 190         /* configure GPMC for specific ecc-scheme */
 191         switch (info->ecc_scheme) {
 192         case OMAP_ECC_HAM1_CODE_SW:
 193                 return;
 194         case OMAP_ECC_HAM1_CODE_HW:
 195                 ecc_algo = 0x0;
 196                 bch_type = 0x0;
 197                 bch_wrapmode = 0x00;
 198                 eccsize0 = 0xFF;
 199                 eccsize1 = 0xFF;
 200                 break;
 201         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 202         case OMAP_ECC_BCH8_CODE_HW:
 203                 ecc_algo = 0x1;
 204                 bch_type = 0x1;
 205                 if (mode == NAND_ECC_WRITE) {
 206                         bch_wrapmode = 0x01;
 207                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 208                         eccsize1 = 28; /* OOB bits in nibbles per sector */
 209                 } else {
 210                         bch_wrapmode = 0x01;
 211                         eccsize0 = 26; /* ECC bits in nibbles per sector */
 212                         eccsize1 = 2;  /* non-ECC bits in nibbles per sector */
 213                 }
 214                 break;
 215         case OMAP_ECC_BCH16_CODE_HW:
 216                 ecc_algo = 0x1;
 217                 bch_type = 0x2;
 218                 if (mode == NAND_ECC_WRITE) {
 219                         bch_wrapmode = 0x01;
 220                         eccsize0 = 0;  /* extra bits in nibbles per sector */
 221                         eccsize1 = 52; /* OOB bits in nibbles per sector */
 222                 } else {
 223                         bch_wrapmode = 0x01;
 224                         eccsize0 = 52; /* ECC bits in nibbles per sector */
 225                         eccsize1 = 0;  /* non-ECC bits in nibbles per sector */
 226                 }
 227                 break;
 228         default:
 229                 return;
 230         }
 231         /* Clear ecc and enable bits */
 232         writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
 233         /* Configure ecc size for BCH */
 234         ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12);
 235         writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config);
 236
 237         /* Configure device details for BCH engine */
 238         ecc_config_val = ((ecc_algo << 16)      | /* HAM1 | BCHx */
 239                         (bch_type << 12)        | /* BCH4/BCH8/BCH16 */
 240                         (bch_wrapmode << 8)     | /* wrap mode */
 241                         (dev_width << 7)        | /* bus width */
 242                         (0x0 << 4)              | /* number of sectors */
 243                         (cs <<  1)              | /* ECC CS */
 244                         (0x1));                   /* enable ECC */
 245         writel(ecc_config_val, &gpmc_cfg->ecc_config);
 246 }
 247
 248 /*
 249  *  omap_calculate_ecc - Read ECC result
 250  *  @mtd:       MTD structure
 251  *  @dat:       unused
 252  *  @ecc_code:  ecc_code buffer
 253  *  Using noninverted ECC can be considered ugly since writing a blank
 254  *  page ie. padding will clear the ECC bytes. This is no problem as
 255  *  long nobody is trying to write data on the seemingly unused page.
 256  *  Reading an erased page will produce an ECC mismatch between
 257  *  generated and read ECC bytes that has to be dealt with separately.
 258  *  E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
 259  *  is used, the result of read will be 0x0 while the ECC offsets of the
 260  *  spare area will be 0xFF which will result in an ECC mismatch.
 261  */
 262 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 263                                 uint8_t *ecc_code)
 264 {
 265         struct nand_chip *chip = mtd->priv;
 266         struct omap_nand_info *info = chip->priv;
 267         uint32_t *ptr, val = 0;
 268         int8_t i = 0, j;
 269
 270         switch (info->ecc_scheme) {
 271         case OMAP_ECC_HAM1_CODE_HW:
 272                 val = readl(&gpmc_cfg->ecc1_result);
 273                 ecc_code[0] = val & 0xFF;
 274                 ecc_code[1] = (val >> 16) & 0xFF;
 275                 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
 276                 break;
 277 #ifdef CONFIG_BCH
 278         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 279 #endif
 280         case OMAP_ECC_BCH8_CODE_HW:
 281                 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
 282                 val = readl(ptr);
 283                 ecc_code[i++] = (val >>  0) & 0xFF;
 284                 ptr--;
 285                 for (j = 0; j < 3; j++) {
 286                         val = readl(ptr);
 287                         ecc_code[i++] = (val >> 24) & 0xFF;
 288                         ecc_code[i++] = (val >> 16) & 0xFF;
 289                         ecc_code[i++] = (val >>  8) & 0xFF;
 290                         ecc_code[i++] = (val >>  0) & 0xFF;
 291                         ptr--;
 292                 }
 293                 break;
 294         case OMAP_ECC_BCH16_CODE_HW:
 295                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
 296                 ecc_code[i++] = (val >>  8) & 0xFF;
 297                 ecc_code[i++] = (val >>  0) & 0xFF;
 298                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
 299                 ecc_code[i++] = (val >> 24) & 0xFF;
 300                 ecc_code[i++] = (val >> 16) & 0xFF;
 301                 ecc_code[i++] = (val >>  8) & 0xFF;
 302                 ecc_code[i++] = (val >>  0) & 0xFF;
 303                 val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
 304                 ecc_code[i++] = (val >> 24) & 0xFF;
 305                 ecc_code[i++] = (val >> 16) & 0xFF;
 306                 ecc_code[i++] = (val >>  8) & 0xFF;
 307                 ecc_code[i++] = (val >>  0) & 0xFF;
 308                 for (j = 3; j >= 0; j--) {
 309                         val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
 310                                                                         );
 311                         ecc_code[i++] = (val >> 24) & 0xFF;
 312                         ecc_code[i++] = (val >> 16) & 0xFF;
 313                         ecc_code[i++] = (val >>  8) & 0xFF;
 314                         ecc_code[i++] = (val >>  0) & 0xFF;
 315                 }
 316                 break;
 317         default:
 318                 return -EINVAL;
 319         }
 320         /* ECC scheme specific syndrome customizations */
 321         switch (info->ecc_scheme) {
 322         case OMAP_ECC_HAM1_CODE_HW:
 323                 break;
 324 #ifdef CONFIG_BCH
 325         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 326
 327                 for (i = 0; i < chip->ecc.bytes; i++)
 328                         *(ecc_code + i) = *(ecc_code + i) ^
 329                                                 bch8_polynomial[i];
 330                 break;
 331 #endif
 332         case OMAP_ECC_BCH8_CODE_HW:
 333                 ecc_code[chip->ecc.bytes - 1] = 0x00;
 334                 break;
 335         case OMAP_ECC_BCH16_CODE_HW:
 336                 break;
 337         default:
 338                 return -EINVAL;
 339         }
 340         return 0;
 341 }
 342
 343 #ifdef CONFIG_NAND_OMAP_ELM
 344 /*
 345  * omap_reverse_list - re-orders list elements in reverse order [internal]
 346  * @list:       pointer to start of list
 347  * @length:     length of list
 348 */
 349 static void omap_reverse_list(u8 *list, unsigned int length)
 350 {
 351         unsigned int i, j;
 352         unsigned int half_length = length / 2;
 353         u8 tmp;
 354         for (i = 0, j = length - 1; i < half_length; i++, j--) {
 355                 tmp = list[i];
 356                 list[i] = list[j];
 357                 list[j] = tmp;
 358         }
 359 }
 360
 361 /*
 362  * omap_correct_data_bch - Compares the ecc read from nand spare area
 363  * with ECC registers values and corrects one bit error if it has occured
 364  *
 365  * @mtd:        MTD device structure
 366  * @dat:        page data
 367  * @read_ecc:   ecc read from nand flash (ignored)
 368  * @calc_ecc:   ecc read from ECC registers
 369  *
 370  * @return 0 if data is OK or corrected, else returns -1
 371  */
 372 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
 373                                 uint8_t *read_ecc, uint8_t *calc_ecc)
 374 {
 375         struct nand_chip *chip = mtd->priv;
 376         struct omap_nand_info *info = chip->priv;
 377         struct nand_ecc_ctrl *ecc = &chip->ecc;
 378         uint32_t error_count = 0, error_max;
 379         uint32_t error_loc[ELM_MAX_ERROR_COUNT];
 380         enum bch_level bch_type;
 381         uint32_t i, ecc_flag = 0;
 382         uint8_t count;
 383         uint32_t byte_pos, bit_pos;
 384         int err = 0;
 385
 386         /* check calculated ecc */
 387         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 388                 if (calc_ecc[i] != 0x00)
 389                         ecc_flag = 1;
 390         }
 391         if (!ecc_flag)
 392                 return 0;
 393
 394         /* check for whether its a erased-page */
 395         ecc_flag = 0;
 396         for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
 397                 if (read_ecc[i] != 0xff)
 398                         ecc_flag = 1;
 399         }
 400         if (!ecc_flag)
 401                 return 0;
 402
 403         /*
 404          * while reading ECC result we read it in big endian.
 405          * Hence while loading to ELM we have rotate to get the right endian.
 406          */
 407         switch (info->ecc_scheme) {
 408         case OMAP_ECC_BCH8_CODE_HW:
 409                 bch_type = BCH_8_BIT;
 410                 omap_reverse_list(calc_ecc, ecc->bytes - 1);
 411                 break;
 412         case OMAP_ECC_BCH16_CODE_HW:
 413                 bch_type = BCH_16_BIT;
 414                 omap_reverse_list(calc_ecc, ecc->bytes);
 415                 break;
 416         default:
 417                 return -EINVAL;
 418         }
 419         /* use elm module to check for errors */
 420         elm_config(bch_type);
 421         err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
 422         if (err)
 423                 return err;
 424
 425         /* correct bch error */
 426         for (count = 0; count < error_count; count++) {
 427                 switch (info->ecc_scheme) {
 428                 case OMAP_ECC_BCH8_CODE_HW:
 429                         /* 14th byte in ECC is reserved to match ROM layout */
 430                         error_max = SECTOR_BYTES + (ecc->bytes - 1);
 431                         break;
 432                 case OMAP_ECC_BCH16_CODE_HW:
 433                         error_max = SECTOR_BYTES + ecc->bytes;
 434                         break;
 435                 default:
 436                         return -EINVAL;
 437                 }
 438                 byte_pos = error_max - (error_loc[count] / 8) - 1;
 439                 bit_pos  = error_loc[count] % 8;
 440                 if (byte_pos < SECTOR_BYTES) {
 441                         dat[byte_pos] ^= 1 << bit_pos;
 442                         printf("nand: bit-flip corrected @data=%d\n", byte_pos);
 443                 } else if (byte_pos < error_max) {
 444                         read_ecc[byte_pos - SECTOR_BYTES] ^= 1 << bit_pos;
 445                         printf("nand: bit-flip corrected @oob=%d\n", byte_pos -
 446                                                                 SECTOR_BYTES);
 447                 } else {
 448                         err = -EBADMSG;
 449                         printf("nand: error: invalid bit-flip location\n");
 450                 }
 451         }
 452         return (err) ? err : error_count;
 453 }
 454
 455 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
 456
 457 #define PREFETCH_CONFIG1_CS_SHIFT       24
 458 #define PREFETCH_FIFOTHRESHOLD_MAX      0x40
 459 #define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
 460 #define PREFETCH_STATUS_COUNT(val)      (val & 0x00003fff)
 461 #define PREFETCH_STATUS_FIFO_CNT(val)   ((val >> 24) & 0x7F)
 462 #define ENABLE_PREFETCH                 (1 << 7)
 463
 464 /**
 465  * omap_prefetch_enable - configures and starts prefetch transfer
 466  * @fifo_th: fifo threshold to be used for read/ write
 467  * @count: number of bytes to be transferred
 468  * @is_write: prefetch read(0) or write post(1) mode
 469  * @cs: chip select to use
 470  */
 471 static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
 472 {
 473         uint32_t val;
 474
 475         if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
 476                 return -EINVAL;
 477
 478         if (readl(&gpmc_cfg->prefetch_control))
 479                 return -EBUSY;
 480
 481         /* Set the amount of bytes to be prefetched */
 482         writel(count, &gpmc_cfg->prefetch_config2);
 483
 484         val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
 485                 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
 486         writel(val, &gpmc_cfg->prefetch_config1);
 487
 488         /*  Start the prefetch engine */
 489         writel(1, &gpmc_cfg->prefetch_control);
 490
 491         return 0;
 492 }
 493
 494 /**
 495  * omap_prefetch_reset - disables and stops the prefetch engine
 496  */
 497 static void omap_prefetch_reset(void)
 498 {
 499         writel(0, &gpmc_cfg->prefetch_control);
 500         writel(0, &gpmc_cfg->prefetch_config1);
 501 }
 502
 503 static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
 504 {
 505         int ret;
 506         uint32_t cnt;
 507         struct omap_nand_info *info = chip->priv;
 508
 509         ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
 510         if (ret < 0)
 511                 return ret;
 512
 513         do {
 514                 int i;
 515
 516                 cnt = readl(&gpmc_cfg->prefetch_status);
 517                 cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
 518
 519                 for (i = 0; i < cnt / 4; i++) {
 520                         *buf++ = readl(CONFIG_SYS_NAND_BASE);
 521                         len -= 4;
 522                 }
 523         } while (len);
 524
 525         omap_prefetch_reset();
 526
 527         return 0;
 528 }
 529
 530 static void omap_nand_read_prefetch8(struct mtd_info *mtd, uint8_t *buf, int len)
 531 {
 532         int ret;
 533         uint32_t head, tail;
 534         struct nand_chip *chip = mtd->priv;
 535
 536         /*
 537          * If the destination buffer is unaligned, start with reading
 538          * the overlap byte-wise.
 539          */
 540         head = ((uint32_t) buf) % 4;
 541         if (head) {
 542                 nand_read_buf(mtd, buf, head);
 543                 buf += head;
 544                 len -= head;
 545         }
 546
 547         /*
 548          * Only transfer multiples of 4 bytes in a pre-fetched fashion.
 549          * If there's a residue, care for it byte-wise afterwards.
 550          */
 551         tail = len % 4;
 552
 553         ret = __read_prefetch_aligned(chip, (uint32_t *) buf, len - tail);
 554         if (ret < 0) {
 555                 /* fallback in case the prefetch engine is busy */
 556                 nand_read_buf(mtd, buf, len);
 557         } else if (tail) {
 558                 buf += len - tail;
 559                 nand_read_buf(mtd, buf, tail);
 560         }
 561 }
 562 #endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
 563
 564 /**
 565  * omap_read_page_bch - hardware ecc based page read function
 566  * @mtd:        mtd info structure
 567  * @chip:       nand chip info structure
 568  * @buf:        buffer to store read data
 569  * @oob_required: caller expects OOB data read to chip->oob_poi
 570  * @page:       page number to read
 571  *
 572  */
 573 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
 574                                 uint8_t *buf, int oob_required, int page)
 575 {
 576         int i, eccsize = chip->ecc.size;
 577         int eccbytes = chip->ecc.bytes;
 578         int eccsteps = chip->ecc.steps;
 579         uint8_t *p = buf;
 580         uint8_t *ecc_calc = chip->buffers->ecccalc;
 581         uint8_t *ecc_code = chip->buffers->ecccode;
 582         uint32_t *eccpos = chip->ecc.layout->eccpos;
 583         uint8_t *oob = chip->oob_poi;
 584         uint32_t data_pos;
 585         uint32_t oob_pos;
 586
 587         data_pos = 0;
 588         /* oob area start */
 589         oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
 590         oob += chip->ecc.layout->eccpos[0];
 591
 592         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
 593                                 oob += eccbytes) {
 594                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 595                 /* read data */
 596                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, -1);
 597                 chip->read_buf(mtd, p, eccsize);
 598
 599                 /* read respective ecc from oob area */
 600                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, -1);
 601                 chip->read_buf(mtd, oob, eccbytes);
 602                 /* read syndrome */
 603                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 604
 605                 data_pos += eccsize;
 606                 oob_pos += eccbytes;
 607         }
 608
 609         for (i = 0; i < chip->ecc.total; i++)
 610                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 611
 612         eccsteps = chip->ecc.steps;
 613         p = buf;
 614
 615         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 616                 int stat;
 617
 618                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 619                 if (stat < 0)
 620                         mtd->ecc_stats.failed++;
 621                 else
 622                         mtd->ecc_stats.corrected += stat;
 623         }
 624         return 0;
 625 }
 626 #endif /* CONFIG_NAND_OMAP_ELM */
 627
 628 /*
 629  * OMAP3 BCH8 support (with BCH library)
 630  */
 631 #ifdef CONFIG_BCH
 632 /**
 633  * omap_correct_data_bch_sw - Decode received data and correct errors
 634  * @mtd: MTD device structure
 635  * @data: page data
 636  * @read_ecc: ecc read from nand flash
 637  * @calc_ecc: ecc read from HW ECC registers
 638  */
 639 static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data,
 640                                  u_char *read_ecc, u_char *calc_ecc)
 641 {
 642         int i, count;
 643         /* cannot correct more than 8 errors */
 644         unsigned int errloc[8];
 645         struct nand_chip *chip = mtd->priv;
 646         struct omap_nand_info *info = chip->priv;
 647
 648         count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
 649                                                         NULL, errloc);
 650         if (count > 0) {
 651                 /* correct errors */
 652                 for (i = 0; i < count; i++) {
 653                         /* correct data only, not ecc bytes */
 654                         if (errloc[i] < 8*512)
 655                                 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
 656                         printf("corrected bitflip %u\n", errloc[i]);
 657 #ifdef DEBUG
 658                         puts("read_ecc: ");
 659                         /*
 660                          * BCH8 have 13 bytes of ECC; BCH4 needs adoption
 661                          * here!
 662                          */
 663                         for (i = 0; i < 13; i++)
 664                                 printf("%02x ", read_ecc[i]);
 665                         puts("\n");
 666                         puts("calc_ecc: ");
 667                         for (i = 0; i < 13; i++)
 668                                 printf("%02x ", calc_ecc[i]);
 669                         puts("\n");
 670 #endif
 671                 }
 672         } else if (count < 0) {
 673                 puts("ecc unrecoverable error\n");
 674         }
 675         return count;
 676 }
 677
 678 /**
 679  * omap_free_bch - Release BCH ecc resources
 680  * @mtd: MTD device structure
 681  */
 682 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
 683 {
 684         struct nand_chip *chip = mtd->priv;
 685         struct omap_nand_info *info = chip->priv;
 686
 687         if (info->control) {
 688                 free_bch(info->control);
 689                 info->control = NULL;
 690         }
 691 }
 692 #endif /* CONFIG_BCH */
 693
 694 /**
 695  * omap_select_ecc_scheme - configures driver for particular ecc-scheme
 696  * @nand: NAND chip device structure
 697  * @ecc_scheme: ecc scheme to configure
 698  * @pagesize: number of main-area bytes per page of NAND device
 699  * @oobsize: number of OOB/spare bytes per page of NAND device
 700  */
 701 static int omap_select_ecc_scheme(struct nand_chip *nand,
 702         enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
 703         struct omap_nand_info   *info           = nand->priv;
 704         struct nand_ecclayout   *ecclayout      = &omap_ecclayout;
 705         int eccsteps = pagesize / SECTOR_BYTES;
 706         int i;
 707
 708         switch (ecc_scheme) {
 709         case OMAP_ECC_HAM1_CODE_SW:
 710                 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
 711                 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
 712                  * initialized in nand_scan_tail(), so just set ecc.mode */
 713                 info->control           = NULL;
 714                 nand->ecc.mode          = NAND_ECC_SOFT;
 715                 nand->ecc.layout        = NULL;
 716                 nand->ecc.size          = 0;
 717                 break;
 718
 719         case OMAP_ECC_HAM1_CODE_HW:
 720                 debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n");
 721                 /* check ecc-scheme requirements before updating ecc info */
 722                 if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 723                         printf("nand: error: insufficient OOB: require=%d\n", (
 724                                 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 725                         return -EINVAL;
 726                 }
 727                 info->control           = NULL;
 728                 /* populate ecc specific fields */
 729                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 730                 nand->ecc.mode          = NAND_ECC_HW;
 731                 nand->ecc.strength      = 1;
 732                 nand->ecc.size          = SECTOR_BYTES;
 733                 nand->ecc.bytes         = 3;
 734                 nand->ecc.hwctl         = omap_enable_hwecc;
 735                 nand->ecc.correct       = omap_correct_data;
 736                 nand->ecc.calculate     = omap_calculate_ecc;
 737                 /* define ecc-layout */
 738                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 739                 for (i = 0; i < ecclayout->eccbytes; i++) {
 740                         if (nand->options & NAND_BUSWIDTH_16)
 741                                 ecclayout->eccpos[i] = i + 2;
 742                         else
 743                                 ecclayout->eccpos[i] = i + 1;
 744                 }
 745                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 746                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 747                                                 BADBLOCK_MARKER_LENGTH;
 748                 break;
 749
 750         case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
 751 #ifdef CONFIG_BCH
 752                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n");
 753                 /* check ecc-scheme requirements before updating ecc info */
 754                 if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 755                         printf("nand: error: insufficient OOB: require=%d\n", (
 756                                 (13 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 757                         return -EINVAL;
 758                 }
 759                 /* check if BCH S/W library can be used for error detection */
 760                 info->control = init_bch(13, 8, 0x201b);
 761                 if (!info->control) {
 762                         printf("nand: error: could not init_bch()\n");
 763                         return -ENODEV;
 764                 }
 765                 /* populate ecc specific fields */
 766                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 767                 nand->ecc.mode          = NAND_ECC_HW;
 768                 nand->ecc.strength      = 8;
 769                 nand->ecc.size          = SECTOR_BYTES;
 770                 nand->ecc.bytes         = 13;
 771                 nand->ecc.hwctl         = omap_enable_hwecc;
 772                 nand->ecc.correct       = omap_correct_data_bch_sw;
 773                 nand->ecc.calculate     = omap_calculate_ecc;
 774                 /* define ecc-layout */
 775                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 776                 ecclayout->eccpos[0]    = BADBLOCK_MARKER_LENGTH;
 777                 for (i = 1; i < ecclayout->eccbytes; i++) {
 778                         if (i % nand->ecc.bytes)
 779                                 ecclayout->eccpos[i] =
 780                                                 ecclayout->eccpos[i - 1] + 1;
 781                         else
 782                                 ecclayout->eccpos[i] =
 783                                                 ecclayout->eccpos[i - 1] + 2;
 784                 }
 785                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 786                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 787                                                 BADBLOCK_MARKER_LENGTH;
 788                 break;
 789 #else
 790                 printf("nand: error: CONFIG_BCH required for ECC\n");
 791                 return -EINVAL;
 792 #endif
 793
 794         case OMAP_ECC_BCH8_CODE_HW:
 795 #ifdef CONFIG_NAND_OMAP_ELM
 796                 debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n");
 797                 /* check ecc-scheme requirements before updating ecc info */
 798                 if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 799                         printf("nand: error: insufficient OOB: require=%d\n", (
 800                                 (14 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 801                         return -EINVAL;
 802                 }
 803                 /* intialize ELM for ECC error detection */
 804                 elm_init();
 805                 info->control           = NULL;
 806                 /* populate ecc specific fields */
 807                 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
 808                 nand->ecc.mode          = NAND_ECC_HW;
 809                 nand->ecc.strength      = 8;
 810                 nand->ecc.size          = SECTOR_BYTES;
 811                 nand->ecc.bytes         = 14;
 812                 nand->ecc.hwctl         = omap_enable_hwecc;
 813                 nand->ecc.correct       = omap_correct_data_bch;
 814                 nand->ecc.calculate     = omap_calculate_ecc;
 815                 nand->ecc.read_page     = omap_read_page_bch;
 816                 /* define ecc-layout */
 817                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 818                 for (i = 0; i < ecclayout->eccbytes; i++)
 819                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 820                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 821                 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
 822                                                 BADBLOCK_MARKER_LENGTH;
 823                 break;
 824 #else
 825                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 826                 return -EINVAL;
 827 #endif
 828
 829         case OMAP_ECC_BCH16_CODE_HW:
 830 #ifdef CONFIG_NAND_OMAP_ELM
 831                 debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
 832                 /* check ecc-scheme requirements before updating ecc info */
 833                 if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
 834                         printf("nand: error: insufficient OOB: require=%d\n", (
 835                                 (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
 836                         return -EINVAL;
 837                 }
 838                 /* intialize ELM for ECC error detection */
 839                 elm_init();
 840                 /* populate ecc specific fields */
 841                 nand->ecc.mode          = NAND_ECC_HW;
 842                 nand->ecc.size          = SECTOR_BYTES;
 843                 nand->ecc.bytes         = 26;
 844                 nand->ecc.strength      = 16;
 845                 nand->ecc.hwctl         = omap_enable_hwecc;
 846                 nand->ecc.correct       = omap_correct_data_bch;
 847                 nand->ecc.calculate     = omap_calculate_ecc;
 848                 nand->ecc.read_page     = omap_read_page_bch;
 849                 /* define ecc-layout */
 850                 ecclayout->eccbytes     = nand->ecc.bytes * eccsteps;
 851                 for (i = 0; i < ecclayout->eccbytes; i++)
 852                         ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
 853                 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
 854                 ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
 855                                                 BADBLOCK_MARKER_LENGTH;
 856                 break;
 857 #else
 858                 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
 859                 return -EINVAL;
 860 #endif
 861         default:
 862                 debug("nand: error: ecc scheme not enabled or supported\n");
 863                 return -EINVAL;
 864         }
 865
 866         /* nand_scan_tail() sets ham1 sw ecc; hw ecc layout is set by driver */
 867         if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
 868                 nand->ecc.layout = ecclayout;
 869
 870         info->ecc_scheme = ecc_scheme;
 871         return 0;
 872 }
 873
 874 #ifndef CONFIG_SPL_BUILD
 875 /*
 876  * omap_nand_switch_ecc - switch the ECC operation between different engines
 877  * (h/w and s/w) and different algorithms (hamming and BCHx)
 878  *
 879  * @hardware            - true if one of the HW engines should be used
 880  * @eccstrength         - the number of bits that could be corrected
 881  *                        (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
 882  */
 883 int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
 884 {
 885         struct nand_chip *nand;
 886         struct mtd_info *mtd;
 887         int err = 0;
 888
 889         if (nand_curr_device < 0 ||
 890             nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 891             !nand_info[nand_curr_device].name) {
 892                 printf("nand: error: no NAND devices found\n");
 893                 return -ENODEV;
 894         }
 895
 896         mtd = &nand_info[nand_curr_device];
 897         nand = mtd->priv;
 898         nand->options |= NAND_OWN_BUFFERS;
 899         nand->options &= ~NAND_SUBPAGE_READ;
 900         /* Setup the ecc configurations again */
 901         if (hardware) {
 902                 if (eccstrength == 1) {
 903                         err = omap_select_ecc_scheme(nand,
 904                                         OMAP_ECC_HAM1_CODE_HW,
 905                                         mtd->writesize, mtd->oobsize);
 906                 } else if (eccstrength == 8) {
 907                         err = omap_select_ecc_scheme(nand,
 908                                         OMAP_ECC_BCH8_CODE_HW,
 909                                         mtd->writesize, mtd->oobsize);
 910                 } else {
 911                         printf("nand: error: unsupported ECC scheme\n");
 912                         return -EINVAL;
 913                 }
 914         } else {
 915                 if (eccstrength == 1) {
 916                         err = omap_select_ecc_scheme(nand,
 917                                         OMAP_ECC_HAM1_CODE_SW,
 918                                         mtd->writesize, mtd->oobsize);
 919                 } else if (eccstrength == 8) {
 920                         err = omap_select_ecc_scheme(nand,
 921                                         OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
 922                                         mtd->writesize, mtd->oobsize);
 923                 } else {
 924                         printf("nand: error: unsupported ECC scheme\n");
 925                         return -EINVAL;
 926                 }
 927         }
 928
 929         /* Update NAND handling after ECC mode switch */
 930         if (!err)
 931                 err = nand_scan_tail(mtd);
 932         return err;
 933 }
 934 #endif /* CONFIG_SPL_BUILD */
 935
 936 /*
 937  * Board-specific NAND initialization. The following members of the
 938  * argument are board-specific:
 939  * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
 940  * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
 941  * - cmd_ctrl: hardwarespecific function for accesing control-lines
 942  * - waitfunc: hardwarespecific function for accesing device ready/busy line
 943  * - ecc.hwctl: function to enable (reset) hardware ecc generator
 944  * - ecc.mode: mode of ecc, see defines
 945  * - chip_delay: chip dependent delay for transfering data from array to
 946  *   read regs (tR)
 947  * - options: various chip options. They can partly be set to inform
 948  *   nand_scan about special functionality. See the defines for further
 949  *   explanation
 950  */
 951 int board_nand_init(struct nand_chip *nand)
 952 {
 953         int32_t gpmc_config = 0;
 954         int cs = cs_next++;
 955         int err = 0;
 956         /*
 957          * xloader/Uboot's gpmc configuration would have configured GPMC for
 958          * nand type of memory. The following logic scans and latches on to the
 959          * first CS with NAND type memory.
 960          * TBD: need to make this logic generic to handle multiple CS NAND
 961          * devices.
 962          */
 963         while (cs < GPMC_MAX_CS) {
 964                 /* Check if NAND type is set */
 965                 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
 966                         /* Found it!! */
 967                         break;
 968                 }
 969                 cs++;
 970         }
 971         if (cs >= GPMC_MAX_CS) {
 972                 printf("nand: error: Unable to find NAND settings in "
 973                         "GPMC Configuration - quitting\n");
 974                 return -ENODEV;
 975         }
 976
 977         gpmc_config = readl(&gpmc_cfg->config);
 978         /* Disable Write protect */
 979         gpmc_config |= 0x10;
 980         writel(gpmc_config, &gpmc_cfg->config);
 981
 982         nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
 983         nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
 984         omap_nand_info[cs].control = NULL;
 985         omap_nand_info[cs].cs = cs;
 986         omap_nand_info[cs].ws = wscfg[cs];
 987         nand->priv      = &omap_nand_info[cs];
 988         nand->cmd_ctrl  = omap_nand_hwcontrol;
 989         nand->options   |= NAND_NO_PADDING | NAND_CACHEPRG;
 990         nand->chip_delay = 100;
 991         nand->ecc.layout = &omap_ecclayout;
 992
 993         /* configure driver and controller based on NAND device bus-width */
 994         gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
 995 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
 996         nand->options |= NAND_BUSWIDTH_16;
 997         writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
 998 #else
 999         nand->options &= ~NAND_BUSWIDTH_16;
1000         writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
1001 #endif
1002         /* select ECC scheme */
1003 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
1004         err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
1005                         CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE);
1006 #else
1007         /* pagesize and oobsize are not required to configure sw ecc-scheme */
1008         err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW,
1009                         0, 0);
1010 #endif
1011         if (err)
1012                 return err;
1013
1014         /* TODO: Implement for 16-bit bus width */
1015         if (nand->options & NAND_BUSWIDTH_16)
1016                 nand->read_buf = nand_read_buf16;
1017 #ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
1018         else
1019                 nand->read_buf = omap_nand_read_prefetch8;
1020 #else
1021         else
1022                 nand->read_buf = nand_read_buf;
1023 #endif
1024
1025         nand->dev_ready = omap_dev_ready;
1026
1027         return 0;
1028 }