2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/errno.h>
27 #include <asm/arch/mem.h>
28 #include <asm/arch/cpu.h>
29 #include <asm/omap_gpmc.h>
30 #include <linux/mtd/nand_ecc.h>
31 #include <linux/bch.h>
32 #include <linux/compiler.h>
35 #include <asm/arch/elm.h>
39 static __maybe_unused struct nand_ecclayout hw_nand_oob =
40 GPMC_NAND_HW_ECC_LAYOUT;
41 static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob =
42 GPMC_NAND_HW_BCH8_ECC_LAYOUT;
45 * omap_nand_hwcontrol - Set the address pointers corretly for the
46 * following address/data/command operation
48 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
51 register struct nand_chip *this = mtd->priv;
54 * Point the IO_ADDR to DATA and ADDRESS registers instead
58 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
59 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
61 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
62 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_adr;
64 case NAND_CTRL_CHANGE | NAND_NCE:
65 this->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
69 if (cmd != NAND_CMD_NONE)
70 writeb(cmd, this->IO_ADDR_W);
73 #ifdef CONFIG_SPL_BUILD
74 /* Check wait pin as dev ready indicator */
75 int omap_spl_dev_ready(struct mtd_info *mtd)
77 return gpmc_cfg->status & (1 << 8);
82 * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
84 * @mtd: MTD device structure
87 static void __maybe_unused omap_hwecc_init(struct nand_chip *chip)
90 * Init ECC Control Register
91 * Clear all ECC | Enable Reg1
93 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
94 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config);
98 * gen_true_ecc - This function will generate true ECC value, which
99 * can be used when correcting data read from NAND flash memory core
101 * @ecc_buf: buffer to store ecc code
103 * @return: re-formatted ECC value
105 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
107 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
108 ((ecc_buf[2] & 0x0F) << 8);
112 * omap_correct_data - Compares the ecc read from nand spare area with ECC
113 * registers values and corrects one bit error if it has occured
114 * Further details can be had from OMAP TRM and the following selected links:
115 * http://en.wikipedia.org/wiki/Hamming_code
116 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
118 * @mtd: MTD device structure
120 * @read_ecc: ecc read from nand flash
121 * @calc_ecc: ecc read from ECC registers
123 * @return 0 if data is OK or corrected, else returns -1
125 static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
126 uint8_t *read_ecc, uint8_t *calc_ecc)
128 uint32_t orig_ecc, new_ecc, res, hm;
129 uint16_t parity_bits, byte;
132 /* Regenerate the orginal ECC */
133 orig_ecc = gen_true_ecc(read_ecc);
134 new_ecc = gen_true_ecc(calc_ecc);
135 /* Get the XOR of real ecc */
136 res = orig_ecc ^ new_ecc;
138 /* Get the hamming width */
140 /* Single bit errors can be corrected! */
142 /* Correctable data! */
143 parity_bits = res >> 16;
144 bit = (parity_bits & 0x7);
145 byte = (parity_bits >> 3) & 0x1FF;
146 /* Flip the bit to correct */
147 dat[byte] ^= (0x1 << bit);
148 } else if (hm == 1) {
149 printf("Error: Ecc is wrong\n");
150 /* ECC itself is corrupted */
154 * hm distance != parity pairs OR one, could mean 2 bit
155 * error OR potentially be on a blank page..
156 * orig_ecc: contains spare area data from nand flash.
157 * new_ecc: generated ecc while reading data area.
158 * Note: if the ecc = 0, all data bits from which it was
159 * generated are 0xFF.
160 * The 3 byte(24 bits) ecc is generated per 512byte
161 * chunk of a page. If orig_ecc(from spare area)
162 * is 0xFF && new_ecc(computed now from data area)=0x0,
163 * this means that data area is 0xFF and spare area is
164 * 0xFF. A sure sign of a erased page!
166 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
168 printf("Error: Bad compare! failed\n");
169 /* detected 2 bit error */
177 * omap_calculate_ecc - Generate non-inverted ECC bytes.
179 * Using noninverted ECC can be considered ugly since writing a blank
180 * page ie. padding will clear the ECC bytes. This is no problem as
181 * long nobody is trying to write data on the seemingly unused page.
182 * Reading an erased page will produce an ECC mismatch between
183 * generated and read ECC bytes that has to be dealt with separately.
184 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
185 * is used, the result of read will be 0x0 while the ECC offsets of the
186 * spare area will be 0xFF which will result in an ECC mismatch.
187 * @mtd: MTD structure
189 * @ecc_code: ecc_code buffer
191 static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd,
192 const uint8_t *dat, uint8_t *ecc_code)
196 /* Start Reading from HW ECC1_Result = 0x200 */
197 val = readl(&gpmc_cfg->ecc1_result);
199 ecc_code[0] = val & 0xFF;
200 ecc_code[1] = (val >> 16) & 0xFF;
201 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
204 * Stop reading anymore ECC vals and clear old results
205 * enable will be called if more reads are required
207 writel(0x000, &gpmc_cfg->ecc_config);
213 * omap_enable_ecc - This function enables the hardware ecc functionality
214 * @mtd: MTD device structure
215 * @mode: Read/Write mode
217 static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
219 struct nand_chip *chip = mtd->priv;
220 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
225 /* Clear the ecc result registers, select ecc reg as 1 */
226 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
229 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
230 * tell all regs to generate size0 sized regs
231 * we just have a single ECC engine for all CS
233 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
234 &gpmc_cfg->ecc_size_config);
235 val = (dev_width << 7) | (cs << 1) | (0x1);
236 writel(val, &gpmc_cfg->ecc_config);
239 printf("Error: Unrecognized Mode[%d]!\n", mode);
245 * Generic BCH interface
247 struct nand_bch_priv {
251 struct bch_control *control;
259 /* GPMC ecc engine settings */
260 #define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */
261 #define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */
263 /* BCH nibbles for diff bch levels */
264 #define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1)
265 #define ECC_BCH4_NIBBLES 13
266 #define ECC_BCH8_NIBBLES 26
267 #define ECC_BCH16_NIBBLES 52
270 * This can be a single instance cause all current users have only one NAND
271 * with nearly the same setup (BCH8, some with ELM and others with sw BCH
273 * When some users with other BCH strength will exists this have to change!
275 static __maybe_unused struct nand_bch_priv bch_priv = {
276 .mode = NAND_ECC_HW_BCH,
278 .nibbles = ECC_BCH8_NIBBLES,
283 * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in
285 * @mtd: MTD device structure
286 * @mode: Read/Write mode
289 static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode)
292 uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
294 uint32_t unused_length = 0;
296 uint32_t wr_mode = BCH_WRAPMODE_6;
297 struct nand_bch_priv *bch = chip->priv;
299 /* Clear the ecc result registers, select ecc reg as 1 */
300 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control);
303 wr_mode = BCH_WRAPMODE_1;
305 switch (bch->nibbles) {
306 case ECC_BCH4_NIBBLES:
309 case ECC_BCH8_NIBBLES:
312 case ECC_BCH16_NIBBLES:
318 * This is ecc_size_config for ELM mode.
319 * Here we are using different settings for read and write access and
320 * also depending on BCH strength.
324 /* write access only setup eccsize1 config */
325 val = ((unused_length + bch->nibbles) << 22);
331 * by default eccsize0 selected for ecc1resultsize
334 val = (bch->nibbles << 12);
335 /* eccsize1 config */
336 val |= (unused_length << 22);
341 * This ecc_size_config setting is for BCH sw library.
343 * Note: we only support BCH8 currently with BCH sw library!
344 * Should be really easy to adobt to BCH4, however some omap3 have
347 * Here we are using wrapping mode 6 both for reading and writing, with:
348 * size0 = 0 (no additional protected byte in spare area)
349 * size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area)
351 val = (32 << 22) | (0 << 12);
353 /* ecc size configuration */
354 writel(val, &gpmc_cfg->ecc_size_config);
357 * Configure the ecc engine in gpmc
358 * We assume 512 Byte sector pages for access to NAND.
360 val = (1 << 16); /* enable BCH mode */
361 val |= (bch->type << 12); /* setup BCH type */
362 val |= (wr_mode << 8); /* setup wrapping mode */
363 val |= (dev_width << 7); /* setup device width (16 or 8 bit) */
364 val |= (cs << 1); /* setup chip select to work on */
365 debug("set ECC_CONFIG=0x%08x\n", val);
366 writel(val, &gpmc_cfg->ecc_config);
370 * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality
371 * @mtd: MTD device structure
372 * @mode: Read/Write mode
375 static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode)
377 struct nand_chip *chip = mtd->priv;
379 omap_hwecc_init_bch(chip, mode);
381 writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config);
385 * omap_ecc_disable - Disable H/W ECC calculation
387 * @mtd: MTD device structure
389 static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd)
391 writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config);
395 * BCH8 support (needs ELM and thus AM33xx-only)
399 * omap_read_bch8_result - Read BCH result for BCH8 level
401 * @mtd: MTD device structure
402 * @big_endian: When set read register 3 first
403 * @ecc_code: Read syndrome from BCH result registers
405 static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian,
412 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3];
413 ecc_code[i++] = readl(ptr) & 0xFF;
415 for (j = 0; j < 3; j++) {
416 ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
417 ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
418 ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
419 ecc_code[i++] = readl(ptr) & 0xFF;
423 ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0];
424 for (j = 0; j < 3; j++) {
425 ecc_code[i++] = readl(ptr) & 0xFF;
426 ecc_code[i++] = (readl(ptr) >> 8) & 0xFF;
427 ecc_code[i++] = (readl(ptr) >> 16) & 0xFF;
428 ecc_code[i++] = (readl(ptr) >> 24) & 0xFF;
431 ecc_code[i++] = readl(ptr) & 0xFF;
432 ecc_code[i++] = 0; /* 14th byte is always zero */
437 * omap_rotate_ecc_bch - Rotate the syndrome bytes
439 * @mtd: MTD device structure
440 * @calc_ecc: ECC read from ECC registers
441 * @syndrome: Rotated syndrome will be retuned in this array
444 static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc,
447 struct nand_chip *chip = mtd->priv;
448 struct nand_bch_priv *bch = chip->priv;
467 for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--)
468 syndrome[i] = calc_ecc[j];
472 * omap_calculate_ecc_bch - Read BCH ECC result
474 * @mtd: MTD structure
476 * @ecc_code: ecc_code buffer
478 static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
481 struct nand_chip *chip = mtd->priv;
482 struct nand_bch_priv *bch = chip->priv;
483 uint8_t big_endian = 1;
486 if (bch->type == ECC_BCH8)
487 omap_read_bch8_result(mtd, big_endian, ecc_code);
488 else /* BCH4 and BCH16 currently not supported */
492 * Stop reading anymore ECC vals and clear old results
493 * enable will be called if more reads are required
495 omap_ecc_disable(mtd);
501 * omap_fix_errors_bch - Correct bch error in the data
503 * @mtd: MTD device structure
504 * @data: Data read from flash
505 * @error_count:Number of errors in data
506 * @error_loc: Locations of errors in the data
509 static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data,
510 uint32_t error_count, uint32_t *error_loc)
512 struct nand_chip *chip = mtd->priv;
513 struct nand_bch_priv *bch = chip->priv;
515 uint32_t error_byte_pos;
516 uint32_t error_bit_mask;
517 uint32_t last_bit = (bch->nibbles * 4) - 1;
519 /* Flip all bits as specified by the error location array. */
520 /* FOR( each found error location flip the bit ) */
521 for (count = 0; count < error_count; count++) {
522 if (error_loc[count] > last_bit) {
523 /* Remove the ECC spare bits from correction. */
524 error_loc[count] -= (last_bit + 1);
525 /* Offset bit in data region */
526 error_byte_pos = ((512 * 8) -
527 (error_loc[count]) - 1) / 8;
529 error_bit_mask = 0x1 << (error_loc[count] % 8);
530 /* Toggle the error bit to make the correction. */
531 data[error_byte_pos] ^= error_bit_mask;
537 * omap_correct_data_bch - Compares the ecc read from nand spare area
538 * with ECC registers values and corrects one bit error if it has occured
540 * @mtd: MTD device structure
542 * @read_ecc: ecc read from nand flash (ignored)
543 * @calc_ecc: ecc read from ECC registers
545 * @return 0 if data is OK or corrected, else returns -1
547 static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
548 uint8_t *read_ecc, uint8_t *calc_ecc)
550 struct nand_chip *chip = mtd->priv;
551 struct nand_bch_priv *bch = chip->priv;
552 uint8_t syndrome[28];
553 uint32_t error_count = 0;
554 uint32_t error_loc[8];
555 uint32_t i, ecc_flag;
558 for (i = 0; i < chip->ecc.bytes; i++)
559 if (read_ecc[i] != 0xff)
566 elm_config((enum bch_level)(bch->type));
569 * while reading ECC result we read it in big endian.
570 * Hence while loading to ELM we have rotate to get the right endian.
572 omap_rotate_ecc_bch(mtd, calc_ecc, syndrome);
574 /* use elm module to check for errors */
575 if (elm_check_error(syndrome, bch->nibbles, &error_count,
577 printf("ECC: uncorrectable.\n");
581 /* correct bch error */
583 omap_fix_errors_bch(mtd, dat, error_count, error_loc);
589 * omap_read_page_bch - hardware ecc based page read function
590 * @mtd: mtd info structure
591 * @chip: nand chip info structure
592 * @buf: buffer to store read data
593 * @oob_required: caller expects OOB data read to chip->oob_poi
594 * @page: page number to read
597 static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip,
598 uint8_t *buf, int oob_required, int page)
600 int i, eccsize = chip->ecc.size;
601 int eccbytes = chip->ecc.bytes;
602 int eccsteps = chip->ecc.steps;
604 uint8_t *ecc_calc = chip->buffers->ecccalc;
605 uint8_t *ecc_code = chip->buffers->ecccode;
606 uint32_t *eccpos = chip->ecc.layout->eccpos;
607 uint8_t *oob = chip->oob_poi;
613 oob_pos = (eccsize * eccsteps) + chip->ecc.layout->eccpos[0];
614 oob += chip->ecc.layout->eccpos[0];
616 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize,
618 chip->ecc.hwctl(mtd, NAND_ECC_READ);
620 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_pos, page);
621 chip->read_buf(mtd, p, eccsize);
623 /* read respective ecc from oob area */
624 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_pos, page);
625 chip->read_buf(mtd, oob, eccbytes);
627 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
633 for (i = 0; i < chip->ecc.total; i++)
634 ecc_code[i] = chip->oob_poi[eccpos[i]];
636 eccsteps = chip->ecc.steps;
639 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
642 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
644 mtd->ecc_stats.failed++;
646 mtd->ecc_stats.corrected += stat;
650 #endif /* CONFIG_AM33XX */
653 * OMAP3 BCH8 support (with BCH library)
655 #ifdef CONFIG_NAND_OMAP_BCH8
657 * omap_calculate_ecc_bch - Read BCH ECC result
659 * @mtd: MTD device structure
660 * @dat: The pointer to data on which ecc is computed (unused here)
661 * @ecc: The ECC output buffer
663 static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat,
668 unsigned long nsectors, val1, val2, val3, val4;
670 nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1;
672 for (i = 0; i < nsectors; i++) {
673 /* Read hw-computed remainder */
674 val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]);
675 val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]);
676 val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]);
677 val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]);
680 * Add constant polynomial to remainder, in order to get an ecc
681 * sequence of 0xFFs for a buffer filled with 0xFFs.
683 *ecc++ = 0xef ^ (val4 & 0xFF);
684 *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF);
685 *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF);
686 *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF);
687 *ecc++ = 0xed ^ (val3 & 0xFF);
688 *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF);
689 *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF);
690 *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF);
691 *ecc++ = 0x97 ^ (val2 & 0xFF);
692 *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF);
693 *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF);
694 *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF);
695 *ecc++ = 0xb5 ^ (val1 & 0xFF);
699 * Stop reading anymore ECC vals and clear old results
700 * enable will be called if more reads are required
702 omap_ecc_disable(mtd);
708 * omap_correct_data_bch - Decode received data and correct errors
709 * @mtd: MTD device structure
711 * @read_ecc: ecc read from nand flash
712 * @calc_ecc: ecc read from HW ECC registers
714 static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data,
715 u_char *read_ecc, u_char *calc_ecc)
718 /* cannot correct more than 8 errors */
719 unsigned int errloc[8];
720 struct nand_chip *chip = mtd->priv;
721 struct nand_bch_priv *chip_priv = chip->priv;
722 struct bch_control *bch = chip_priv->control;
724 count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
727 for (i = 0; i < count; i++) {
728 /* correct data only, not ecc bytes */
729 if (errloc[i] < 8*512)
730 data[errloc[i]/8] ^= 1 << (errloc[i] & 7);
731 printf("corrected bitflip %u\n", errloc[i]);
735 * BCH8 have 13 bytes of ECC; BCH4 needs adoption
738 for (i = 0; i < 13; i++)
739 printf("%02x ", read_ecc[i]);
742 for (i = 0; i < 13; i++)
743 printf("%02x ", calc_ecc[i]);
747 } else if (count < 0) {
748 puts("ecc unrecoverable error\n");
754 * omap_free_bch - Release BCH ecc resources
755 * @mtd: MTD device structure
757 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
759 struct nand_chip *chip = mtd->priv;
760 struct nand_bch_priv *chip_priv = chip->priv;
761 struct bch_control *bch = NULL;
764 bch = chip_priv->control;
768 chip_priv->control = NULL;
771 #endif /* CONFIG_NAND_OMAP_BCH8 */
773 #ifndef CONFIG_SPL_BUILD
775 * omap_nand_switch_ecc - switch the ECC operation between different engines
776 * (h/w and s/w) and different algorithms (hamming and BCHx)
778 * @hardware - true if one of the HW engines should be used
779 * @eccstrength - the number of bits that could be corrected
780 * (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16)
782 void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength)
784 struct nand_chip *nand;
785 struct mtd_info *mtd;
787 if (nand_curr_device < 0 ||
788 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
789 !nand_info[nand_curr_device].name) {
790 printf("Error: Can't switch ecc, no devices available\n");
794 mtd = &nand_info[nand_curr_device];
797 nand->options |= NAND_OWN_BUFFERS;
799 /* Reset ecc interface */
800 nand->ecc.mode = NAND_ECC_NONE;
801 nand->ecc.read_page = NULL;
802 nand->ecc.write_page = NULL;
803 nand->ecc.read_oob = NULL;
804 nand->ecc.write_oob = NULL;
805 nand->ecc.hwctl = NULL;
806 nand->ecc.correct = NULL;
807 nand->ecc.calculate = NULL;
808 nand->ecc.strength = eccstrength;
810 /* Setup the ecc configurations again */
812 if (eccstrength == 1) {
813 nand->ecc.mode = NAND_ECC_HW;
814 nand->ecc.layout = &hw_nand_oob;
815 nand->ecc.size = 512;
817 nand->ecc.hwctl = omap_enable_hwecc;
818 nand->ecc.correct = omap_correct_data;
819 nand->ecc.calculate = omap_calculate_ecc;
820 omap_hwecc_init(nand);
821 printf("1-bit hamming HW ECC selected\n");
823 #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
824 else if (eccstrength == 8) {
825 nand->ecc.mode = NAND_ECC_HW;
826 nand->ecc.layout = &hw_bch8_nand_oob;
827 nand->ecc.size = 512;
829 nand->ecc.bytes = 14;
830 nand->ecc.read_page = omap_read_page_bch;
832 nand->ecc.bytes = 13;
834 nand->ecc.hwctl = omap_enable_ecc_bch;
835 nand->ecc.correct = omap_correct_data_bch;
836 nand->ecc.calculate = omap_calculate_ecc_bch;
837 omap_hwecc_init_bch(nand, NAND_ECC_READ);
838 printf("8-bit BCH HW ECC selected\n");
842 nand->ecc.mode = NAND_ECC_SOFT;
843 /* Use mtd default settings */
844 nand->ecc.layout = NULL;
846 printf("SW ECC selected\n");
849 /* Update NAND handling after ECC mode switch */
852 nand->options &= ~NAND_OWN_BUFFERS;
854 #endif /* CONFIG_SPL_BUILD */
857 * Board-specific NAND initialization. The following members of the
858 * argument are board-specific:
859 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
860 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
861 * - cmd_ctrl: hardwarespecific function for accesing control-lines
862 * - waitfunc: hardwarespecific function for accesing device ready/busy line
863 * - ecc.hwctl: function to enable (reset) hardware ecc generator
864 * - ecc.mode: mode of ecc, see defines
865 * - chip_delay: chip dependent delay for transfering data from array to
867 * - options: various chip options. They can partly be set to inform
868 * nand_scan about special functionality. See the defines for further
871 int board_nand_init(struct nand_chip *nand)
873 int32_t gpmc_config = 0;
877 * xloader/Uboot's gpmc configuration would have configured GPMC for
878 * nand type of memory. The following logic scans and latches on to the
879 * first CS with NAND type memory.
880 * TBD: need to make this logic generic to handle multiple CS NAND
883 while (cs < GPMC_MAX_CS) {
884 /* Check if NAND type is set */
885 if ((readl(&gpmc_cfg->cs[cs].config1) & 0xC00) == 0x800) {
891 if (cs >= GPMC_MAX_CS) {
892 printf("NAND: Unable to find NAND settings in "
893 "GPMC Configuration - quitting\n");
897 gpmc_config = readl(&gpmc_cfg->config);
898 /* Disable Write protect */
900 writel(gpmc_config, &gpmc_cfg->config);
902 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
903 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
905 nand->cmd_ctrl = omap_nand_hwcontrol;
906 nand->options = NAND_NO_PADDING | NAND_CACHEPRG;
907 /* If we are 16 bit dev, our gpmc config tells us that */
908 if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
909 nand->options |= NAND_BUSWIDTH_16;
911 nand->chip_delay = 100;
913 #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
915 /* AM33xx uses the ELM */
916 /* required in case of BCH */
920 * Whereas other OMAP based SoC do not have the ELM, they use the BCH
923 bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */);
924 if (!bch_priv.control) {
925 puts("Could not init_bch()\n");
929 /* BCH info that will be correct for SPL or overridden otherwise. */
930 nand->priv = &bch_priv;
933 /* Default ECC mode */
934 #if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8)
935 nand->ecc.mode = NAND_ECC_HW;
936 nand->ecc.layout = &hw_bch8_nand_oob;
937 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
938 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
939 nand->ecc.strength = 8;
940 nand->ecc.hwctl = omap_enable_ecc_bch;
941 nand->ecc.correct = omap_correct_data_bch;
942 nand->ecc.calculate = omap_calculate_ecc_bch;
944 nand->ecc.read_page = omap_read_page_bch;
946 omap_hwecc_init_bch(nand, NAND_ECC_READ);
948 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC)
949 nand->ecc.mode = NAND_ECC_SOFT;
951 nand->ecc.mode = NAND_ECC_HW;
952 nand->ecc.layout = &hw_nand_oob;
953 nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
954 nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
955 nand->ecc.hwctl = omap_enable_hwecc;
956 nand->ecc.correct = omap_correct_data;
957 nand->ecc.calculate = omap_calculate_ecc;
958 nand->ecc.strength = 1;
959 omap_hwecc_init(nand);
963 #ifdef CONFIG_SPL_BUILD
964 if (nand->options & NAND_BUSWIDTH_16)
965 nand->read_buf = nand_read_buf16;
967 nand->read_buf = nand_read_buf;
968 nand->dev_ready = omap_spl_dev_ready;