2 * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com>
3 * Rohit Choraria <rohitkc@ti.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/errno.h>
27 #include <asm/arch/mem.h>
28 #include <asm/arch/omap_gpmc.h>
29 #include <linux/mtd/nand_ecc.h>
33 static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
34 static gpmc_csx_t *gpmc_cs_base;
35 static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
38 * omap_nand_hwcontrol - Set the address pointers corretly for the
39 * following address/data/command operation
41 static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
44 register struct nand_chip *this = mtd->priv;
47 * Point the IO_ADDR to DATA and ADDRESS registers instead
51 case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
52 this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd;
54 case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
55 this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_adr;
57 case NAND_CTRL_CHANGE | NAND_NCE:
58 this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_dat;
62 if (cmd != NAND_CMD_NONE)
63 writeb(cmd, this->IO_ADDR_W);
67 * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in
69 * @mtd: MTD device structure
72 static void omap_hwecc_init(struct nand_chip *chip)
75 * Init ECC Control Register
76 * Clear all ECC | Enable Reg1
78 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
79 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_base->ecc_size_config);
83 * gen_true_ecc - This function will generate true ECC value, which
84 * can be used when correcting data read from NAND flash memory core
86 * @ecc_buf: buffer to store ecc code
88 * @return: re-formatted ECC value
90 static uint32_t gen_true_ecc(uint8_t *ecc_buf)
92 return ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xF0) << 20) |
93 ((ecc_buf[2] & 0x0F) << 8);
97 * omap_correct_data - Compares the ecc read from nand spare area with ECC
98 * registers values and corrects one bit error if it has occured
99 * Further details can be had from OMAP TRM and the following selected links:
100 * http://en.wikipedia.org/wiki/Hamming_code
101 * http://www.cs.utexas.edu/users/plaxton/c/337/05f/slides/ErrorCorrection-4.pdf
103 * @mtd: MTD device structure
105 * @read_ecc: ecc read from nand flash
106 * @calc_ecc: ecc read from ECC registers
108 * @return 0 if data is OK or corrected, else returns -1
110 static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
111 uint8_t *read_ecc, uint8_t *calc_ecc)
113 uint32_t orig_ecc, new_ecc, res, hm;
114 uint16_t parity_bits, byte;
117 /* Regenerate the orginal ECC */
118 orig_ecc = gen_true_ecc(read_ecc);
119 new_ecc = gen_true_ecc(calc_ecc);
120 /* Get the XOR of real ecc */
121 res = orig_ecc ^ new_ecc;
123 /* Get the hamming width */
125 /* Single bit errors can be corrected! */
127 /* Correctable data! */
128 parity_bits = res >> 16;
129 bit = (parity_bits & 0x7);
130 byte = (parity_bits >> 3) & 0x1FF;
131 /* Flip the bit to correct */
132 dat[byte] ^= (0x1 << bit);
133 } else if (hm == 1) {
134 printf("Error: Ecc is wrong\n");
135 /* ECC itself is corrupted */
139 * hm distance != parity pairs OR one, could mean 2 bit
140 * error OR potentially be on a blank page..
141 * orig_ecc: contains spare area data from nand flash.
142 * new_ecc: generated ecc while reading data area.
143 * Note: if the ecc = 0, all data bits from which it was
144 * generated are 0xFF.
145 * The 3 byte(24 bits) ecc is generated per 512byte
146 * chunk of a page. If orig_ecc(from spare area)
147 * is 0xFF && new_ecc(computed now from data area)=0x0,
148 * this means that data area is 0xFF and spare area is
149 * 0xFF. A sure sign of a erased page!
151 if ((orig_ecc == 0x0FFF0FFF) && (new_ecc == 0x00000000))
153 printf("Error: Bad compare! failed\n");
154 /* detected 2 bit error */
162 * omap_calculate_ecc - Generate non-inverted ECC bytes.
164 * Using noninverted ECC can be considered ugly since writing a blank
165 * page ie. padding will clear the ECC bytes. This is no problem as
166 * long nobody is trying to write data on the seemingly unused page.
167 * Reading an erased page will produce an ECC mismatch between
168 * generated and read ECC bytes that has to be dealt with separately.
169 * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC
170 * is used, the result of read will be 0x0 while the ECC offsets of the
171 * spare area will be 0xFF which will result in an ECC mismatch.
172 * @mtd: MTD structure
174 * @ecc_code: ecc_code buffer
176 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
181 /* Start Reading from HW ECC1_Result = 0x200 */
182 val = readl(&gpmc_base->ecc1_result);
184 ecc_code[0] = val & 0xFF;
185 ecc_code[1] = (val >> 16) & 0xFF;
186 ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0);
189 * Stop reading anymore ECC vals and clear old results
190 * enable will be called if more reads are required
192 writel(0x000, &gpmc_base->ecc_config);
198 * omap_enable_ecc - This function enables the hardware ecc functionality
199 * @mtd: MTD device structure
200 * @mode: Read/Write mode
202 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
204 struct nand_chip *chip = mtd->priv;
205 uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1;
210 /* Clear the ecc result registers, select ecc reg as 1 */
211 writel(ECCCLEAR | ECCRESULTREG1, &gpmc_base->ecc_control);
214 * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes
215 * tell all regs to generate size0 sized regs
216 * we just have a single ECC engine for all CS
218 writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL,
219 &gpmc_base->ecc_size_config);
220 val = (dev_width << 7) | (cs << 1) | (0x1);
221 writel(val, &gpmc_base->ecc_config);
224 printf("Error: Unrecognized Mode[%d]!\n", mode);
230 * omap_nand_switch_ecc - switch the ECC operation b/w h/w ecc and s/w ecc.
231 * The default is to come up on s/w ecc
233 * @hardware - 1 -switch to h/w ecc, 0 - s/w ecc
236 void omap_nand_switch_ecc(int32_t hardware)
238 struct nand_chip *nand;
239 struct mtd_info *mtd;
241 if (nand_curr_device < 0 ||
242 nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
243 !nand_info[nand_curr_device].name) {
244 printf("Error: Can't switch ecc, no devices available\n");
248 mtd = &nand_info[nand_curr_device];
251 nand->options |= NAND_OWN_BUFFERS;
253 /* Reset ecc interface */
254 nand->ecc.read_page = NULL;
255 nand->ecc.write_page = NULL;
256 nand->ecc.read_oob = NULL;
257 nand->ecc.write_oob = NULL;
258 nand->ecc.hwctl = NULL;
259 nand->ecc.correct = NULL;
260 nand->ecc.calculate = NULL;
262 /* Setup the ecc configurations again */
264 nand->ecc.mode = NAND_ECC_HW;
265 nand->ecc.layout = &hw_nand_oob;
266 nand->ecc.size = 512;
268 nand->ecc.hwctl = omap_enable_hwecc;
269 nand->ecc.correct = omap_correct_data;
270 nand->ecc.calculate = omap_calculate_ecc;
271 omap_hwecc_init(nand);
272 printf("HW ECC selected\n");
274 nand->ecc.mode = NAND_ECC_SOFT;
275 /* Use mtd default settings */
276 nand->ecc.layout = NULL;
277 printf("SW ECC selected\n");
280 /* Update NAND handling after ECC mode switch */
283 nand->options &= ~NAND_OWN_BUFFERS;
287 * Board-specific NAND initialization. The following members of the
288 * argument are board-specific:
289 * - IO_ADDR_R: address to read the 8 I/O lines of the flash device
290 * - IO_ADDR_W: address to write the 8 I/O lines of the flash device
291 * - cmd_ctrl: hardwarespecific function for accesing control-lines
292 * - waitfunc: hardwarespecific function for accesing device ready/busy line
293 * - ecc.hwctl: function to enable (reset) hardware ecc generator
294 * - ecc.mode: mode of ecc, see defines
295 * - chip_delay: chip dependent delay for transfering data from array to
297 * - options: various chip options. They can partly be set to inform
298 * nand_scan about special functionality. See the defines for further
301 int board_nand_init(struct nand_chip *nand)
303 int32_t gpmc_config = 0;
307 * xloader/Uboot's gpmc configuration would have configured GPMC for
308 * nand type of memory. The following logic scans and latches on to the
309 * first CS with NAND type memory.
310 * TBD: need to make this logic generic to handle multiple CS NAND
313 while (cs < GPMC_MAX_CS) {
315 * Each GPMC set for a single CS is at offset 0x30
316 * - already remapped for us
318 gpmc_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
319 (cs * GPMC_CONFIG_WIDTH));
320 /* Check if NAND type is set */
321 if ((readl(&gpmc_cs_base->config1) & 0xC00) ==
328 if (cs >= GPMC_MAX_CS) {
329 printf("NAND: Unable to find NAND settings in "
330 "GPMC Configuration - quitting\n");
334 gpmc_config = readl(&gpmc_base->config);
335 /* Disable Write protect */
337 writel(gpmc_config, &gpmc_base->config);
339 nand->IO_ADDR_R = (void __iomem *)&gpmc_cs_base->nand_dat;
340 nand->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd;
342 nand->cmd_ctrl = omap_nand_hwcontrol;
343 nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
344 /* If we are 16 bit dev, our gpmc config tells us that */
345 if ((readl(gpmc_cs_base) & 0x3000) == 0x1000)
346 nand->options |= NAND_BUSWIDTH_16;
348 nand->chip_delay = 100;
349 /* Default ECC mode */
350 nand->ecc.mode = NAND_ECC_SOFT;