3 * Platform independend driver for NDFC (NanD Flash Controller)
4 * integrated into IBM/AMCC PPC4xx cores
6 * (C) Copyright 2006-2009
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 * Based on original work by
13 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/mtd/ndfc.h>
19 #include <linux/mtd/nand_ecc.h>
20 #include <asm/processor.h>
22 #include <asm/ppc4xx.h>
24 #ifndef CONFIG_SYS_NAND_BCR
25 #define CONFIG_SYS_NAND_BCR 0x80002222
27 #ifndef CONFIG_SYS_NDFC_EBC0_CFG
28 #define CONFIG_SYS_NDFC_EBC0_CFG 0xb8400000
32 * We need to store the info, which chip-select (CS) is used for the
33 * chip number. For example on Sequoia NAND chip #0 uses
36 static int ndfc_cs[NDFC_MAX_BANKS];
38 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
40 struct nand_chip *this = mtd->priv;
41 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
43 if (cmd == NAND_CMD_NONE)
47 out_8((u8 *)(base + NDFC_CMD), cmd & 0xFF);
49 out_8((u8 *)(base + NDFC_ALE), cmd & 0xFF);
52 static int ndfc_dev_ready(struct mtd_info *mtdinfo)
54 struct nand_chip *this = mtdinfo->priv;
55 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
57 return (in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY);
60 static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
62 struct nand_chip *this = mtdinfo->priv;
63 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
66 ccr = in_be32((u32 *)(base + NDFC_CCR));
67 ccr |= NDFC_CCR_RESET_ECC;
68 out_be32((u32 *)(base + NDFC_CCR), ccr);
71 static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
72 const u_char *dat, u_char *ecc_code)
74 struct nand_chip *this = mtdinfo->priv;
75 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
79 ecc = in_be32((u32 *)(base + NDFC_ECC));
81 /* The NDFC uses Smart Media (SMC) bytes order
91 * Speedups for buffer read/write/verify
93 * NDFC allows 32bit read/write of data. So we can speed up the buffer
94 * functions. No further checking, as nand_base will always read/write
97 static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
99 struct nand_chip *this = mtdinfo->priv;
100 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
101 uint32_t *p = (uint32_t *) buf;
103 for (;len > 0; len -= 4)
104 *p++ = in_be32((u32 *)(base + NDFC_DATA));
107 #ifndef CONFIG_NAND_SPL
109 * Don't use these speedup functions in NAND boot image, since the image
110 * has to fit into 4kByte.
112 static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
114 struct nand_chip *this = mtdinfo->priv;
115 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
116 uint32_t *p = (uint32_t *) buf;
118 for (; len > 0; len -= 4)
119 out_be32((u32 *)(base + NDFC_DATA), *p++);
122 static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
124 struct nand_chip *this = mtdinfo->priv;
125 ulong base = (ulong) this->IO_ADDR_W & 0xffffff00;
126 uint32_t *p = (uint32_t *) buf;
128 for (; len > 0; len -= 4)
129 if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
136 * Read a byte from the NDFC.
138 static uint8_t ndfc_read_byte(struct mtd_info *mtd)
141 struct nand_chip *chip = mtd->priv;
143 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
144 return (uint8_t) readw(chip->IO_ADDR_R);
146 return readb(chip->IO_ADDR_R);
151 #endif /* #ifndef CONFIG_NAND_SPL */
153 void board_nand_select_device(struct nand_chip *nand, int chip)
156 * Don't use "chip" to address the NAND device,
157 * generate the cs from the address where it is encoded.
159 ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
160 int cs = ndfc_cs[chip];
162 /* Set NandFlash Core Configuration Register */
164 out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
165 out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), CONFIG_SYS_NAND_BCR);
168 static void ndfc_select_chip(struct mtd_info *mtd, int chip)
171 * Nothing to do here!
175 int board_nand_init(struct nand_chip *nand)
177 int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
178 ulong base = (ulong)nand->IO_ADDR_W & 0xffffff00;
182 * Save chip-select for this chip #
187 * Select required NAND chip in NDFC
189 board_nand_select_device(nand, chip);
191 nand->IO_ADDR_R = (void __iomem *)(base + NDFC_DATA);
192 nand->IO_ADDR_W = (void __iomem *)(base + NDFC_DATA);
193 nand->cmd_ctrl = ndfc_hwcontrol;
194 nand->chip_delay = 50;
195 nand->read_buf = ndfc_read_buf;
196 nand->dev_ready = ndfc_dev_ready;
197 nand->ecc.correct = nand_correct_data;
198 nand->ecc.hwctl = ndfc_enable_hwecc;
199 nand->ecc.calculate = ndfc_calculate_ecc;
200 nand->ecc.mode = NAND_ECC_HW;
201 nand->ecc.size = 256;
203 nand->ecc.strength = 1;
204 nand->select_chip = ndfc_select_chip;
206 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
207 nand->options |= NAND_BUSWIDTH_16;
210 #ifndef CONFIG_NAND_SPL
211 nand->write_buf = ndfc_write_buf;
212 nand->verify_buf = ndfc_verify_buf;
213 nand->read_byte = ndfc_read_byte;
218 * Setup EBC (CS0 only right now)
220 mtebc(EBC0_CFG, CONFIG_SYS_NDFC_EBC0_CFG);
222 mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
223 mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);