drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/tech/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *
  28  * This program is free software; you can redistribute it and/or modify
  29  * it under the terms of the GNU General Public License version 2 as
  30  * published by the Free Software Foundation.
  31  *
  32  */
  33
  34 /* XXX U-BOOT XXX */
  35 #if 0
  36 #include <linux/module.h>
  37 #include <linux/delay.h>
  38 #include <linux/errno.h>
  39 #include <linux/err.h>
  40 #include <linux/sched.h>
  41 #include <linux/slab.h>
  42 #include <linux/types.h>
  43 #include <linux/mtd/mtd.h>
  44 #include <linux/mtd/nand.h>
  45 #include <linux/mtd/nand_ecc.h>
  46 #include <linux/mtd/compatmac.h>
  47 #include <linux/interrupt.h>
  48 #include <linux/bitops.h>
  49 #include <linux/leds.h>
  50 #include <asm/io.h>
  51
  52 #ifdef CONFIG_MTD_PARTITIONS
  53 #include <linux/mtd/partitions.h>
  54 #endif
  55
  56 #endif
  57
  58 #include <common.h>
  59
  60 #define ENOTSUPP        524     /* Operation is not supported */
  61
  62 #if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
  63
  64 #include <malloc.h>
  65 #include <watchdog.h>
  66 #include <linux/err.h>
  67 #include <linux/mtd/compat.h>
  68 #include <linux/mtd/mtd.h>
  69 #include <linux/mtd/nand.h>
  70 #include <linux/mtd/nand_ecc.h>
  71
  72 #include <asm/io.h>
  73 #include <asm/errno.h>
  74
  75 #ifdef CONFIG_JFFS2_NAND
  76 #include <jffs2/jffs2.h>
  77 #endif
  78
  79 /* Define default oob placement schemes for large and small page devices */
  80 static struct nand_ecclayout nand_oob_8 = {
  81         .eccbytes = 3,
  82         .eccpos = {0, 1, 2},
  83         .oobfree = {
  84                 {.offset = 3,
  85                  .length = 2},
  86                 {.offset = 6,
  87                  .length = 2}}
  88 };
  89
  90 static struct nand_ecclayout nand_oob_16 = {
  91         .eccbytes = 6,
  92         .eccpos = {0, 1, 2, 3, 6, 7},
  93         .oobfree = {
  94                 {.offset = 8,
  95                  . length = 8}}
  96 };
  97
  98 static struct nand_ecclayout nand_oob_64 = {
  99         .eccbytes = 24,
 100         .eccpos = {
 101                    40, 41, 42, 43, 44, 45, 46, 47,
 102                    48, 49, 50, 51, 52, 53, 54, 55,
 103                    56, 57, 58, 59, 60, 61, 62, 63},
 104         .oobfree = {
 105                 {.offset = 2,
 106                  .length = 38}}
 107 };
 108
 109 static struct nand_ecclayout nand_oob_128 = {
 110         .eccbytes = 48,
 111         .eccpos = {
 112                     80,  81,  82,  83,  84,  85,  86,  87,
 113                     88,  89,  90,  91,  92,  93,  94,  95,
 114                     96,  97,  98,  99, 100, 101, 102, 103,
 115                    104, 105, 106, 107, 108, 109, 110, 111,
 116                    112, 113, 114, 115, 116, 117, 118, 119,
 117                    120, 121, 122, 123, 124, 125, 126, 127},
 118         .oobfree = {
 119                 {.offset = 2,
 120                  .length = 78}}
 121 };
 122
 123
 124 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 125                            int new_state);
 126
 127 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 128                              struct mtd_oob_ops *ops);
 129
 130 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this);
 131
 132 /*
 133  * For devices which display every fart in the system on a seperate LED. Is
 134  * compiled away when LED support is disabled.
 135  */
 136 /* XXX U-BOOT XXX */
 137 #if 0
 138 DEFINE_LED_TRIGGER(nand_led_trigger);
 139 #endif
 140
 141 /**
 142  * nand_release_device - [GENERIC] release chip
 143  * @mtd:        MTD device structure
 144  *
 145  * Deselect, release chip lock and wake up anyone waiting on the device
 146  */
 147 /* XXX U-BOOT XXX */
 148 #if 0
 149 static void nand_release_device(struct mtd_info *mtd)
 150 {
 151         struct nand_chip *chip = mtd->priv;
 152
 153         /* De-select the NAND device */
 154         chip->select_chip(mtd, -1);
 155
 156         /* Release the controller and the chip */
 157         spin_lock(&chip->controller->lock);
 158         chip->controller->active = NULL;
 159         chip->state = FL_READY;
 160         wake_up(&chip->controller->wq);
 161         spin_unlock(&chip->controller->lock);
 162 }
 163 #else
 164 static void nand_release_device (struct mtd_info *mtd)
 165 {
 166         struct nand_chip *this = mtd->priv;
 167         this->select_chip(mtd, -1);     /* De-select the NAND device */
 168 }
 169 #endif
 170
 171 /**
 172  * nand_read_byte - [DEFAULT] read one byte from the chip
 173  * @mtd:        MTD device structure
 174  *
 175  * Default read function for 8bit buswith
 176  */
 177 static uint8_t nand_read_byte(struct mtd_info *mtd)
 178 {
 179         struct nand_chip *chip = mtd->priv;
 180         return readb(chip->IO_ADDR_R);
 181 }
 182
 183 /**
 184  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 185  * @mtd:        MTD device structure
 186  *
 187  * Default read function for 16bit buswith with
 188  * endianess conversion
 189  */
 190 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 191 {
 192         struct nand_chip *chip = mtd->priv;
 193         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 194 }
 195
 196 /**
 197  * nand_read_word - [DEFAULT] read one word from the chip
 198  * @mtd:        MTD device structure
 199  *
 200  * Default read function for 16bit buswith without
 201  * endianess conversion
 202  */
 203 static u16 nand_read_word(struct mtd_info *mtd)
 204 {
 205         struct nand_chip *chip = mtd->priv;
 206         return readw(chip->IO_ADDR_R);
 207 }
 208
 209 /**
 210  * nand_select_chip - [DEFAULT] control CE line
 211  * @mtd:        MTD device structure
 212  * @chipnr:     chipnumber to select, -1 for deselect
 213  *
 214  * Default select function for 1 chip devices.
 215  */
 216 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 217 {
 218         struct nand_chip *chip = mtd->priv;
 219
 220         switch (chipnr) {
 221         case -1:
 222                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 223                 break;
 224         case 0:
 225                 break;
 226
 227         default:
 228                 BUG();
 229         }
 230 }
 231
 232 /**
 233  * nand_write_buf - [DEFAULT] write buffer to chip
 234  * @mtd:        MTD device structure
 235  * @buf:        data buffer
 236  * @len:        number of bytes to write
 237  *
 238  * Default write function for 8bit buswith
 239  */
 240 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 241 {
 242         int i;
 243         struct nand_chip *chip = mtd->priv;
 244
 245         for (i = 0; i < len; i++)
 246                 writeb(buf[i], chip->IO_ADDR_W);
 247 }
 248
 249 /**
 250  * nand_read_buf - [DEFAULT] read chip data into buffer
 251  * @mtd:        MTD device structure
 252  * @buf:        buffer to store date
 253  * @len:        number of bytes to read
 254  *
 255  * Default read function for 8bit buswith
 256  */
 257 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 258 {
 259         int i;
 260         struct nand_chip *chip = mtd->priv;
 261
 262         for (i = 0; i < len; i++)
 263                 buf[i] = readb(chip->IO_ADDR_R);
 264 }
 265
 266 /**
 267  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 268  * @mtd:        MTD device structure
 269  * @buf:        buffer containing the data to compare
 270  * @len:        number of bytes to compare
 271  *
 272  * Default verify function for 8bit buswith
 273  */
 274 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 275 {
 276         int i;
 277         struct nand_chip *chip = mtd->priv;
 278
 279         for (i = 0; i < len; i++)
 280                 if (buf[i] != readb(chip->IO_ADDR_R))
 281                         return -EFAULT;
 282         return 0;
 283 }
 284
 285 /**
 286  * nand_write_buf16 - [DEFAULT] write buffer to chip
 287  * @mtd:        MTD device structure
 288  * @buf:        data buffer
 289  * @len:        number of bytes to write
 290  *
 291  * Default write function for 16bit buswith
 292  */
 293 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 294 {
 295         int i;
 296         struct nand_chip *chip = mtd->priv;
 297         u16 *p = (u16 *) buf;
 298         len >>= 1;
 299
 300         for (i = 0; i < len; i++)
 301                 writew(p[i], chip->IO_ADDR_W);
 302
 303 }
 304
 305 /**
 306  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 307  * @mtd:        MTD device structure
 308  * @buf:        buffer to store date
 309  * @len:        number of bytes to read
 310  *
 311  * Default read function for 16bit buswith
 312  */
 313 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 314 {
 315         int i;
 316         struct nand_chip *chip = mtd->priv;
 317         u16 *p = (u16 *) buf;
 318         len >>= 1;
 319
 320         for (i = 0; i < len; i++)
 321                 p[i] = readw(chip->IO_ADDR_R);
 322 }
 323
 324 /**
 325  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 326  * @mtd:        MTD device structure
 327  * @buf:        buffer containing the data to compare
 328  * @len:        number of bytes to compare
 329  *
 330  * Default verify function for 16bit buswith
 331  */
 332 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 333 {
 334         int i;
 335         struct nand_chip *chip = mtd->priv;
 336         u16 *p = (u16 *) buf;
 337         len >>= 1;
 338
 339         for (i = 0; i < len; i++)
 340                 if (p[i] != readw(chip->IO_ADDR_R))
 341                         return -EFAULT;
 342
 343         return 0;
 344 }
 345
 346 /**
 347  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 348  * @mtd:        MTD device structure
 349  * @ofs:        offset from device start
 350  * @getchip:    0, if the chip is already selected
 351  *
 352  * Check, if the block is bad.
 353  */
 354 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 355 {
 356         int page, chipnr, res = 0;
 357         struct nand_chip *chip = mtd->priv;
 358         u16 bad;
 359
 360         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 361
 362         if (getchip) {
 363                 chipnr = (int)(ofs >> chip->chip_shift);
 364
 365                 nand_get_device(chip, mtd, FL_READING);
 366
 367                 /* Select the NAND device */
 368                 chip->select_chip(mtd, chipnr);
 369         }
 370
 371         if (chip->options & NAND_BUSWIDTH_16) {
 372                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 373                               page);
 374                 bad = cpu_to_le16(chip->read_word(mtd));
 375                 if (chip->badblockpos & 0x1)
 376                         bad >>= 8;
 377                 if ((bad & 0xFF) != 0xff)
 378                         res = 1;
 379         } else {
 380                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 381                 if (chip->read_byte(mtd) != 0xff)
 382                         res = 1;
 383         }
 384
 385         if (getchip)
 386                 nand_release_device(mtd);
 387
 388         return res;
 389 }
 390
 391 /**
 392  * nand_default_block_markbad - [DEFAULT] mark a block bad
 393  * @mtd:        MTD device structure
 394  * @ofs:        offset from device start
 395  *
 396  * This is the default implementation, which can be overridden by
 397  * a hardware specific driver.
 398 */
 399 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 400 {
 401         struct nand_chip *chip = mtd->priv;
 402         uint8_t buf[2] = { 0, 0 };
 403         int block, ret;
 404
 405         /* Get block number */
 406         block = (int)(ofs >> chip->bbt_erase_shift);
 407         if (chip->bbt)
 408                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 409
 410         /* Do we have a flash based bad block table ? */
 411         if (chip->options & NAND_USE_FLASH_BBT)
 412                 ret = nand_update_bbt(mtd, ofs);
 413         else {
 414                 /* We write two bytes, so we dont have to mess with 16 bit
 415                  * access
 416                  */
 417                 ofs += mtd->oobsize;
 418                 chip->ops.len = chip->ops.ooblen = 2;
 419                 chip->ops.datbuf = NULL;
 420                 chip->ops.oobbuf = buf;
 421                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 422
 423                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 424         }
 425         if (!ret)
 426                 mtd->ecc_stats.badblocks++;
 427         return ret;
 428 }
 429
 430 /**
 431  * nand_check_wp - [GENERIC] check if the chip is write protected
 432  * @mtd:        MTD device structure
 433  * Check, if the device is write protected
 434  *
 435  * The function expects, that the device is already selected
 436  */
 437 static int nand_check_wp(struct mtd_info *mtd)
 438 {
 439         struct nand_chip *chip = mtd->priv;
 440         /* Check the WP bit */
 441         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 442         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 443 }
 444
 445 /**
 446  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 447  * @mtd:        MTD device structure
 448  * @ofs:        offset from device start
 449  * @getchip:    0, if the chip is already selected
 450  * @allowbbt:   1, if its allowed to access the bbt area
 451  *
 452  * Check, if the block is bad. Either by reading the bad block table or
 453  * calling of the scan function.
 454  */
 455 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 456                                int allowbbt)
 457 {
 458         struct nand_chip *chip = mtd->priv;
 459
 460         if (!(chip->options & NAND_BBT_SCANNED)) {
 461                 chip->scan_bbt(mtd);
 462                 chip->options |= NAND_BBT_SCANNED;
 463         }
 464
 465         if (!chip->bbt)
 466                 return chip->block_bad(mtd, ofs, getchip);
 467
 468         /* Return info from the table */
 469         return nand_isbad_bbt(mtd, ofs, allowbbt);
 470 }
 471
 472 /*
 473  * Wait for the ready pin, after a command
 474  * The timeout is catched later.
 475  */
 476 /* XXX U-BOOT XXX */
 477 #if 0
 478 void nand_wait_ready(struct mtd_info *mtd)
 479 {
 480         struct nand_chip *chip = mtd->priv;
 481         unsigned long timeo = jiffies + 2;
 482
 483         led_trigger_event(nand_led_trigger, LED_FULL);
 484         /* wait until command is processed or timeout occures */
 485         do {
 486                 if (chip->dev_ready(mtd))
 487                         break;
 488                 touch_softlockup_watchdog();
 489         } while (time_before(jiffies, timeo));
 490         led_trigger_event(nand_led_trigger, LED_OFF);
 491 }
 492 EXPORT_SYMBOL_GPL(nand_wait_ready);
 493 #else
 494 void nand_wait_ready(struct mtd_info *mtd)
 495 {
 496         struct nand_chip *chip = mtd->priv;
 497         u32 timeo = (CFG_HZ * 20) / 1000;
 498
 499         reset_timer();
 500
 501         /* wait until command is processed or timeout occures */
 502         while (get_timer(0) < timeo) {
 503                 if (chip->dev_ready)
 504                         if (chip->dev_ready(mtd))
 505                                 break;
 506         }
 507 }
 508 #endif
 509
 510 /**
 511  * nand_command - [DEFAULT] Send command to NAND device
 512  * @mtd:        MTD device structure
 513  * @command:    the command to be sent
 514  * @column:     the column address for this command, -1 if none
 515  * @page_addr:  the page address for this command, -1 if none
 516  *
 517  * Send command to NAND device. This function is used for small page
 518  * devices (256/512 Bytes per page)
 519  */
 520 static void nand_command(struct mtd_info *mtd, unsigned int command,
 521                          int column, int page_addr)
 522 {
 523         register struct nand_chip *chip = mtd->priv;
 524         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 525
 526         /*
 527          * Write out the command to the device.
 528          */
 529         if (command == NAND_CMD_SEQIN) {
 530                 int readcmd;
 531
 532                 if (column >= mtd->writesize) {
 533                         /* OOB area */
 534                         column -= mtd->writesize;
 535                         readcmd = NAND_CMD_READOOB;
 536                 } else if (column < 256) {
 537                         /* First 256 bytes --> READ0 */
 538                         readcmd = NAND_CMD_READ0;
 539                 } else {
 540                         column -= 256;
 541                         readcmd = NAND_CMD_READ1;
 542                 }
 543                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 544                 ctrl &= ~NAND_CTRL_CHANGE;
 545         }
 546         chip->cmd_ctrl(mtd, command, ctrl);
 547
 548         /*
 549          * Address cycle, when necessary
 550          */
 551         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 552         /* Serially input address */
 553         if (column != -1) {
 554                 /* Adjust columns for 16 bit buswidth */
 555                 if (chip->options & NAND_BUSWIDTH_16)
 556                         column >>= 1;
 557                 chip->cmd_ctrl(mtd, column, ctrl);
 558                 ctrl &= ~NAND_CTRL_CHANGE;
 559         }
 560         if (page_addr != -1) {
 561                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 562                 ctrl &= ~NAND_CTRL_CHANGE;
 563                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 564                 /* One more address cycle for devices > 32MiB */
 565                 if (chip->chipsize > (32 << 20))
 566                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 567         }
 568         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 569
 570         /*
 571          * program and erase have their own busy handlers
 572          * status and sequential in needs no delay
 573          */
 574         switch (command) {
 575
 576         case NAND_CMD_PAGEPROG:
 577         case NAND_CMD_ERASE1:
 578         case NAND_CMD_ERASE2:
 579         case NAND_CMD_SEQIN:
 580         case NAND_CMD_STATUS:
 581                 return;
 582
 583         case NAND_CMD_RESET:
 584                 if (chip->dev_ready)
 585                         break;
 586                 udelay(chip->chip_delay);
 587                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 588                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 589                 chip->cmd_ctrl(mtd,
 590                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 591                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 592                 return;
 593
 594                 /* This applies to read commands */
 595         default:
 596                 /*
 597                  * If we don't have access to the busy pin, we apply the given
 598                  * command delay
 599                  */
 600                 if (!chip->dev_ready) {
 601                         udelay(chip->chip_delay);
 602                         return;
 603                 }
 604         }
 605         /* Apply this short delay always to ensure that we do wait tWB in
 606          * any case on any machine. */
 607         ndelay(100);
 608
 609         nand_wait_ready(mtd);
 610 }
 611
 612 /**
 613  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 614  * @mtd:        MTD device structure
 615  * @command:    the command to be sent
 616  * @column:     the column address for this command, -1 if none
 617  * @page_addr:  the page address for this command, -1 if none
 618  *
 619  * Send command to NAND device. This is the version for the new large page
 620  * devices We dont have the separate regions as we have in the small page
 621  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 622  */
 623 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 624                             int column, int page_addr)
 625 {
 626         register struct nand_chip *chip = mtd->priv;
 627
 628         /* Emulate NAND_CMD_READOOB */
 629         if (command == NAND_CMD_READOOB) {
 630                 column += mtd->writesize;
 631                 command = NAND_CMD_READ0;
 632         }
 633
 634         /* Command latch cycle */
 635         chip->cmd_ctrl(mtd, command & 0xff,
 636                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 637
 638         if (column != -1 || page_addr != -1) {
 639                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 640
 641                 /* Serially input address */
 642                 if (column != -1) {
 643                         /* Adjust columns for 16 bit buswidth */
 644                         if (chip->options & NAND_BUSWIDTH_16)
 645                                 column >>= 1;
 646                         chip->cmd_ctrl(mtd, column, ctrl);
 647                         ctrl &= ~NAND_CTRL_CHANGE;
 648                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 649                 }
 650                 if (page_addr != -1) {
 651                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 652                         chip->cmd_ctrl(mtd, page_addr >> 8,
 653                                        NAND_NCE | NAND_ALE);
 654                         /* One more address cycle for devices > 128MiB */
 655                         if (chip->chipsize > (128 << 20))
 656                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 657                                                NAND_NCE | NAND_ALE);
 658                 }
 659         }
 660         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 661
 662         /*
 663          * program and erase have their own busy handlers
 664          * status, sequential in, and deplete1 need no delay
 665          */
 666         switch (command) {
 667
 668         case NAND_CMD_CACHEDPROG:
 669         case NAND_CMD_PAGEPROG:
 670         case NAND_CMD_ERASE1:
 671         case NAND_CMD_ERASE2:
 672         case NAND_CMD_SEQIN:
 673         case NAND_CMD_RNDIN:
 674         case NAND_CMD_STATUS:
 675         case NAND_CMD_DEPLETE1:
 676                 return;
 677
 678                 /*
 679                  * read error status commands require only a short delay
 680                  */
 681         case NAND_CMD_STATUS_ERROR:
 682         case NAND_CMD_STATUS_ERROR0:
 683         case NAND_CMD_STATUS_ERROR1:
 684         case NAND_CMD_STATUS_ERROR2:
 685         case NAND_CMD_STATUS_ERROR3:
 686                 udelay(chip->chip_delay);
 687                 return;
 688
 689         case NAND_CMD_RESET:
 690                 if (chip->dev_ready)
 691                         break;
 692                 udelay(chip->chip_delay);
 693                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 694                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 695                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 696                                NAND_NCE | NAND_CTRL_CHANGE);
 697                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 698                 return;
 699
 700         case NAND_CMD_RNDOUT:
 701                 /* No ready / busy check necessary */
 702                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 703                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 704                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 705                                NAND_NCE | NAND_CTRL_CHANGE);
 706                 return;
 707
 708         case NAND_CMD_READ0:
 709                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 710                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 711                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 712                                NAND_NCE | NAND_CTRL_CHANGE);
 713
 714                 /* This applies to read commands */
 715         default:
 716                 /*
 717                  * If we don't have access to the busy pin, we apply the given
 718                  * command delay
 719                  */
 720                 if (!chip->dev_ready) {
 721                         udelay(chip->chip_delay);
 722                         return;
 723                 }
 724         }
 725
 726         /* Apply this short delay always to ensure that we do wait tWB in
 727          * any case on any machine. */
 728         ndelay(100);
 729
 730         nand_wait_ready(mtd);
 731 }
 732
 733 /**
 734  * nand_get_device - [GENERIC] Get chip for selected access
 735  * @chip:       the nand chip descriptor
 736  * @mtd:        MTD device structure
 737  * @new_state:  the state which is requested
 738  *
 739  * Get the device and lock it for exclusive access
 740  */
 741 /* XXX U-BOOT XXX */
 742 #if 0
 743 static int
 744 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 745 {
 746         spinlock_t *lock = &chip->controller->lock;
 747         wait_queue_head_t *wq = &chip->controller->wq;
 748         DECLARE_WAITQUEUE(wait, current);
 749  retry:
 750         spin_lock(lock);
 751
 752         /* Hardware controller shared among independend devices */
 753         /* Hardware controller shared among independend devices */
 754         if (!chip->controller->active)
 755                 chip->controller->active = chip;
 756
 757         if (chip->controller->active == chip && chip->state == FL_READY) {
 758                 chip->state = new_state;
 759                 spin_unlock(lock);
 760                 return 0;
 761         }
 762         if (new_state == FL_PM_SUSPENDED) {
 763                 spin_unlock(lock);
 764                 return (chip->state == FL_PM_SUSPENDED) ? 0 : -EAGAIN;
 765         }
 766         set_current_state(TASK_UNINTERRUPTIBLE);
 767         add_wait_queue(wq, &wait);
 768         spin_unlock(lock);
 769         schedule();
 770         remove_wait_queue(wq, &wait);
 771         goto retry;
 772 }
 773 #else
 774 static int nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int new_state)
 775 {
 776         return 0;
 777 }
 778 #endif
 779
 780 /**
 781  * nand_wait - [DEFAULT]  wait until the command is done
 782  * @mtd:        MTD device structure
 783  * @chip:       NAND chip structure
 784  *
 785  * Wait for command done. This applies to erase and program only
 786  * Erase can take up to 400ms and program up to 20ms according to
 787  * general NAND and SmartMedia specs
 788  */
 789 /* XXX U-BOOT XXX */
 790 #if 0
 791 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 792 {
 793
 794         unsigned long timeo = jiffies;
 795         int status, state = chip->state;
 796
 797         if (state == FL_ERASING)
 798                 timeo += (HZ * 400) / 1000;
 799         else
 800                 timeo += (HZ * 20) / 1000;
 801
 802         led_trigger_event(nand_led_trigger, LED_FULL);
 803
 804         /* Apply this short delay always to ensure that we do wait tWB in
 805          * any case on any machine. */
 806         ndelay(100);
 807
 808         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 809                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 810         else
 811                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 812
 813         while (time_before(jiffies, timeo)) {
 814                 if (chip->dev_ready) {
 815                         if (chip->dev_ready(mtd))
 816                                 break;
 817                 } else {
 818                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 819                                 break;
 820                 }
 821                 cond_resched();
 822         }
 823         led_trigger_event(nand_led_trigger, LED_OFF);
 824
 825         status = (int)chip->read_byte(mtd);
 826         return status;
 827 }
 828 #else
 829 static int nand_wait(struct mtd_info *mtd, struct nand_chip *this)
 830 {
 831         unsigned long   timeo;
 832         int state = this->state;
 833
 834         if (state == FL_ERASING)
 835                 timeo = (CFG_HZ * 400) / 1000;
 836         else
 837                 timeo = (CFG_HZ * 20) / 1000;
 838
 839         if ((state == FL_ERASING) && (this->options & NAND_IS_AND))
 840                 this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 841         else
 842                 this->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 843
 844         reset_timer();
 845
 846         while (1) {
 847                 if (get_timer(0) > timeo) {
 848                         printf("Timeout!");
 849                         return 0x01;
 850                 }
 851
 852                 if (this->dev_ready) {
 853                         if (this->dev_ready(mtd))
 854                                 break;
 855                 } else {
 856                         if (this->read_byte(mtd) & NAND_STATUS_READY)
 857                                 break;
 858                 }
 859         }
 860 #ifdef PPCHAMELON_NAND_TIMER_HACK
 861         reset_timer();
 862         while (get_timer(0) < 10);
 863 #endif /*  PPCHAMELON_NAND_TIMER_HACK */
 864
 865         return this->read_byte(mtd);
 866 }
 867 #endif
 868
 869 /**
 870  * nand_read_page_raw - [Intern] read raw page data without ecc
 871  * @mtd:        mtd info structure
 872  * @chip:       nand chip info structure
 873  * @buf:        buffer to store read data
 874  */
 875 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 876                               uint8_t *buf)
 877 {
 878         chip->read_buf(mtd, buf, mtd->writesize);
 879         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 880         return 0;
 881 }
 882
 883 /**
 884  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 885  * @mtd:        mtd info structure
 886  * @chip:       nand chip info structure
 887  * @buf:        buffer to store read data
 888  */
 889 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 890                                 uint8_t *buf)
 891 {
 892         int i, eccsize = chip->ecc.size;
 893         int eccbytes = chip->ecc.bytes;
 894         int eccsteps = chip->ecc.steps;
 895         uint8_t *p = buf;
 896         uint8_t *ecc_calc = chip->buffers->ecccalc;
 897         uint8_t *ecc_code = chip->buffers->ecccode;
 898         uint32_t *eccpos = chip->ecc.layout->eccpos;
 899
 900         chip->ecc.read_page_raw(mtd, chip, buf);
 901
 902         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 903                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 904
 905         for (i = 0; i < chip->ecc.total; i++)
 906                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 907
 908         eccsteps = chip->ecc.steps;
 909         p = buf;
 910
 911         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 912                 int stat;
 913
 914                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 915                 if (stat == -1)
 916                         mtd->ecc_stats.failed++;
 917                 else
 918                         mtd->ecc_stats.corrected += stat;
 919         }
 920         return 0;
 921 }
 922
 923 /**
 924  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
 925  * @mtd:        mtd info structure
 926  * @chip:       nand chip info structure
 927  * @buf:        buffer to store read data
 928  *
 929  * Not for syndrome calculating ecc controllers which need a special oob layout
 930  */
 931 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 932                                 uint8_t *buf)
 933 {
 934         int i, eccsize = chip->ecc.size;
 935         int eccbytes = chip->ecc.bytes;
 936         int eccsteps = chip->ecc.steps;
 937         uint8_t *p = buf;
 938         uint8_t *ecc_calc = chip->buffers->ecccalc;
 939         uint8_t *ecc_code = chip->buffers->ecccode;
 940         uint32_t *eccpos = chip->ecc.layout->eccpos;
 941
 942         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 943                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 944                 chip->read_buf(mtd, p, eccsize);
 945                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 946         }
 947         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 948
 949         for (i = 0; i < chip->ecc.total; i++)
 950                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 951
 952         eccsteps = chip->ecc.steps;
 953         p = buf;
 954
 955         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 956                 int stat;
 957
 958                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 959                 if (stat == -1)
 960                         mtd->ecc_stats.failed++;
 961                 else
 962                         mtd->ecc_stats.corrected += stat;
 963         }
 964         return 0;
 965 }
 966
 967 /**
 968  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
 969  * @mtd:        mtd info structure
 970  * @chip:       nand chip info structure
 971  * @buf:        buffer to store read data
 972  *
 973  * The hw generator calculates the error syndrome automatically. Therefor
 974  * we need a special oob layout and handling.
 975  */
 976 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 977                                    uint8_t *buf)
 978 {
 979         int i, eccsize = chip->ecc.size;
 980         int eccbytes = chip->ecc.bytes;
 981         int eccsteps = chip->ecc.steps;
 982         uint8_t *p = buf;
 983         uint8_t *oob = chip->oob_poi;
 984
 985         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 986                 int stat;
 987
 988                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 989                 chip->read_buf(mtd, p, eccsize);
 990
 991                 if (chip->ecc.prepad) {
 992                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 993                         oob += chip->ecc.prepad;
 994                 }
 995
 996                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
 997                 chip->read_buf(mtd, oob, eccbytes);
 998                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 999
1000                 if (stat == -1)
1001                         mtd->ecc_stats.failed++;
1002                 else
1003                         mtd->ecc_stats.corrected += stat;
1004
1005                 oob += eccbytes;
1006
1007                 if (chip->ecc.postpad) {
1008                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1009                         oob += chip->ecc.postpad;
1010                 }
1011         }
1012
1013         /* Calculate remaining oob bytes */
1014         i = mtd->oobsize - (oob - chip->oob_poi);
1015         if (i)
1016                 chip->read_buf(mtd, oob, i);
1017
1018         return 0;
1019 }
1020
1021 /**
1022  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1023  * @chip:       nand chip structure
1024  * @oob:        oob destination address
1025  * @ops:        oob ops structure
1026  * @len:        size of oob to transfer
1027  */
1028 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1029                                   struct mtd_oob_ops *ops, size_t len)
1030 {
1031         switch(ops->mode) {
1032
1033         case MTD_OOB_PLACE:
1034         case MTD_OOB_RAW:
1035                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1036                 return oob + len;
1037
1038         case MTD_OOB_AUTO: {
1039                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1040                 uint32_t boffs = 0, roffs = ops->ooboffs;
1041                 size_t bytes = 0;
1042
1043                 for(; free->length && len; free++, len -= bytes) {
1044                         /* Read request not from offset 0 ? */
1045                         if (unlikely(roffs)) {
1046                                 if (roffs >= free->length) {
1047                                         roffs -= free->length;
1048                                         continue;
1049                                 }
1050                                 boffs = free->offset + roffs;
1051                                 bytes = min_t(size_t, len,
1052                                               (free->length - roffs));
1053                                 roffs = 0;
1054                         } else {
1055                                 bytes = min_t(size_t, len, free->length);
1056                                 boffs = free->offset;
1057                         }
1058                         memcpy(oob, chip->oob_poi + boffs, bytes);
1059                         oob += bytes;
1060                 }
1061                 return oob;
1062         }
1063         default:
1064                 BUG();
1065         }
1066         return NULL;
1067 }
1068
1069 /**
1070  * nand_do_read_ops - [Internal] Read data with ECC
1071  *
1072  * @mtd:        MTD device structure
1073  * @from:       offset to read from
1074  * @ops:        oob ops structure
1075  *
1076  * Internal function. Called with chip held.
1077  */
1078 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1079                             struct mtd_oob_ops *ops)
1080 {
1081         int chipnr, page, realpage, col, bytes, aligned;
1082         struct nand_chip *chip = mtd->priv;
1083         struct mtd_ecc_stats stats;
1084         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1085         int sndcmd = 1;
1086         int ret = 0;
1087         uint32_t readlen = ops->len;
1088         uint32_t oobreadlen = ops->ooblen;
1089         uint8_t *bufpoi, *oob, *buf;
1090
1091         stats = mtd->ecc_stats;
1092
1093         chipnr = (int)(from >> chip->chip_shift);
1094         chip->select_chip(mtd, chipnr);
1095
1096         realpage = (int)(from >> chip->page_shift);
1097         page = realpage & chip->pagemask;
1098
1099         col = (int)(from & (mtd->writesize - 1));
1100
1101         buf = ops->datbuf;
1102         oob = ops->oobbuf;
1103
1104         while(1) {
1105                 bytes = min(mtd->writesize - col, readlen);
1106                 aligned = (bytes == mtd->writesize);
1107
1108                 /* Is the current page in the buffer ? */
1109                 if (realpage != chip->pagebuf || oob) {
1110                         bufpoi = aligned ? buf : chip->buffers->databuf;
1111
1112                         if (likely(sndcmd)) {
1113                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1114                                 sndcmd = 0;
1115                         }
1116
1117                         /* Now read the page into the buffer */
1118                         if (unlikely(ops->mode == MTD_OOB_RAW))
1119                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi);
1120                         else
1121                                 ret = chip->ecc.read_page(mtd, chip, bufpoi);
1122                         if (ret < 0)
1123                                 break;
1124
1125                         /* Transfer not aligned data */
1126                         if (!aligned) {
1127                                 chip->pagebuf = realpage;
1128                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1129                         }
1130
1131                         buf += bytes;
1132
1133                         if (unlikely(oob)) {
1134                                 /* Raw mode does data:oob:data:oob */
1135                                 if (ops->mode != MTD_OOB_RAW) {
1136                                         int toread = min(oobreadlen,
1137                                                 chip->ecc.layout->oobavail);
1138                                         if (toread) {
1139                                                 oob = nand_transfer_oob(chip,
1140                                                         oob, ops, toread);
1141                                                 oobreadlen -= toread;
1142                                         }
1143                                 } else
1144                                         buf = nand_transfer_oob(chip,
1145                                                 buf, ops, mtd->oobsize);
1146                         }
1147
1148                         if (!(chip->options & NAND_NO_READRDY)) {
1149                                 /*
1150                                  * Apply delay or wait for ready/busy pin. Do
1151                                  * this before the AUTOINCR check, so no
1152                                  * problems arise if a chip which does auto
1153                                  * increment is marked as NOAUTOINCR by the
1154                                  * board driver.
1155                                  */
1156                                 if (!chip->dev_ready)
1157                                         udelay(chip->chip_delay);
1158                                 else
1159                                         nand_wait_ready(mtd);
1160                         }
1161                 } else {
1162                         memcpy(buf, chip->buffers->databuf + col, bytes);
1163                         buf += bytes;
1164                 }
1165
1166                 readlen -= bytes;
1167
1168                 if (!readlen)
1169                         break;
1170
1171                 /* For subsequent reads align to page boundary. */
1172                 col = 0;
1173                 /* Increment page address */
1174                 realpage++;
1175
1176                 page = realpage & chip->pagemask;
1177                 /* Check, if we cross a chip boundary */
1178                 if (!page) {
1179                         chipnr++;
1180                         chip->select_chip(mtd, -1);
1181                         chip->select_chip(mtd, chipnr);
1182                 }
1183
1184                 /* Check, if the chip supports auto page increment
1185                  * or if we have hit a block boundary.
1186                  */
1187                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1188                         sndcmd = 1;
1189         }
1190
1191         ops->retlen = ops->len - (size_t) readlen;
1192         if (oob)
1193                 ops->oobretlen = ops->ooblen - oobreadlen;
1194
1195         if (ret)
1196                 return ret;
1197
1198         if (mtd->ecc_stats.failed - stats.failed)
1199                 return -EBADMSG;
1200
1201         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1202 }
1203
1204 /**
1205  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1206  * @mtd:        MTD device structure
1207  * @from:       offset to read from
1208  * @len:        number of bytes to read
1209  * @retlen:     pointer to variable to store the number of read bytes
1210  * @buf:        the databuffer to put data
1211  *
1212  * Get hold of the chip and call nand_do_read
1213  */
1214 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1215                      size_t *retlen, uint8_t *buf)
1216 {
1217         struct nand_chip *chip = mtd->priv;
1218         int ret;
1219
1220         /* Do not allow reads past end of device */
1221         if ((from + len) > mtd->size)
1222                 return -EINVAL;
1223         if (!len)
1224                 return 0;
1225
1226         nand_get_device(chip, mtd, FL_READING);
1227
1228         chip->ops.len = len;
1229         chip->ops.datbuf = buf;
1230         chip->ops.oobbuf = NULL;
1231
1232         ret = nand_do_read_ops(mtd, from, &chip->ops);
1233
1234         *retlen = chip->ops.retlen;
1235
1236         nand_release_device(mtd);
1237
1238         return ret;
1239 }
1240
1241 /**
1242  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1243  * @mtd:        mtd info structure
1244  * @chip:       nand chip info structure
1245  * @page:       page number to read
1246  * @sndcmd:     flag whether to issue read command or not
1247  */
1248 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1249                              int page, int sndcmd)
1250 {
1251         if (sndcmd) {
1252                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1253                 sndcmd = 0;
1254         }
1255         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1256         return sndcmd;
1257 }
1258
1259 /**
1260  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1261  *                          with syndromes
1262  * @mtd:        mtd info structure
1263  * @chip:       nand chip info structure
1264  * @page:       page number to read
1265  * @sndcmd:     flag whether to issue read command or not
1266  */
1267 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1268                                   int page, int sndcmd)
1269 {
1270         uint8_t *buf = chip->oob_poi;
1271         int length = mtd->oobsize;
1272         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1273         int eccsize = chip->ecc.size;
1274         uint8_t *bufpoi = buf;
1275         int i, toread, sndrnd = 0, pos;
1276
1277         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1278         for (i = 0; i < chip->ecc.steps; i++) {
1279                 if (sndrnd) {
1280                         pos = eccsize + i * (eccsize + chunk);
1281                         if (mtd->writesize > 512)
1282                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1283                         else
1284                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1285                 } else
1286                         sndrnd = 1;
1287                 toread = min_t(int, length, chunk);
1288                 chip->read_buf(mtd, bufpoi, toread);
1289                 bufpoi += toread;
1290                 length -= toread;
1291         }
1292         if (length > 0)
1293                 chip->read_buf(mtd, bufpoi, length);
1294
1295         return 1;
1296 }
1297
1298 /**
1299  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1300  * @mtd:        mtd info structure
1301  * @chip:       nand chip info structure
1302  * @page:       page number to write
1303  */
1304 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1305                               int page)
1306 {
1307         int status = 0;
1308         const uint8_t *buf = chip->oob_poi;
1309         int length = mtd->oobsize;
1310
1311         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1312         chip->write_buf(mtd, buf, length);
1313         /* Send command to program the OOB data */
1314         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1315
1316         status = chip->waitfunc(mtd, chip);
1317
1318         return status & NAND_STATUS_FAIL ? -EIO : 0;
1319 }
1320
1321 /**
1322  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1323  *                           with syndrome - only for large page flash !
1324  * @mtd:        mtd info structure
1325  * @chip:       nand chip info structure
1326  * @page:       page number to write
1327  */
1328 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1329                                    struct nand_chip *chip, int page)
1330 {
1331         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1332         int eccsize = chip->ecc.size, length = mtd->oobsize;
1333         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1334         const uint8_t *bufpoi = chip->oob_poi;
1335
1336         /*
1337          * data-ecc-data-ecc ... ecc-oob
1338          * or
1339          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1340          */
1341         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1342                 pos = steps * (eccsize + chunk);
1343                 steps = 0;
1344         } else
1345                 pos = eccsize;
1346
1347         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1348         for (i = 0; i < steps; i++) {
1349                 if (sndcmd) {
1350                         if (mtd->writesize <= 512) {
1351                                 uint32_t fill = 0xFFFFFFFF;
1352
1353                                 len = eccsize;
1354                                 while (len > 0) {
1355                                         int num = min_t(int, len, 4);
1356                                         chip->write_buf(mtd, (uint8_t *)&fill,
1357                                                         num);
1358                                         len -= num;
1359                                 }
1360                         } else {
1361                                 pos = eccsize + i * (eccsize + chunk);
1362                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1363                         }
1364                 } else
1365                         sndcmd = 1;
1366                 len = min_t(int, length, chunk);
1367                 chip->write_buf(mtd, bufpoi, len);
1368                 bufpoi += len;
1369                 length -= len;
1370         }
1371         if (length > 0)
1372                 chip->write_buf(mtd, bufpoi, length);
1373
1374         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1375         status = chip->waitfunc(mtd, chip);
1376
1377         return status & NAND_STATUS_FAIL ? -EIO : 0;
1378 }
1379
1380 /**
1381  * nand_do_read_oob - [Intern] NAND read out-of-band
1382  * @mtd:        MTD device structure
1383  * @from:       offset to read from
1384  * @ops:        oob operations description structure
1385  *
1386  * NAND read out-of-band data from the spare area
1387  */
1388 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1389                             struct mtd_oob_ops *ops)
1390 {
1391         int page, realpage, chipnr, sndcmd = 1;
1392         struct nand_chip *chip = mtd->priv;
1393         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1394         int readlen = ops->ooblen;
1395         int len;
1396         uint8_t *buf = ops->oobbuf;
1397
1398         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_read_oob: from = 0x%08Lx, len = %i\n",
1399                   (unsigned long long)from, readlen);
1400
1401         if (ops->mode == MTD_OOB_AUTO)
1402                 len = chip->ecc.layout->oobavail;
1403         else
1404                 len = mtd->oobsize;
1405
1406         if (unlikely(ops->ooboffs >= len)) {
1407                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1408                           "Attempt to start read outside oob\n");
1409                 return -EINVAL;
1410         }
1411
1412         /* Do not allow reads past end of device */
1413         if (unlikely(from >= mtd->size ||
1414                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1415                                         (from >> chip->page_shift)) * len)) {
1416                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1417                           "Attempt read beyond end of device\n");
1418                 return -EINVAL;
1419         }
1420
1421         chipnr = (int)(from >> chip->chip_shift);
1422         chip->select_chip(mtd, chipnr);
1423
1424         /* Shift to get page */
1425         realpage = (int)(from >> chip->page_shift);
1426         page = realpage & chip->pagemask;
1427
1428         while(1) {
1429                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1430
1431                 len = min(len, readlen);
1432                 buf = nand_transfer_oob(chip, buf, ops, len);
1433
1434                 if (!(chip->options & NAND_NO_READRDY)) {
1435                         /*
1436                          * Apply delay or wait for ready/busy pin. Do this
1437                          * before the AUTOINCR check, so no problems arise if a
1438                          * chip which does auto increment is marked as
1439                          * NOAUTOINCR by the board driver.
1440                          */
1441                         if (!chip->dev_ready)
1442                                 udelay(chip->chip_delay);
1443                         else
1444                                 nand_wait_ready(mtd);
1445                 }
1446
1447                 readlen -= len;
1448                 if (!readlen)
1449                         break;
1450
1451                 /* Increment page address */
1452                 realpage++;
1453
1454                 page = realpage & chip->pagemask;
1455                 /* Check, if we cross a chip boundary */
1456                 if (!page) {
1457                         chipnr++;
1458                         chip->select_chip(mtd, -1);
1459                         chip->select_chip(mtd, chipnr);
1460                 }
1461
1462                 /* Check, if the chip supports auto page increment
1463                  * or if we have hit a block boundary.
1464                  */
1465                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1466                         sndcmd = 1;
1467         }
1468
1469         ops->oobretlen = ops->ooblen;
1470         return 0;
1471 }
1472
1473 /**
1474  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1475  * @mtd:        MTD device structure
1476  * @from:       offset to read from
1477  * @ops:        oob operation description structure
1478  *
1479  * NAND read data and/or out-of-band data
1480  */
1481 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1482                          struct mtd_oob_ops *ops)
1483 {
1484         struct nand_chip *chip = mtd->priv;
1485         int ret = -ENOTSUPP;
1486
1487         ops->retlen = 0;
1488
1489         /* Do not allow reads past end of device */
1490         if (ops->datbuf && (from + ops->len) > mtd->size) {
1491                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1492                           "Attempt read beyond end of device\n");
1493                 return -EINVAL;
1494         }
1495
1496         nand_get_device(chip, mtd, FL_READING);
1497
1498         switch(ops->mode) {
1499         case MTD_OOB_PLACE:
1500         case MTD_OOB_AUTO:
1501         case MTD_OOB_RAW:
1502                 break;
1503
1504         default:
1505                 goto out;
1506         }
1507
1508         if (!ops->datbuf)
1509                 ret = nand_do_read_oob(mtd, from, ops);
1510         else
1511                 ret = nand_do_read_ops(mtd, from, ops);
1512
1513  out:
1514         nand_release_device(mtd);
1515         return ret;
1516 }
1517
1518
1519 /**
1520  * nand_write_page_raw - [Intern] raw page write function
1521  * @mtd:        mtd info structure
1522  * @chip:       nand chip info structure
1523  * @buf:        data buffer
1524  */
1525 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1526                                 const uint8_t *buf)
1527 {
1528         chip->write_buf(mtd, buf, mtd->writesize);
1529         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1530 }
1531
1532 /**
1533  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1534  * @mtd:        mtd info structure
1535  * @chip:       nand chip info structure
1536  * @buf:        data buffer
1537  */
1538 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1539                                   const uint8_t *buf)
1540 {
1541         int i, eccsize = chip->ecc.size;
1542         int eccbytes = chip->ecc.bytes;
1543         int eccsteps = chip->ecc.steps;
1544         uint8_t *ecc_calc = chip->buffers->ecccalc;
1545         const uint8_t *p = buf;
1546         uint32_t *eccpos = chip->ecc.layout->eccpos;
1547
1548         /* Software ecc calculation */
1549         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1550                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1551
1552         for (i = 0; i < chip->ecc.total; i++)
1553                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1554
1555         chip->ecc.write_page_raw(mtd, chip, buf);
1556 }
1557
1558 /**
1559  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1560  * @mtd:        mtd info structure
1561  * @chip:       nand chip info structure
1562  * @buf:        data buffer
1563  */
1564 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1565                                   const uint8_t *buf)
1566 {
1567         int i, eccsize = chip->ecc.size;
1568         int eccbytes = chip->ecc.bytes;
1569         int eccsteps = chip->ecc.steps;
1570         uint8_t *ecc_calc = chip->buffers->ecccalc;
1571         const uint8_t *p = buf;
1572         uint32_t *eccpos = chip->ecc.layout->eccpos;
1573
1574         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1575                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1576                 chip->write_buf(mtd, p, eccsize);
1577                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1578         }
1579
1580         for (i = 0; i < chip->ecc.total; i++)
1581                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1582
1583         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1584 }
1585
1586 /**
1587  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1588  * @mtd:        mtd info structure
1589  * @chip:       nand chip info structure
1590  * @buf:        data buffer
1591  *
1592  * The hw generator calculates the error syndrome automatically. Therefor
1593  * we need a special oob layout and handling.
1594  */
1595 static void nand_write_page_syndrome(struct mtd_info *mtd,
1596                                     struct nand_chip *chip, const uint8_t *buf)
1597 {
1598         int i, eccsize = chip->ecc.size;
1599         int eccbytes = chip->ecc.bytes;
1600         int eccsteps = chip->ecc.steps;
1601         const uint8_t *p = buf;
1602         uint8_t *oob = chip->oob_poi;
1603
1604         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1605
1606                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1607                 chip->write_buf(mtd, p, eccsize);
1608
1609                 if (chip->ecc.prepad) {
1610                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1611                         oob += chip->ecc.prepad;
1612                 }
1613
1614                 chip->ecc.calculate(mtd, p, oob);
1615                 chip->write_buf(mtd, oob, eccbytes);
1616                 oob += eccbytes;
1617
1618                 if (chip->ecc.postpad) {
1619                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1620                         oob += chip->ecc.postpad;
1621                 }
1622         }
1623
1624         /* Calculate remaining oob bytes */
1625         i = mtd->oobsize - (oob - chip->oob_poi);
1626         if (i)
1627                 chip->write_buf(mtd, oob, i);
1628 }
1629
1630 /**
1631  * nand_write_page - [REPLACEABLE] write one page
1632  * @mtd:        MTD device structure
1633  * @chip:       NAND chip descriptor
1634  * @buf:        the data to write
1635  * @page:       page number to write
1636  * @cached:     cached programming
1637  * @raw:        use _raw version of write_page
1638  */
1639 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1640                            const uint8_t *buf, int page, int cached, int raw)
1641 {
1642         int status;
1643
1644         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1645
1646         if (unlikely(raw))
1647                 chip->ecc.write_page_raw(mtd, chip, buf);
1648         else
1649                 chip->ecc.write_page(mtd, chip, buf);
1650
1651         /*
1652          * Cached progamming disabled for now, Not sure if its worth the
1653          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1654          */
1655         cached = 0;
1656
1657         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1658
1659                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1660                 status = chip->waitfunc(mtd, chip);
1661                 /*
1662                  * See if operation failed and additional status checks are
1663                  * available
1664                  */
1665                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1666                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1667                                                page);
1668
1669                 if (status & NAND_STATUS_FAIL)
1670                         return -EIO;
1671         } else {
1672                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1673                 status = chip->waitfunc(mtd, chip);
1674         }
1675
1676 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1677         /* Send command to read back the data */
1678         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1679
1680         if (chip->verify_buf(mtd, buf, mtd->writesize))
1681                 return -EIO;
1682 #endif
1683         return 0;
1684 }
1685
1686 /**
1687  * nand_fill_oob - [Internal] Transfer client buffer to oob
1688  * @chip:       nand chip structure
1689  * @oob:        oob data buffer
1690  * @ops:        oob ops structure
1691  */
1692 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1693                                   struct mtd_oob_ops *ops)
1694 {
1695         size_t len = ops->ooblen;
1696
1697         switch(ops->mode) {
1698
1699         case MTD_OOB_PLACE:
1700         case MTD_OOB_RAW:
1701                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1702                 return oob + len;
1703
1704         case MTD_OOB_AUTO: {
1705                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1706                 uint32_t boffs = 0, woffs = ops->ooboffs;
1707                 size_t bytes = 0;
1708
1709                 for(; free->length && len; free++, len -= bytes) {
1710                         /* Write request not from offset 0 ? */
1711                         if (unlikely(woffs)) {
1712                                 if (woffs >= free->length) {
1713                                         woffs -= free->length;
1714                                         continue;
1715                                 }
1716                                 boffs = free->offset + woffs;
1717                                 bytes = min_t(size_t, len,
1718                                               (free->length - woffs));
1719                                 woffs = 0;
1720                         } else {
1721                                 bytes = min_t(size_t, len, free->length);
1722                                 boffs = free->offset;
1723                         }
1724                         memcpy(chip->oob_poi + boffs, oob, bytes);
1725                         oob += bytes;
1726                 }
1727                 return oob;
1728         }
1729         default:
1730                 BUG();
1731         }
1732         return NULL;
1733 }
1734
1735 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1736
1737 /**
1738  * nand_do_write_ops - [Internal] NAND write with ECC
1739  * @mtd:        MTD device structure
1740  * @to:         offset to write to
1741  * @ops:        oob operations description structure
1742  *
1743  * NAND write with ECC
1744  */
1745 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1746                              struct mtd_oob_ops *ops)
1747 {
1748         int chipnr, realpage, page, blockmask, column;
1749         struct nand_chip *chip = mtd->priv;
1750         uint32_t writelen = ops->len;
1751         uint8_t *oob = ops->oobbuf;
1752         uint8_t *buf = ops->datbuf;
1753         int ret, subpage;
1754
1755         ops->retlen = 0;
1756         if (!writelen)
1757                 return 0;
1758
1759         /* reject writes, which are not page aligned */
1760         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1761                 printk(KERN_NOTICE "nand_write: "
1762                        "Attempt to write not page aligned data\n");
1763                 return -EINVAL;
1764         }
1765
1766         column = to & (mtd->writesize - 1);
1767         subpage = column || (writelen & (mtd->writesize - 1));
1768
1769         if (subpage && oob)
1770                 return -EINVAL;
1771
1772         chipnr = (int)(to >> chip->chip_shift);
1773         chip->select_chip(mtd, chipnr);
1774
1775         /* Check, if it is write protected */
1776         if (nand_check_wp(mtd)) {
1777                 printk (KERN_NOTICE "nand_do_write_ops: Device is write protected\n");
1778                 return -EIO;
1779         }
1780
1781         realpage = (int)(to >> chip->page_shift);
1782         page = realpage & chip->pagemask;
1783         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1784
1785         /* Invalidate the page cache, when we write to the cached page */
1786         if (to <= (chip->pagebuf << chip->page_shift) &&
1787             (chip->pagebuf << chip->page_shift) < (to + ops->len))
1788                 chip->pagebuf = -1;
1789
1790         /* If we're not given explicit OOB data, let it be 0xFF */
1791         if (likely(!oob))
1792                 memset(chip->oob_poi, 0xff, mtd->oobsize);
1793
1794         while(1) {
1795                 int bytes = mtd->writesize;
1796                 int cached = writelen > bytes && page != blockmask;
1797                 uint8_t *wbuf = buf;
1798
1799                 /* Partial page write ? */
1800                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
1801                         cached = 0;
1802                         bytes = min_t(int, bytes - column, (int) writelen);
1803                         chip->pagebuf = -1;
1804                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
1805                         memcpy(&chip->buffers->databuf[column], buf, bytes);
1806                         wbuf = chip->buffers->databuf;
1807                 }
1808
1809                 if (unlikely(oob))
1810                         oob = nand_fill_oob(chip, oob, ops);
1811
1812                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
1813                                        (ops->mode == MTD_OOB_RAW));
1814                 if (ret)
1815                         break;
1816
1817                 writelen -= bytes;
1818                 if (!writelen)
1819                         break;
1820
1821                 column = 0;
1822                 buf += bytes;
1823                 realpage++;
1824
1825                 page = realpage & chip->pagemask;
1826                 /* Check, if we cross a chip boundary */
1827                 if (!page) {
1828                         chipnr++;
1829                         chip->select_chip(mtd, -1);
1830                         chip->select_chip(mtd, chipnr);
1831                 }
1832         }
1833
1834         ops->retlen = ops->len - writelen;
1835         if (unlikely(oob))
1836                 ops->oobretlen = ops->ooblen;
1837         return ret;
1838 }
1839
1840 /**
1841  * nand_write - [MTD Interface] NAND write with ECC
1842  * @mtd:        MTD device structure
1843  * @to:         offset to write to
1844  * @len:        number of bytes to write
1845  * @retlen:     pointer to variable to store the number of written bytes
1846  * @buf:        the data to write
1847  *
1848  * NAND write with ECC
1849  */
1850 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
1851                           size_t *retlen, const uint8_t *buf)
1852 {
1853         struct nand_chip *chip = mtd->priv;
1854         int ret;
1855
1856         /* Do not allow reads past end of device */
1857         if ((to + len) > mtd->size)
1858                 return -EINVAL;
1859         if (!len)
1860                 return 0;
1861
1862         nand_get_device(chip, mtd, FL_WRITING);
1863
1864         chip->ops.len = len;
1865         chip->ops.datbuf = (uint8_t *)buf;
1866         chip->ops.oobbuf = NULL;
1867
1868         ret = nand_do_write_ops(mtd, to, &chip->ops);
1869
1870         *retlen = chip->ops.retlen;
1871
1872         nand_release_device(mtd);
1873
1874         return ret;
1875 }
1876
1877 /**
1878  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
1879  * @mtd:        MTD device structure
1880  * @to:         offset to write to
1881  * @ops:        oob operation description structure
1882  *
1883  * NAND write out-of-band
1884  */
1885 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
1886                              struct mtd_oob_ops *ops)
1887 {
1888         int chipnr, page, status, len;
1889         struct nand_chip *chip = mtd->priv;
1890
1891         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_write_oob: to = 0x%08x, len = %i\n",
1892                   (unsigned int)to, (int)ops->ooblen);
1893
1894         if (ops->mode == MTD_OOB_AUTO)
1895                 len = chip->ecc.layout->oobavail;
1896         else
1897                 len = mtd->oobsize;
1898
1899         /* Do not allow write past end of page */
1900         if ((ops->ooboffs + ops->ooblen) > len) {
1901                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_write_oob: "
1902                           "Attempt to write past end of page\n");
1903                 return -EINVAL;
1904         }
1905
1906         if (unlikely(ops->ooboffs >= len)) {
1907                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1908                           "Attempt to start write outside oob\n");
1909                 return -EINVAL;
1910         }
1911
1912         /* Do not allow reads past end of device */
1913         if (unlikely(to >= mtd->size ||
1914                      ops->ooboffs + ops->ooblen >
1915                         ((mtd->size >> chip->page_shift) -
1916                          (to >> chip->page_shift)) * len)) {
1917                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1918                           "Attempt write beyond end of device\n");
1919                 return -EINVAL;
1920         }
1921
1922         chipnr = (int)(to >> chip->chip_shift);
1923         chip->select_chip(mtd, chipnr);
1924
1925         /* Shift to get page */
1926         page = (int)(to >> chip->page_shift);
1927
1928         /*
1929          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
1930          * of my DiskOnChip 2000 test units) will clear the whole data page too
1931          * if we don't do this. I have no clue why, but I seem to have 'fixed'
1932          * it in the doc2000 driver in August 1999.  dwmw2.
1933          */
1934         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1935
1936         /* Check, if it is write protected */
1937         if (nand_check_wp(mtd))
1938                 return -EROFS;
1939
1940         /* Invalidate the page cache, if we write to the cached page */
1941         if (page == chip->pagebuf)
1942                 chip->pagebuf = -1;
1943
1944         memset(chip->oob_poi, 0xff, mtd->oobsize);
1945         nand_fill_oob(chip, ops->oobbuf, ops);
1946         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
1947         memset(chip->oob_poi, 0xff, mtd->oobsize);
1948
1949         if (status)
1950                 return status;
1951
1952         ops->oobretlen = ops->ooblen;
1953
1954         return 0;
1955 }
1956
1957 /**
1958  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
1959  * @mtd:        MTD device structure
1960  * @to:         offset to write to
1961  * @ops:        oob operation description structure
1962  */
1963 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
1964                           struct mtd_oob_ops *ops)
1965 {
1966         struct nand_chip *chip = mtd->priv;
1967         int ret = -ENOTSUPP;
1968
1969         ops->retlen = 0;
1970
1971         /* Do not allow writes past end of device */
1972         if (ops->datbuf && (to + ops->len) > mtd->size) {
1973                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_read_oob: "
1974                           "Attempt read beyond end of device\n");
1975                 return -EINVAL;
1976         }
1977
1978         nand_get_device(chip, mtd, FL_WRITING);
1979
1980         switch(ops->mode) {
1981         case MTD_OOB_PLACE:
1982         case MTD_OOB_AUTO:
1983         case MTD_OOB_RAW:
1984                 break;
1985
1986         default:
1987                 goto out;
1988         }
1989
1990         if (!ops->datbuf)
1991                 ret = nand_do_write_oob(mtd, to, ops);
1992         else
1993                 ret = nand_do_write_ops(mtd, to, ops);
1994
1995  out:
1996         nand_release_device(mtd);
1997         return ret;
1998 }
1999
2000 /**
2001  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2002  * @mtd:        MTD device structure
2003  * @page:       the page address of the block which will be erased
2004  *
2005  * Standard erase command for NAND chips
2006  */
2007 static void single_erase_cmd(struct mtd_info *mtd, int page)
2008 {
2009         struct nand_chip *chip = mtd->priv;
2010         /* Send commands to erase a block */
2011         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2012         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2013 }
2014
2015 /**
2016  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2017  * @mtd:        MTD device structure
2018  * @page:       the page address of the block which will be erased
2019  *
2020  * AND multi block erase command function
2021  * Erase 4 consecutive blocks
2022  */
2023 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2024 {
2025         struct nand_chip *chip = mtd->priv;
2026         /* Send commands to erase a block */
2027         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2028         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2029         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2030         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2031         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2032 }
2033
2034 /**
2035  * nand_erase - [MTD Interface] erase block(s)
2036  * @mtd:        MTD device structure
2037  * @instr:      erase instruction
2038  *
2039  * Erase one ore more blocks
2040  */
2041 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2042 {
2043         return nand_erase_nand(mtd, instr, 0);
2044 }
2045
2046 #define BBT_PAGE_MASK   0xffffff3f
2047 /**
2048  * nand_erase_nand - [Internal] erase block(s)
2049  * @mtd:        MTD device structure
2050  * @instr:      erase instruction
2051  * @allowbbt:   allow erasing the bbt area
2052  *
2053  * Erase one ore more blocks
2054  */
2055 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2056                     int allowbbt)
2057 {
2058         int page, len, status, pages_per_block, ret, chipnr;
2059         struct nand_chip *chip = mtd->priv;
2060         int rewrite_bbt[NAND_MAX_CHIPS]={0};
2061         unsigned int bbt_masked_page = 0xffffffff;
2062
2063         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_erase: start = 0x%08x, len = %i\n",
2064                   (unsigned int) instr->addr, (unsigned int) instr->len);
2065
2066         /* Start address must align on block boundary */
2067         if (instr->addr & ((1 << chip->phys_erase_shift) - 1)) {
2068                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: Unaligned address\n");
2069                 return -EINVAL;
2070         }
2071
2072         /* Length must align on block boundary */
2073         if (instr->len & ((1 << chip->phys_erase_shift) - 1)) {
2074                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2075                           "nand_erase: Length not block aligned\n");
2076                 return -EINVAL;
2077         }
2078
2079         /* Do not allow erase past end of device */
2080         if ((instr->len + instr->addr) > mtd->size) {
2081                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2082                           "nand_erase: Erase past end of device\n");
2083                 return -EINVAL;
2084         }
2085
2086         instr->fail_addr = 0xffffffff;
2087
2088         /* Grab the lock and see if the device is available */
2089         nand_get_device(chip, mtd, FL_ERASING);
2090
2091         /* Shift to get first page */
2092         page = (int)(instr->addr >> chip->page_shift);
2093         chipnr = (int)(instr->addr >> chip->chip_shift);
2094
2095         /* Calculate pages in each block */
2096         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2097
2098         /* Select the NAND device */
2099         chip->select_chip(mtd, chipnr);
2100
2101         /* Check, if it is write protected */
2102         if (nand_check_wp(mtd)) {
2103                 MTDDEBUG (MTD_DEBUG_LEVEL0,
2104                           "nand_erase: Device is write protected!!!\n");
2105                 instr->state = MTD_ERASE_FAILED;
2106                 goto erase_exit;
2107         }
2108
2109         /*
2110          * If BBT requires refresh, set the BBT page mask to see if the BBT
2111          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2112          * can not be matched. This is also done when the bbt is actually
2113          * erased to avoid recusrsive updates
2114          */
2115         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2116                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2117
2118         /* Loop through the pages */
2119         len = instr->len;
2120
2121         instr->state = MTD_ERASING;
2122
2123         while (len) {
2124                 /*
2125                  * heck if we have a bad block, we do not erase bad blocks !
2126                  */
2127                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2128                                         chip->page_shift, 0, allowbbt)) {
2129                         printk(KERN_WARNING "nand_erase: attempt to erase a "
2130                                "bad block at page 0x%08x\n", page);
2131                         instr->state = MTD_ERASE_FAILED;
2132                         goto erase_exit;
2133                 }
2134
2135                 /*
2136                  * Invalidate the page cache, if we erase the block which
2137                  * contains the current cached page
2138                  */
2139                 if (page <= chip->pagebuf && chip->pagebuf <
2140                     (page + pages_per_block))
2141                         chip->pagebuf = -1;
2142
2143                 chip->erase_cmd(mtd, page & chip->pagemask);
2144
2145                 status = chip->waitfunc(mtd, chip);
2146
2147                 /*
2148                  * See if operation failed and additional status checks are
2149                  * available
2150                  */
2151                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2152                         status = chip->errstat(mtd, chip, FL_ERASING,
2153                                                status, page);
2154
2155                 /* See if block erase succeeded */
2156                 if (status & NAND_STATUS_FAIL) {
2157                         MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase: "
2158                                   "Failed erase, page 0x%08x\n", page);
2159                         instr->state = MTD_ERASE_FAILED;
2160                         instr->fail_addr = (page << chip->page_shift);
2161                         goto erase_exit;
2162                 }
2163
2164                 /*
2165                  * If BBT requires refresh, set the BBT rewrite flag to the
2166                  * page being erased
2167                  */
2168                 if (bbt_masked_page != 0xffffffff &&
2169                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2170                             rewrite_bbt[chipnr] = (page << chip->page_shift);
2171
2172                 /* Increment page address and decrement length */
2173                 len -= (1 << chip->phys_erase_shift);
2174                 page += pages_per_block;
2175
2176                 /* Check, if we cross a chip boundary */
2177                 if (len && !(page & chip->pagemask)) {
2178                         chipnr++;
2179                         chip->select_chip(mtd, -1);
2180                         chip->select_chip(mtd, chipnr);
2181
2182                         /*
2183                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2184                          * page mask to see if this BBT should be rewritten
2185                          */
2186                         if (bbt_masked_page != 0xffffffff &&
2187                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2188                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2189                                         BBT_PAGE_MASK;
2190                 }
2191         }
2192         instr->state = MTD_ERASE_DONE;
2193
2194  erase_exit:
2195
2196         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2197         /* Do call back function */
2198         if (!ret)
2199                 mtd_erase_callback(instr);
2200
2201         /* Deselect and wake up anyone waiting on the device */
2202         nand_release_device(mtd);
2203
2204         /*
2205          * If BBT requires refresh and erase was successful, rewrite any
2206          * selected bad block tables
2207          */
2208         if (bbt_masked_page == 0xffffffff || ret)
2209                 return ret;
2210
2211         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2212                 if (!rewrite_bbt[chipnr])
2213                         continue;
2214                 /* update the BBT for chip */
2215                 MTDDEBUG (MTD_DEBUG_LEVEL0, "nand_erase_nand: nand_update_bbt "
2216                           "(%d:0x%0x 0x%0x)\n", chipnr, rewrite_bbt[chipnr],
2217                           chip->bbt_td->pages[chipnr]);
2218                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2219         }
2220
2221         /* Return more or less happy */
2222         return ret;
2223 }
2224
2225 /**
2226  * nand_sync - [MTD Interface] sync
2227  * @mtd:        MTD device structure
2228  *
2229  * Sync is actually a wait for chip ready function
2230  */
2231 static void nand_sync(struct mtd_info *mtd)
2232 {
2233         struct nand_chip *chip = mtd->priv;
2234
2235         MTDDEBUG (MTD_DEBUG_LEVEL3, "nand_sync: called\n");
2236
2237         /* Grab the lock and see if the device is available */
2238         nand_get_device(chip, mtd, FL_SYNCING);
2239         /* Release it and go back */
2240         nand_release_device(mtd);
2241 }
2242
2243 /**
2244  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2245  * @mtd:        MTD device structure
2246  * @offs:       offset relative to mtd start
2247  */
2248 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2249 {
2250         /* Check for invalid offset */
2251         if (offs > mtd->size)
2252                 return -EINVAL;
2253
2254         return nand_block_checkbad(mtd, offs, 1, 0);
2255 }
2256
2257 /**
2258  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2259  * @mtd:        MTD device structure
2260  * @ofs:        offset relative to mtd start
2261  */
2262 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2263 {
2264         struct nand_chip *chip = mtd->priv;
2265         int ret;
2266
2267         if ((ret = nand_block_isbad(mtd, ofs))) {
2268                 /* If it was bad already, return success and do nothing. */
2269                 if (ret > 0)
2270                         return 0;
2271                 return ret;
2272         }
2273
2274         return chip->block_markbad(mtd, ofs);
2275 }
2276
2277 /**
2278  * nand_suspend - [MTD Interface] Suspend the NAND flash
2279  * @mtd:        MTD device structure
2280  */
2281 static int nand_suspend(struct mtd_info *mtd)
2282 {
2283         struct nand_chip *chip = mtd->priv;
2284
2285         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2286 }
2287
2288 /**
2289  * nand_resume - [MTD Interface] Resume the NAND flash
2290  * @mtd:        MTD device structure
2291  */
2292 static void nand_resume(struct mtd_info *mtd)
2293 {
2294         struct nand_chip *chip = mtd->priv;
2295
2296         if (chip->state == FL_PM_SUSPENDED)
2297                 nand_release_device(mtd);
2298         else
2299                 printk(KERN_ERR "nand_resume() called for a chip which is not "
2300                        "in suspended state\n");
2301 }
2302
2303 /*
2304  * Set default functions
2305  */
2306 static void nand_set_defaults(struct nand_chip *chip, int busw)
2307 {
2308         /* check for proper chip_delay setup, set 20us if not */
2309         if (!chip->chip_delay)
2310                 chip->chip_delay = 20;
2311
2312         /* check, if a user supplied command function given */
2313         if (chip->cmdfunc == NULL)
2314                 chip->cmdfunc = nand_command;
2315
2316         /* check, if a user supplied wait function given */
2317         if (chip->waitfunc == NULL)
2318                 chip->waitfunc = nand_wait;
2319
2320         if (!chip->select_chip)
2321                 chip->select_chip = nand_select_chip;
2322         if (!chip->read_byte)
2323                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2324         if (!chip->read_word)
2325                 chip->read_word = nand_read_word;
2326         if (!chip->block_bad)
2327                 chip->block_bad = nand_block_bad;
2328         if (!chip->block_markbad)
2329                 chip->block_markbad = nand_default_block_markbad;
2330         if (!chip->write_buf)
2331                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2332         if (!chip->read_buf)
2333                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2334         if (!chip->verify_buf)
2335                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2336         if (!chip->scan_bbt)
2337                 chip->scan_bbt = nand_default_bbt;
2338
2339         if (!chip->controller) {
2340                 chip->controller = &chip->hwcontrol;
2341
2342                 /* XXX U-BOOT XXX */
2343 #if 0
2344                 spin_lock_init(&chip->controller->lock);
2345                 init_waitqueue_head(&chip->controller->wq);
2346 #endif
2347         }
2348
2349 }
2350
2351 /*
2352  * Get the flash and manufacturer id and lookup if the type is supported
2353  */
2354 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2355                                                   struct nand_chip *chip,
2356                                                   int busw, int *maf_id)
2357 {
2358         struct nand_flash_dev *type = NULL;
2359         int i, dev_id, maf_idx;
2360
2361         /* Select the device */
2362         chip->select_chip(mtd, 0);
2363
2364         /* Send the command for reading device ID */
2365         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2366
2367         /* Read manufacturer and device IDs */
2368         *maf_id = chip->read_byte(mtd);
2369         dev_id = chip->read_byte(mtd);
2370
2371         /* Lookup the flash id */
2372         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2373                 if (dev_id == nand_flash_ids[i].id) {
2374                         type =  &nand_flash_ids[i];
2375                         break;
2376                 }
2377         }
2378
2379         if (!type)
2380                 return ERR_PTR(-ENODEV);
2381
2382         if (!mtd->name)
2383                 mtd->name = type->name;
2384
2385         chip->chipsize = type->chipsize << 20;
2386
2387         /* Newer devices have all the information in additional id bytes */
2388         if (!type->pagesize) {
2389                 int extid;
2390                 /* The 3rd id byte holds MLC / multichip data */
2391                 chip->cellinfo = chip->read_byte(mtd);
2392                 /* The 4th id byte is the important one */
2393                 extid = chip->read_byte(mtd);
2394                 /* Calc pagesize */
2395                 mtd->writesize = 1024 << (extid & 0x3);
2396                 extid >>= 2;
2397                 /* Calc oobsize */
2398                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2399                 extid >>= 2;
2400                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2401                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2402                 extid >>= 2;
2403                 /* Get buswidth information */
2404                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2405
2406         } else {
2407                 /*
2408                  * Old devices have chip data hardcoded in the device id table
2409                  */
2410                 mtd->erasesize = type->erasesize;
2411                 mtd->writesize = type->pagesize;
2412                 mtd->oobsize = mtd->writesize / 32;
2413                 busw = type->options & NAND_BUSWIDTH_16;
2414         }
2415
2416         /* Try to identify manufacturer */
2417         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2418                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2419                         break;
2420         }
2421
2422         /*
2423          * Check, if buswidth is correct. Hardware drivers should set
2424          * chip correct !
2425          */
2426         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2427                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2428                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2429                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2430                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2431                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2432                        busw ? 16 : 8);
2433                 return ERR_PTR(-EINVAL);
2434         }
2435
2436         /* Calculate the address shift from the page size */
2437         chip->page_shift = ffs(mtd->writesize) - 1;
2438         /* Convert chipsize to number of pages per chip -1. */
2439         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2440
2441         chip->bbt_erase_shift = chip->phys_erase_shift =
2442                 ffs(mtd->erasesize) - 1;
2443         chip->chip_shift = ffs(chip->chipsize) - 1;
2444
2445         /* Set the bad block position */
2446         chip->badblockpos = mtd->writesize > 512 ?
2447                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2448
2449         /* Get chip options, preserve non chip based options */
2450         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2451         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2452
2453         /*
2454          * Set chip as a default. Board drivers can override it, if necessary
2455          */
2456         chip->options |= NAND_NO_AUTOINCR;
2457
2458         /* Check if chip is a not a samsung device. Do not clear the
2459          * options for chips which are not having an extended id.
2460          */
2461         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2462                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2463
2464         /* Check for AND chips with 4 page planes */
2465         if (chip->options & NAND_4PAGE_ARRAY)
2466                 chip->erase_cmd = multi_erase_cmd;
2467         else
2468                 chip->erase_cmd = single_erase_cmd;
2469
2470         /* Do not replace user supplied command function ! */
2471         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2472                 chip->cmdfunc = nand_command_lp;
2473
2474         MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
2475                   " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2476                   nand_manuf_ids[maf_idx].name, type->name);
2477
2478         return type;
2479 }
2480
2481 /**
2482  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2483  * @mtd:             MTD device structure
2484  * @maxchips:        Number of chips to scan for
2485  *
2486  * This is the first phase of the normal nand_scan() function. It
2487  * reads the flash ID and sets up MTD fields accordingly.
2488  *
2489  * The mtd->owner field must be set to the module of the caller.
2490  */
2491 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2492 {
2493         int i, busw, nand_maf_id;
2494         struct nand_chip *chip = mtd->priv;
2495         struct nand_flash_dev *type;
2496
2497         /* Get buswidth to select the correct functions */
2498         busw = chip->options & NAND_BUSWIDTH_16;
2499         /* Set the default functions */
2500         nand_set_defaults(chip, busw);
2501
2502         /* Read the flash type */
2503         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2504
2505         if (IS_ERR(type)) {
2506                 printk(KERN_WARNING "No NAND device found!!!\n");
2507                 chip->select_chip(mtd, -1);
2508                 return PTR_ERR(type);
2509         }
2510
2511         /* Check for a chip array */
2512         for (i = 1; i < maxchips; i++) {
2513                 chip->select_chip(mtd, i);
2514                 /* Send the command for reading device ID */
2515                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2516                 /* Read manufacturer and device IDs */
2517                 if (nand_maf_id != chip->read_byte(mtd) ||
2518                     type->id != chip->read_byte(mtd))
2519                         break;
2520         }
2521         if (i > 1)
2522                 printk(KERN_INFO "%d NAND chips detected\n", i);
2523
2524         /* Store the number of chips and calc total size for mtd */
2525         chip->numchips = i;
2526         mtd->size = i * chip->chipsize;
2527
2528         return 0;
2529 }
2530
2531
2532 /**
2533  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2534  * @mtd:            MTD device structure
2535  * @maxchips:       Number of chips to scan for
2536  *
2537  * This is the second phase of the normal nand_scan() function. It
2538  * fills out all the uninitialized function pointers with the defaults
2539  * and scans for a bad block table if appropriate.
2540  */
2541 int nand_scan_tail(struct mtd_info *mtd)
2542 {
2543         int i;
2544         struct nand_chip *chip = mtd->priv;
2545
2546         if (!(chip->options & NAND_OWN_BUFFERS))
2547                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2548         if (!chip->buffers)
2549                 return -ENOMEM;
2550
2551         /* Set the internal oob buffer location, just after the page data */
2552         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2553
2554         /*
2555          * If no default placement scheme is given, select an appropriate one
2556          */
2557         if (!chip->ecc.layout) {
2558                 switch (mtd->oobsize) {
2559                 case 8:
2560                         chip->ecc.layout = &nand_oob_8;
2561                         break;
2562                 case 16:
2563                         chip->ecc.layout = &nand_oob_16;
2564                         break;
2565                 case 64:
2566                         chip->ecc.layout = &nand_oob_64;
2567                         break;
2568                 case 128:
2569                         chip->ecc.layout = &nand_oob_128;
2570                         break;
2571                 default:
2572                         printk(KERN_WARNING "No oob scheme defined for "
2573                                "oobsize %d\n", mtd->oobsize);
2574 /*                      BUG(); */
2575                 }
2576         }
2577
2578         if (!chip->write_page)
2579                 chip->write_page = nand_write_page;
2580
2581         /*
2582          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2583          * selected and we have 256 byte pagesize fallback to software ECC
2584          */
2585         if (!chip->ecc.read_page_raw)
2586                 chip->ecc.read_page_raw = nand_read_page_raw;
2587         if (!chip->ecc.write_page_raw)
2588                 chip->ecc.write_page_raw = nand_write_page_raw;
2589
2590         switch (chip->ecc.mode) {
2591         case NAND_ECC_HW:
2592                 /* Use standard hwecc read page function ? */
2593                 if (!chip->ecc.read_page)
2594                         chip->ecc.read_page = nand_read_page_hwecc;
2595                 if (!chip->ecc.write_page)
2596                         chip->ecc.write_page = nand_write_page_hwecc;
2597                 if (!chip->ecc.read_oob)
2598                         chip->ecc.read_oob = nand_read_oob_std;
2599                 if (!chip->ecc.write_oob)
2600                         chip->ecc.write_oob = nand_write_oob_std;
2601
2602         case NAND_ECC_HW_SYNDROME:
2603                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2604                      !chip->ecc.hwctl) &&
2605                     (!chip->ecc.read_page ||
2606                      chip->ecc.read_page == nand_read_page_hwecc ||
2607                      !chip->ecc.write_page ||
2608                      chip->ecc.write_page == nand_write_page_hwecc)) {
2609                         printk(KERN_WARNING "No ECC functions supplied, "
2610                                "Hardware ECC not possible\n");
2611                         BUG();
2612                 }
2613                 /* Use standard syndrome read/write page function ? */
2614                 if (!chip->ecc.read_page)
2615                         chip->ecc.read_page = nand_read_page_syndrome;
2616                 if (!chip->ecc.write_page)
2617                         chip->ecc.write_page = nand_write_page_syndrome;
2618                 if (!chip->ecc.read_oob)
2619                         chip->ecc.read_oob = nand_read_oob_syndrome;
2620                 if (!chip->ecc.write_oob)
2621                         chip->ecc.write_oob = nand_write_oob_syndrome;
2622
2623                 if (mtd->writesize >= chip->ecc.size)
2624                         break;
2625                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2626                        "%d byte page size, fallback to SW ECC\n",
2627                        chip->ecc.size, mtd->writesize);
2628                 chip->ecc.mode = NAND_ECC_SOFT;
2629
2630         case NAND_ECC_SOFT:
2631                 chip->ecc.calculate = nand_calculate_ecc;
2632                 chip->ecc.correct = nand_correct_data;
2633                 chip->ecc.read_page = nand_read_page_swecc;
2634                 chip->ecc.write_page = nand_write_page_swecc;
2635                 chip->ecc.read_oob = nand_read_oob_std;
2636                 chip->ecc.write_oob = nand_write_oob_std;
2637                 chip->ecc.size = 256;
2638                 chip->ecc.bytes = 3;
2639                 break;
2640
2641         case NAND_ECC_NONE:
2642                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2643                        "This is not recommended !!\n");
2644                 chip->ecc.read_page = nand_read_page_raw;
2645                 chip->ecc.write_page = nand_write_page_raw;
2646                 chip->ecc.read_oob = nand_read_oob_std;
2647                 chip->ecc.write_oob = nand_write_oob_std;
2648                 chip->ecc.size = mtd->writesize;
2649                 chip->ecc.bytes = 0;
2650                 break;
2651
2652         default:
2653                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2654                        chip->ecc.mode);
2655                 BUG();
2656         }
2657
2658         /*
2659          * The number of bytes available for a client to place data into
2660          * the out of band area
2661          */
2662         chip->ecc.layout->oobavail = 0;
2663         for (i = 0; chip->ecc.layout->oobfree[i].length; i++)
2664                 chip->ecc.layout->oobavail +=
2665                         chip->ecc.layout->oobfree[i].length;
2666         mtd->oobavail = chip->ecc.layout->oobavail;
2667
2668         /*
2669          * Set the number of read / write steps for one page depending on ECC
2670          * mode
2671          */
2672         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2673         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2674                 printk(KERN_WARNING "Invalid ecc parameters\n");
2675                 BUG();
2676         }
2677         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2678
2679         /*
2680          * Allow subpage writes up to ecc.steps. Not possible for MLC
2681          * FLASH.
2682          */
2683         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2684             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2685                 switch(chip->ecc.steps) {
2686                 case 2:
2687                         mtd->subpage_sft = 1;
2688                         break;
2689                 case 4:
2690                 case 8:
2691                         mtd->subpage_sft = 2;
2692                         break;
2693                 }
2694         }
2695         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2696
2697         /* Initialize state */
2698         chip->state = FL_READY;
2699
2700         /* De-select the device */
2701         chip->select_chip(mtd, -1);
2702
2703         /* Invalidate the pagebuffer reference */
2704         chip->pagebuf = -1;
2705
2706         /* Fill in remaining MTD driver data */
2707         mtd->type = MTD_NANDFLASH;
2708         mtd->flags = MTD_CAP_NANDFLASH;
2709         mtd->erase = nand_erase;
2710         mtd->point = NULL;
2711         mtd->unpoint = NULL;
2712         mtd->read = nand_read;
2713         mtd->write = nand_write;
2714         mtd->read_oob = nand_read_oob;
2715         mtd->write_oob = nand_write_oob;
2716         mtd->sync = nand_sync;
2717         mtd->lock = NULL;
2718         mtd->unlock = NULL;
2719         mtd->suspend = nand_suspend;
2720         mtd->resume = nand_resume;
2721         mtd->block_isbad = nand_block_isbad;
2722         mtd->block_markbad = nand_block_markbad;
2723
2724         /* propagate ecc.layout to mtd_info */
2725         mtd->ecclayout = chip->ecc.layout;
2726
2727         /* Check, if we should skip the bad block table scan */
2728         if (chip->options & NAND_SKIP_BBTSCAN)
2729                 chip->options |= NAND_BBT_SCANNED;
2730
2731         return 0;
2732 }
2733
2734 /* module_text_address() isn't exported, and it's mostly a pointless
2735    test if this is a module _anyway_ -- they'd have to try _really_ hard
2736    to call us from in-kernel code if the core NAND support is modular. */
2737 #ifdef MODULE
2738 #define caller_is_module() (1)
2739 #else
2740 #define caller_is_module() \
2741         module_text_address((unsigned long)__builtin_return_address(0))
2742 #endif
2743
2744 /**
2745  * nand_scan - [NAND Interface] Scan for the NAND device
2746  * @mtd:        MTD device structure
2747  * @maxchips:   Number of chips to scan for
2748  *
2749  * This fills out all the uninitialized function pointers
2750  * with the defaults.
2751  * The flash ID is read and the mtd/chip structures are
2752  * filled with the appropriate values.
2753  * The mtd->owner field must be set to the module of the caller
2754  *
2755  */
2756 int nand_scan(struct mtd_info *mtd, int maxchips)
2757 {
2758         int ret;
2759
2760         /* Many callers got this wrong, so check for it for a while... */
2761         /* XXX U-BOOT XXX */
2762 #if 0
2763         if (!mtd->owner && caller_is_module()) {
2764                 printk(KERN_CRIT "nand_scan() called with NULL mtd->owner!\n");
2765                 BUG();
2766         }
2767 #endif
2768
2769         ret = nand_scan_ident(mtd, maxchips);
2770         if (!ret)
2771                 ret = nand_scan_tail(mtd);
2772         return ret;
2773 }
2774
2775 /**
2776  * nand_release - [NAND Interface] Free resources held by the NAND device
2777  * @mtd:        MTD device structure
2778 */
2779 void nand_release(struct mtd_info *mtd)
2780 {
2781         struct nand_chip *chip = mtd->priv;
2782
2783 #ifdef CONFIG_MTD_PARTITIONS
2784         /* Deregister partitions */
2785         del_mtd_partitions(mtd);
2786 #endif
2787         /* Deregister the device */
2788         /* XXX U-BOOT XXX */
2789 #if 0
2790         del_mtd_device(mtd);
2791 #endif
2792
2793         /* Free bad block table memory */
2794         kfree(chip->bbt);
2795         if (!(chip->options & NAND_OWN_BUFFERS))
2796                 kfree(chip->buffers);
2797 }
2798
2799 /* XXX U-BOOT XXX */
2800 #if 0
2801 EXPORT_SYMBOL_GPL(nand_scan);
2802 EXPORT_SYMBOL_GPL(nand_scan_ident);
2803 EXPORT_SYMBOL_GPL(nand_scan_tail);
2804 EXPORT_SYMBOL_GPL(nand_release);
2805
2806 static int __init nand_base_init(void)
2807 {
2808         led_trigger_register_simple("nand-disk", &nand_led_trigger);
2809         return 0;
2810 }
2811
2812 static void __exit nand_base_exit(void)
2813 {
2814         led_trigger_unregister_simple(nand_led_trigger);
2815 }
2816
2817 module_init(nand_base_init);
2818 module_exit(nand_base_exit);
2819
2820 MODULE_LICENSE("GPL");
2821 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
2822 MODULE_DESCRIPTION("Generic NAND flash driver code");
2823 #endif
2824
2825 #endif
2826