5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
8 * Additional technical information is available on
9 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
12 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
15 * David Woodhouse for adding multichip support
17 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
18 * rework for 2K page size chips
21 * Enable cached programming for 2k page size chips
22 * Check, if mtd->ecctype should be set to MTD_ECC_HW
23 * if we have HW ECC support.
24 * BBT table is not serialized, has to be fixed
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License version 2 as
28 * published by the Free Software Foundation.
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
50 #include <linux/mtd/partitions.h>
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
56 #include <linux/err.h>
57 #include <linux/compat.h>
58 #include <linux/mtd/mtd.h>
59 #include <linux/mtd/nand.h>
60 #include <linux/mtd/nand_ecc.h>
61 #include <linux/mtd/nand_bch.h>
62 #ifdef CONFIG_MTD_PARTITIONS
63 #include <linux/mtd/partitions.h>
66 #include <asm/errno.h>
69 * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
70 * a flash. NAND flash is initialized prior to interrupts so standard timers
71 * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
72 * which is greater than (max NAND reset time / NAND status read time).
73 * A conservative default of 200000 (500 us / 25 ns) is used as a default.
75 #ifndef CONFIG_SYS_NAND_RESET_CNT
76 #define CONFIG_SYS_NAND_RESET_CNT 200000
79 static bool is_module_text_address(unsigned long addr) {return 0;}
82 /* Define default oob placement schemes for large and small page devices */
83 static struct nand_ecclayout nand_oob_8 = {
93 static struct nand_ecclayout nand_oob_16 = {
95 .eccpos = {0, 1, 2, 3, 6, 7},
101 static struct nand_ecclayout nand_oob_64 = {
104 40, 41, 42, 43, 44, 45, 46, 47,
105 48, 49, 50, 51, 52, 53, 54, 55,
106 56, 57, 58, 59, 60, 61, 62, 63},
112 static struct nand_ecclayout nand_oob_128 = {
115 80, 81, 82, 83, 84, 85, 86, 87,
116 88, 89, 90, 91, 92, 93, 94, 95,
117 96, 97, 98, 99, 100, 101, 102, 103,
118 104, 105, 106, 107, 108, 109, 110, 111,
119 112, 113, 114, 115, 116, 117, 118, 119,
120 120, 121, 122, 123, 124, 125, 126, 127},
126 static int nand_get_device(struct mtd_info *mtd, int new_state);
128 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
129 struct mtd_oob_ops *ops);
132 * For devices which display every fart in the system on a separate LED. Is
133 * compiled away when LED support is disabled.
135 DEFINE_LED_TRIGGER(nand_led_trigger);
137 static int check_offs_len(struct mtd_info *mtd,
138 loff_t ofs, uint64_t len)
140 struct nand_chip *chip = mtd->priv;
143 /* Start address must align on block boundary */
144 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
145 pr_debug("%s: unaligned address\n", __func__);
149 /* Length must align on block boundary */
150 if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
151 pr_debug("%s: length not block aligned\n", __func__);
159 * nand_release_device - [GENERIC] release chip
160 * @mtd: MTD device structure
162 * Release chip lock and wake up anyone waiting on the device.
164 static void nand_release_device(struct mtd_info *mtd)
166 struct nand_chip *chip = mtd->priv;
169 /* Release the controller and the chip */
170 spin_lock(&chip->controller->lock);
171 chip->controller->active = NULL;
172 chip->state = FL_READY;
173 wake_up(&chip->controller->wq);
174 spin_unlock(&chip->controller->lock);
176 /* De-select the NAND device */
177 chip->select_chip(mtd, -1);
182 * nand_read_byte - [DEFAULT] read one byte from the chip
183 * @mtd: MTD device structure
185 * Default read function for 8bit buswidth
188 static uint8_t nand_read_byte(struct mtd_info *mtd)
190 uint8_t nand_read_byte(struct mtd_info *mtd)
193 struct nand_chip *chip = mtd->priv;
194 return readb(chip->IO_ADDR_R);
198 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
199 * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
200 * @mtd: MTD device structure
202 * Default read function for 16bit buswidth with endianness conversion.
205 static uint8_t nand_read_byte16(struct mtd_info *mtd)
207 struct nand_chip *chip = mtd->priv;
208 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
212 * nand_read_word - [DEFAULT] read one word from the chip
213 * @mtd: MTD device structure
215 * Default read function for 16bit buswidth without endianness conversion.
217 static u16 nand_read_word(struct mtd_info *mtd)
219 struct nand_chip *chip = mtd->priv;
220 return readw(chip->IO_ADDR_R);
224 * nand_select_chip - [DEFAULT] control CE line
225 * @mtd: MTD device structure
226 * @chipnr: chipnumber to select, -1 for deselect
228 * Default select function for 1 chip devices.
230 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
232 struct nand_chip *chip = mtd->priv;
236 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
247 * nand_write_byte - [DEFAULT] write single byte to chip
248 * @mtd: MTD device structure
249 * @byte: value to write
251 * Default function to write a byte to I/O[7:0]
253 static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
255 struct nand_chip *chip = mtd->priv;
257 chip->write_buf(mtd, &byte, 1);
261 * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
262 * @mtd: MTD device structure
263 * @byte: value to write
265 * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
267 static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
269 struct nand_chip *chip = mtd->priv;
270 uint16_t word = byte;
273 * It's not entirely clear what should happen to I/O[15:8] when writing
274 * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
276 * When the host supports a 16-bit bus width, only data is
277 * transferred at the 16-bit width. All address and command line
278 * transfers shall use only the lower 8-bits of the data bus. During
279 * command transfers, the host may place any value on the upper
280 * 8-bits of the data bus. During address transfers, the host shall
281 * set the upper 8-bits of the data bus to 00h.
283 * One user of the write_byte callback is nand_onfi_set_features. The
284 * four parameters are specified to be written to I/O[7:0], but this is
285 * neither an address nor a command transfer. Let's assume a 0 on the
286 * upper I/O lines is OK.
288 chip->write_buf(mtd, (uint8_t *)&word, 2);
291 #if defined(__UBOOT__) && !defined(CONFIG_BLACKFIN)
292 static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
296 for (i = 0; i < len; i++)
297 writeb(buf[i], addr);
299 static void ioread8_rep(void *addr, uint8_t *buf, int len)
303 for (i = 0; i < len; i++)
304 buf[i] = readb(addr);
307 static void ioread16_rep(void *addr, void *buf, int len)
310 u16 *p = (u16 *) buf;
312 for (i = 0; i < len; i++)
316 static void iowrite16_rep(void *addr, void *buf, int len)
319 u16 *p = (u16 *) buf;
321 for (i = 0; i < len; i++)
327 * nand_write_buf - [DEFAULT] write buffer to chip
328 * @mtd: MTD device structure
330 * @len: number of bytes to write
332 * Default write function for 8bit buswidth.
335 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
337 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
340 struct nand_chip *chip = mtd->priv;
342 iowrite8_rep(chip->IO_ADDR_W, buf, len);
346 * nand_read_buf - [DEFAULT] read chip data into buffer
347 * @mtd: MTD device structure
348 * @buf: buffer to store date
349 * @len: number of bytes to read
351 * Default read function for 8bit buswidth.
354 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
356 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
359 struct nand_chip *chip = mtd->priv;
361 ioread8_rep(chip->IO_ADDR_R, buf, len);
365 * nand_write_buf16 - [DEFAULT] write buffer to chip
366 * @mtd: MTD device structure
368 * @len: number of bytes to write
370 * Default write function for 16bit buswidth.
373 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
375 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
378 struct nand_chip *chip = mtd->priv;
379 u16 *p = (u16 *) buf;
381 iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
385 * nand_read_buf16 - [DEFAULT] read chip data into buffer
386 * @mtd: MTD device structure
387 * @buf: buffer to store date
388 * @len: number of bytes to read
390 * Default read function for 16bit buswidth.
393 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
395 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
398 struct nand_chip *chip = mtd->priv;
399 u16 *p = (u16 *) buf;
401 ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
405 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
406 * @mtd: MTD device structure
407 * @ofs: offset from device start
408 * @getchip: 0, if the chip is already selected
410 * Check, if the block is bad.
412 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
414 int page, chipnr, res = 0, i = 0;
415 struct nand_chip *chip = mtd->priv;
418 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
419 ofs += mtd->erasesize - mtd->writesize;
421 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
424 chipnr = (int)(ofs >> chip->chip_shift);
426 nand_get_device(mtd, FL_READING);
428 /* Select the NAND device */
429 chip->select_chip(mtd, chipnr);
433 if (chip->options & NAND_BUSWIDTH_16) {
434 chip->cmdfunc(mtd, NAND_CMD_READOOB,
435 chip->badblockpos & 0xFE, page);
436 bad = cpu_to_le16(chip->read_word(mtd));
437 if (chip->badblockpos & 0x1)
442 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
444 bad = chip->read_byte(mtd);
447 if (likely(chip->badblockbits == 8))
450 res = hweight8(bad) < chip->badblockbits;
451 ofs += mtd->writesize;
452 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
454 } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
457 chip->select_chip(mtd, -1);
458 nand_release_device(mtd);
465 * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
466 * @mtd: MTD device structure
467 * @ofs: offset from device start
469 * This is the default implementation, which can be overridden by a hardware
470 * specific driver. It provides the details for writing a bad block marker to a
473 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
475 struct nand_chip *chip = mtd->priv;
476 struct mtd_oob_ops ops;
477 uint8_t buf[2] = { 0, 0 };
478 int ret = 0, res, i = 0;
482 ops.ooboffs = chip->badblockpos;
483 if (chip->options & NAND_BUSWIDTH_16) {
484 ops.ooboffs &= ~0x01;
485 ops.len = ops.ooblen = 2;
487 ops.len = ops.ooblen = 1;
489 ops.mode = MTD_OPS_PLACE_OOB;
491 /* Write to first/last page(s) if necessary */
492 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
493 ofs += mtd->erasesize - mtd->writesize;
495 res = nand_do_write_oob(mtd, ofs, &ops);
500 ofs += mtd->writesize;
501 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
507 * nand_block_markbad_lowlevel - mark a block bad
508 * @mtd: MTD device structure
509 * @ofs: offset from device start
511 * This function performs the generic NAND bad block marking steps (i.e., bad
512 * block table(s) and/or marker(s)). We only allow the hardware driver to
513 * specify how to write bad block markers to OOB (chip->block_markbad).
515 * We try operations in the following order:
516 * (1) erase the affected block, to allow OOB marker to be written cleanly
517 * (2) write bad block marker to OOB area of affected block (unless flag
518 * NAND_BBT_NO_OOB_BBM is present)
520 * Note that we retain the first error encountered in (2) or (3), finish the
521 * procedures, and dump the error in the end.
523 static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
525 struct nand_chip *chip = mtd->priv;
528 if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
529 struct erase_info einfo;
531 /* Attempt erase before marking OOB */
532 memset(&einfo, 0, sizeof(einfo));
535 einfo.len = 1ULL << chip->phys_erase_shift;
536 nand_erase_nand(mtd, &einfo, 0);
538 /* Write bad block marker to OOB */
539 nand_get_device(mtd, FL_WRITING);
540 ret = chip->block_markbad(mtd, ofs);
541 nand_release_device(mtd);
544 /* Mark block bad in BBT */
546 res = nand_markbad_bbt(mtd, ofs);
552 mtd->ecc_stats.badblocks++;
558 * nand_check_wp - [GENERIC] check if the chip is write protected
559 * @mtd: MTD device structure
561 * Check, if the device is write protected. The function expects, that the
562 * device is already selected.
564 static int nand_check_wp(struct mtd_info *mtd)
566 struct nand_chip *chip = mtd->priv;
568 /* Broken xD cards report WP despite being writable */
569 if (chip->options & NAND_BROKEN_XD)
572 /* Check the WP bit */
573 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
574 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
578 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
579 * @mtd: MTD device structure
580 * @ofs: offset from device start
581 * @getchip: 0, if the chip is already selected
582 * @allowbbt: 1, if its allowed to access the bbt area
584 * Check, if the block is bad. Either by reading the bad block table or
585 * calling of the scan function.
587 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
590 struct nand_chip *chip = mtd->priv;
592 if (!(chip->options & NAND_SKIP_BBTSCAN) &&
593 !(chip->options & NAND_BBT_SCANNED)) {
594 chip->options |= NAND_BBT_SCANNED;
599 return chip->block_bad(mtd, ofs, getchip);
601 /* Return info from the table */
602 return nand_isbad_bbt(mtd, ofs, allowbbt);
607 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
608 * @mtd: MTD device structure
611 * Helper function for nand_wait_ready used when needing to wait in interrupt
614 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
616 struct nand_chip *chip = mtd->priv;
619 /* Wait for the device to get ready */
620 for (i = 0; i < timeo; i++) {
621 if (chip->dev_ready(mtd))
623 touch_softlockup_watchdog();
629 /* Wait for the ready pin, after a command. The timeout is caught later. */
630 void nand_wait_ready(struct mtd_info *mtd)
632 struct nand_chip *chip = mtd->priv;
634 unsigned long timeo = jiffies + msecs_to_jiffies(20);
637 if (in_interrupt() || oops_in_progress)
638 return panic_nand_wait_ready(mtd, 400);
640 led_trigger_event(nand_led_trigger, LED_FULL);
641 /* Wait until command is processed or timeout occurs */
643 if (chip->dev_ready(mtd))
645 touch_softlockup_watchdog();
646 } while (time_before(jiffies, timeo));
647 led_trigger_event(nand_led_trigger, LED_OFF);
649 u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
652 time_start = get_timer(0);
653 /* Wait until command is processed or timeout occurs */
654 while (get_timer(time_start) < timeo) {
656 if (chip->dev_ready(mtd))
661 EXPORT_SYMBOL_GPL(nand_wait_ready);
664 * nand_command - [DEFAULT] Send command to NAND device
665 * @mtd: MTD device structure
666 * @command: the command to be sent
667 * @column: the column address for this command, -1 if none
668 * @page_addr: the page address for this command, -1 if none
670 * Send command to NAND device. This function is used for small page devices
671 * (512 Bytes per page).
673 static void nand_command(struct mtd_info *mtd, unsigned int command,
674 int column, int page_addr)
676 register struct nand_chip *chip = mtd->priv;
677 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
678 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
680 /* Write out the command to the device */
681 if (command == NAND_CMD_SEQIN) {
684 if (column >= mtd->writesize) {
686 column -= mtd->writesize;
687 readcmd = NAND_CMD_READOOB;
688 } else if (column < 256) {
689 /* First 256 bytes --> READ0 */
690 readcmd = NAND_CMD_READ0;
693 readcmd = NAND_CMD_READ1;
695 chip->cmd_ctrl(mtd, readcmd, ctrl);
696 ctrl &= ~NAND_CTRL_CHANGE;
698 chip->cmd_ctrl(mtd, command, ctrl);
700 /* Address cycle, when necessary */
701 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
702 /* Serially input address */
704 /* Adjust columns for 16 bit buswidth */
705 if (chip->options & NAND_BUSWIDTH_16 &&
706 !nand_opcode_8bits(command))
708 chip->cmd_ctrl(mtd, column, ctrl);
709 ctrl &= ~NAND_CTRL_CHANGE;
711 if (page_addr != -1) {
712 chip->cmd_ctrl(mtd, page_addr, ctrl);
713 ctrl &= ~NAND_CTRL_CHANGE;
714 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
715 /* One more address cycle for devices > 32MiB */
716 if (chip->chipsize > (32 << 20))
717 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
719 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
722 * Program and erase have their own busy handlers status and sequential
727 case NAND_CMD_PAGEPROG:
728 case NAND_CMD_ERASE1:
729 case NAND_CMD_ERASE2:
731 case NAND_CMD_STATUS:
737 udelay(chip->chip_delay);
738 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
739 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
741 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
742 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
746 /* This applies to read commands */
749 * If we don't have access to the busy pin, we apply the given
752 if (!chip->dev_ready) {
753 udelay(chip->chip_delay);
758 * Apply this short delay always to ensure that we do wait tWB in
759 * any case on any machine.
763 nand_wait_ready(mtd);
767 * nand_command_lp - [DEFAULT] Send command to NAND large page device
768 * @mtd: MTD device structure
769 * @command: the command to be sent
770 * @column: the column address for this command, -1 if none
771 * @page_addr: the page address for this command, -1 if none
773 * Send command to NAND device. This is the version for the new large page
774 * devices. We don't have the separate regions as we have in the small page
775 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
777 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
778 int column, int page_addr)
780 register struct nand_chip *chip = mtd->priv;
781 uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
783 /* Emulate NAND_CMD_READOOB */
784 if (command == NAND_CMD_READOOB) {
785 column += mtd->writesize;
786 command = NAND_CMD_READ0;
789 /* Command latch cycle */
790 chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
792 if (column != -1 || page_addr != -1) {
793 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
795 /* Serially input address */
797 /* Adjust columns for 16 bit buswidth */
798 if (chip->options & NAND_BUSWIDTH_16 &&
799 !nand_opcode_8bits(command))
801 chip->cmd_ctrl(mtd, column, ctrl);
802 ctrl &= ~NAND_CTRL_CHANGE;
803 chip->cmd_ctrl(mtd, column >> 8, ctrl);
805 if (page_addr != -1) {
806 chip->cmd_ctrl(mtd, page_addr, ctrl);
807 chip->cmd_ctrl(mtd, page_addr >> 8,
808 NAND_NCE | NAND_ALE);
809 /* One more address cycle for devices > 128MiB */
810 if (chip->chipsize > (128 << 20))
811 chip->cmd_ctrl(mtd, page_addr >> 16,
812 NAND_NCE | NAND_ALE);
815 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
818 * Program and erase have their own busy handlers status, sequential
819 * in, and deplete1 need no delay.
823 case NAND_CMD_CACHEDPROG:
824 case NAND_CMD_PAGEPROG:
825 case NAND_CMD_ERASE1:
826 case NAND_CMD_ERASE2:
829 case NAND_CMD_STATUS:
835 udelay(chip->chip_delay);
836 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
837 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
838 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
839 NAND_NCE | NAND_CTRL_CHANGE);
840 while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
844 case NAND_CMD_RNDOUT:
845 /* No ready / busy check necessary */
846 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
847 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
848 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
849 NAND_NCE | NAND_CTRL_CHANGE);
853 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
854 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
855 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
856 NAND_NCE | NAND_CTRL_CHANGE);
858 /* This applies to read commands */
861 * If we don't have access to the busy pin, we apply the given
864 if (!chip->dev_ready) {
865 udelay(chip->chip_delay);
871 * Apply this short delay always to ensure that we do wait tWB in
872 * any case on any machine.
876 nand_wait_ready(mtd);
880 * panic_nand_get_device - [GENERIC] Get chip for selected access
881 * @chip: the nand chip descriptor
882 * @mtd: MTD device structure
883 * @new_state: the state which is requested
885 * Used when in panic, no locks are taken.
887 static void panic_nand_get_device(struct nand_chip *chip,
888 struct mtd_info *mtd, int new_state)
890 /* Hardware controller shared among independent devices */
891 chip->controller->active = chip;
892 chip->state = new_state;
896 * nand_get_device - [GENERIC] Get chip for selected access
897 * @mtd: MTD device structure
898 * @new_state: the state which is requested
900 * Get the device and lock it for exclusive access
903 nand_get_device(struct mtd_info *mtd, int new_state)
905 struct nand_chip *chip = mtd->priv;
907 spinlock_t *lock = &chip->controller->lock;
908 wait_queue_head_t *wq = &chip->controller->wq;
909 DECLARE_WAITQUEUE(wait, current);
913 /* Hardware controller shared among independent devices */
914 if (!chip->controller->active)
915 chip->controller->active = chip;
917 if (chip->controller->active == chip && chip->state == FL_READY) {
918 chip->state = new_state;
922 if (new_state == FL_PM_SUSPENDED) {
923 if (chip->controller->active->state == FL_PM_SUSPENDED) {
924 chip->state = FL_PM_SUSPENDED;
929 set_current_state(TASK_UNINTERRUPTIBLE);
930 add_wait_queue(wq, &wait);
933 remove_wait_queue(wq, &wait);
936 chip->state = new_state;
942 * panic_nand_wait - [GENERIC] wait until the command is done
943 * @mtd: MTD device structure
944 * @chip: NAND chip structure
947 * Wait for command done. This is a helper function for nand_wait used when
948 * we are in interrupt context. May happen when in panic and trying to write
949 * an oops through mtdoops.
951 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
955 for (i = 0; i < timeo; i++) {
956 if (chip->dev_ready) {
957 if (chip->dev_ready(mtd))
960 if (chip->read_byte(mtd) & NAND_STATUS_READY)
968 * nand_wait - [DEFAULT] wait until the command is done
969 * @mtd: MTD device structure
970 * @chip: NAND chip structure
972 * Wait for command done. This applies to erase and program only. Erase can
973 * take up to 400ms and program up to 20ms according to general NAND and
976 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
979 int status, state = chip->state;
980 unsigned long timeo = (state == FL_ERASING ? 400 : 20);
982 led_trigger_event(nand_led_trigger, LED_FULL);
985 * Apply this short delay always to ensure that we do wait tWB in any
986 * case on any machine.
990 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
993 if (in_interrupt() || oops_in_progress)
994 panic_nand_wait(mtd, chip, timeo);
996 timeo = jiffies + msecs_to_jiffies(timeo);
997 while (time_before(jiffies, timeo)) {
998 if (chip->dev_ready) {
999 if (chip->dev_ready(mtd))
1002 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1009 u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
1012 time_start = get_timer(0);
1013 while (get_timer(time_start) < timer) {
1014 if (chip->dev_ready) {
1015 if (chip->dev_ready(mtd))
1018 if (chip->read_byte(mtd) & NAND_STATUS_READY)
1023 led_trigger_event(nand_led_trigger, LED_OFF);
1025 status = (int)chip->read_byte(mtd);
1026 /* This can happen if in case of timeout or buggy dev_ready */
1027 WARN_ON(!(status & NAND_STATUS_READY));
1033 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1035 * @ofs: offset to start unlock from
1036 * @len: length to unlock
1037 * @invert: when = 0, unlock the range of blocks within the lower and
1038 * upper boundary address
1039 * when = 1, unlock the range of blocks outside the boundaries
1040 * of the lower and upper boundary address
1042 * Returs unlock status.
1044 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
1045 uint64_t len, int invert)
1049 struct nand_chip *chip = mtd->priv;
1051 /* Submit address of first page to unlock */
1052 page = ofs >> chip->page_shift;
1053 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
1055 /* Submit address of last page to unlock */
1056 page = (ofs + len) >> chip->page_shift;
1057 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
1058 (page | invert) & chip->pagemask);
1060 /* Call wait ready function */
1061 status = chip->waitfunc(mtd, chip);
1062 /* See if device thinks it succeeded */
1063 if (status & NAND_STATUS_FAIL) {
1064 pr_debug("%s: error status = 0x%08x\n",
1073 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
1075 * @ofs: offset to start unlock from
1076 * @len: length to unlock
1078 * Returns unlock status.
1080 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1084 struct nand_chip *chip = mtd->priv;
1086 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1087 __func__, (unsigned long long)ofs, len);
1089 if (check_offs_len(mtd, ofs, len))
1092 /* Align to last block address if size addresses end of the device */
1093 if (ofs + len == mtd->size)
1094 len -= mtd->erasesize;
1096 nand_get_device(mtd, FL_UNLOCKING);
1098 /* Shift to get chip number */
1099 chipnr = ofs >> chip->chip_shift;
1101 chip->select_chip(mtd, chipnr);
1103 /* Check, if it is write protected */
1104 if (nand_check_wp(mtd)) {
1105 pr_debug("%s: device is write protected!\n",
1111 ret = __nand_unlock(mtd, ofs, len, 0);
1114 chip->select_chip(mtd, -1);
1115 nand_release_device(mtd);
1119 EXPORT_SYMBOL(nand_unlock);
1122 * nand_lock - [REPLACEABLE] locks all blocks present in the device
1124 * @ofs: offset to start unlock from
1125 * @len: length to unlock
1127 * This feature is not supported in many NAND parts. 'Micron' NAND parts do
1128 * have this feature, but it allows only to lock all blocks, not for specified
1129 * range for block. Implementing 'lock' feature by making use of 'unlock', for
1132 * Returns lock status.
1134 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1137 int chipnr, status, page;
1138 struct nand_chip *chip = mtd->priv;
1140 pr_debug("%s: start = 0x%012llx, len = %llu\n",
1141 __func__, (unsigned long long)ofs, len);
1143 if (check_offs_len(mtd, ofs, len))
1146 nand_get_device(mtd, FL_LOCKING);
1148 /* Shift to get chip number */
1149 chipnr = ofs >> chip->chip_shift;
1151 chip->select_chip(mtd, chipnr);
1153 /* Check, if it is write protected */
1154 if (nand_check_wp(mtd)) {
1155 pr_debug("%s: device is write protected!\n",
1157 status = MTD_ERASE_FAILED;
1162 /* Submit address of first page to lock */
1163 page = ofs >> chip->page_shift;
1164 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1166 /* Call wait ready function */
1167 status = chip->waitfunc(mtd, chip);
1168 /* See if device thinks it succeeded */
1169 if (status & NAND_STATUS_FAIL) {
1170 pr_debug("%s: error status = 0x%08x\n",
1176 ret = __nand_unlock(mtd, ofs, len, 0x1);
1179 chip->select_chip(mtd, -1);
1180 nand_release_device(mtd);
1184 EXPORT_SYMBOL(nand_lock);
1188 * nand_read_page_raw - [INTERN] read raw page data without ecc
1189 * @mtd: mtd info structure
1190 * @chip: nand chip info structure
1191 * @buf: buffer to store read data
1192 * @oob_required: caller requires OOB data read to chip->oob_poi
1193 * @page: page number to read
1195 * Not for syndrome calculating ECC controllers, which use a special oob layout.
1197 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1198 uint8_t *buf, int oob_required, int page)
1200 chip->read_buf(mtd, buf, mtd->writesize);
1202 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1207 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1208 * @mtd: mtd info structure
1209 * @chip: nand chip info structure
1210 * @buf: buffer to store read data
1211 * @oob_required: caller requires OOB data read to chip->oob_poi
1212 * @page: page number to read
1214 * We need a special oob layout and handling even when OOB isn't used.
1216 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1217 struct nand_chip *chip, uint8_t *buf,
1218 int oob_required, int page)
1220 int eccsize = chip->ecc.size;
1221 int eccbytes = chip->ecc.bytes;
1222 uint8_t *oob = chip->oob_poi;
1225 for (steps = chip->ecc.steps; steps > 0; steps--) {
1226 chip->read_buf(mtd, buf, eccsize);
1229 if (chip->ecc.prepad) {
1230 chip->read_buf(mtd, oob, chip->ecc.prepad);
1231 oob += chip->ecc.prepad;
1234 chip->read_buf(mtd, oob, eccbytes);
1237 if (chip->ecc.postpad) {
1238 chip->read_buf(mtd, oob, chip->ecc.postpad);
1239 oob += chip->ecc.postpad;
1243 size = mtd->oobsize - (oob - chip->oob_poi);
1245 chip->read_buf(mtd, oob, size);
1251 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1252 * @mtd: mtd info structure
1253 * @chip: nand chip info structure
1254 * @buf: buffer to store read data
1255 * @oob_required: caller requires OOB data read to chip->oob_poi
1256 * @page: page number to read
1258 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1259 uint8_t *buf, int oob_required, int page)
1261 int i, eccsize = chip->ecc.size;
1262 int eccbytes = chip->ecc.bytes;
1263 int eccsteps = chip->ecc.steps;
1265 uint8_t *ecc_calc = chip->buffers->ecccalc;
1266 uint8_t *ecc_code = chip->buffers->ecccode;
1267 uint32_t *eccpos = chip->ecc.layout->eccpos;
1268 unsigned int max_bitflips = 0;
1270 chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1272 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1273 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1275 for (i = 0; i < chip->ecc.total; i++)
1276 ecc_code[i] = chip->oob_poi[eccpos[i]];
1278 eccsteps = chip->ecc.steps;
1281 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1284 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1286 mtd->ecc_stats.failed++;
1288 mtd->ecc_stats.corrected += stat;
1289 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1292 return max_bitflips;
1296 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
1297 * @mtd: mtd info structure
1298 * @chip: nand chip info structure
1299 * @data_offs: offset of requested data within the page
1300 * @readlen: data length
1301 * @bufpoi: buffer to store read data
1302 * @page: page number to read
1304 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1305 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
1308 int start_step, end_step, num_steps;
1309 uint32_t *eccpos = chip->ecc.layout->eccpos;
1311 int data_col_addr, i, gaps = 0;
1312 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1313 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1315 unsigned int max_bitflips = 0;
1317 /* Column address within the page aligned to ECC size (256bytes) */
1318 start_step = data_offs / chip->ecc.size;
1319 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1320 num_steps = end_step - start_step + 1;
1321 index = start_step * chip->ecc.bytes;
1323 /* Data size aligned to ECC ecc.size */
1324 datafrag_len = num_steps * chip->ecc.size;
1325 eccfrag_len = num_steps * chip->ecc.bytes;
1327 data_col_addr = start_step * chip->ecc.size;
1328 /* If we read not a page aligned data */
1329 if (data_col_addr != 0)
1330 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1332 p = bufpoi + data_col_addr;
1333 chip->read_buf(mtd, p, datafrag_len);
1336 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1337 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1340 * The performance is faster if we position offsets according to
1341 * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1343 for (i = 0; i < eccfrag_len - 1; i++) {
1344 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1345 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1351 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1352 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1355 * Send the command to read the particular ECC bytes take care
1356 * about buswidth alignment in read_buf.
1358 aligned_pos = eccpos[index] & ~(busw - 1);
1359 aligned_len = eccfrag_len;
1360 if (eccpos[index] & (busw - 1))
1362 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1365 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1366 mtd->writesize + aligned_pos, -1);
1367 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1370 for (i = 0; i < eccfrag_len; i++)
1371 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1373 p = bufpoi + data_col_addr;
1374 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1377 stat = chip->ecc.correct(mtd, p,
1378 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1380 mtd->ecc_stats.failed++;
1382 mtd->ecc_stats.corrected += stat;
1383 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1386 return max_bitflips;
1390 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1391 * @mtd: mtd info structure
1392 * @chip: nand chip info structure
1393 * @buf: buffer to store read data
1394 * @oob_required: caller requires OOB data read to chip->oob_poi
1395 * @page: page number to read
1397 * Not for syndrome calculating ECC controllers which need a special oob layout.
1399 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1400 uint8_t *buf, int oob_required, int page)
1402 int i, eccsize = chip->ecc.size;
1403 int eccbytes = chip->ecc.bytes;
1404 int eccsteps = chip->ecc.steps;
1406 uint8_t *ecc_calc = chip->buffers->ecccalc;
1407 uint8_t *ecc_code = chip->buffers->ecccode;
1408 uint32_t *eccpos = chip->ecc.layout->eccpos;
1409 unsigned int max_bitflips = 0;
1411 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1412 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1413 chip->read_buf(mtd, p, eccsize);
1414 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1416 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1418 for (i = 0; i < chip->ecc.total; i++)
1419 ecc_code[i] = chip->oob_poi[eccpos[i]];
1421 eccsteps = chip->ecc.steps;
1424 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1427 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1429 mtd->ecc_stats.failed++;
1431 mtd->ecc_stats.corrected += stat;
1432 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1435 return max_bitflips;
1439 * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1440 * @mtd: mtd info structure
1441 * @chip: nand chip info structure
1442 * @buf: buffer to store read data
1443 * @oob_required: caller requires OOB data read to chip->oob_poi
1444 * @page: page number to read
1446 * Hardware ECC for large page chips, require OOB to be read first. For this
1447 * ECC mode, the write_page method is re-used from ECC_HW. These methods
1448 * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1449 * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1450 * the data area, by overwriting the NAND manufacturer bad block markings.
1452 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1453 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1455 int i, eccsize = chip->ecc.size;
1456 int eccbytes = chip->ecc.bytes;
1457 int eccsteps = chip->ecc.steps;
1459 uint8_t *ecc_code = chip->buffers->ecccode;
1460 uint32_t *eccpos = chip->ecc.layout->eccpos;
1461 uint8_t *ecc_calc = chip->buffers->ecccalc;
1462 unsigned int max_bitflips = 0;
1464 /* Read the OOB area first */
1465 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1466 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1467 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1469 for (i = 0; i < chip->ecc.total; i++)
1470 ecc_code[i] = chip->oob_poi[eccpos[i]];
1472 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1475 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1476 chip->read_buf(mtd, p, eccsize);
1477 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1479 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1481 mtd->ecc_stats.failed++;
1483 mtd->ecc_stats.corrected += stat;
1484 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1487 return max_bitflips;
1491 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1492 * @mtd: mtd info structure
1493 * @chip: nand chip info structure
1494 * @buf: buffer to store read data
1495 * @oob_required: caller requires OOB data read to chip->oob_poi
1496 * @page: page number to read
1498 * The hw generator calculates the error syndrome automatically. Therefore we
1499 * need a special oob layout and handling.
1501 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1502 uint8_t *buf, int oob_required, int page)
1504 int i, eccsize = chip->ecc.size;
1505 int eccbytes = chip->ecc.bytes;
1506 int eccsteps = chip->ecc.steps;
1508 uint8_t *oob = chip->oob_poi;
1509 unsigned int max_bitflips = 0;
1511 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1514 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1515 chip->read_buf(mtd, p, eccsize);
1517 if (chip->ecc.prepad) {
1518 chip->read_buf(mtd, oob, chip->ecc.prepad);
1519 oob += chip->ecc.prepad;
1522 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1523 chip->read_buf(mtd, oob, eccbytes);
1524 stat = chip->ecc.correct(mtd, p, oob, NULL);
1527 mtd->ecc_stats.failed++;
1529 mtd->ecc_stats.corrected += stat;
1530 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1535 if (chip->ecc.postpad) {
1536 chip->read_buf(mtd, oob, chip->ecc.postpad);
1537 oob += chip->ecc.postpad;
1541 /* Calculate remaining oob bytes */
1542 i = mtd->oobsize - (oob - chip->oob_poi);
1544 chip->read_buf(mtd, oob, i);
1546 return max_bitflips;
1550 * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1551 * @chip: nand chip structure
1552 * @oob: oob destination address
1553 * @ops: oob ops structure
1554 * @len: size of oob to transfer
1556 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1557 struct mtd_oob_ops *ops, size_t len)
1559 switch (ops->mode) {
1561 case MTD_OPS_PLACE_OOB:
1563 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1566 case MTD_OPS_AUTO_OOB: {
1567 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1568 uint32_t boffs = 0, roffs = ops->ooboffs;
1571 for (; free->length && len; free++, len -= bytes) {
1572 /* Read request not from offset 0? */
1573 if (unlikely(roffs)) {
1574 if (roffs >= free->length) {
1575 roffs -= free->length;
1578 boffs = free->offset + roffs;
1579 bytes = min_t(size_t, len,
1580 (free->length - roffs));
1583 bytes = min_t(size_t, len, free->length);
1584 boffs = free->offset;
1586 memcpy(oob, chip->oob_poi + boffs, bytes);
1598 * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
1599 * @mtd: MTD device structure
1600 * @retry_mode: the retry mode to use
1602 * Some vendors supply a special command to shift the Vt threshold, to be used
1603 * when there are too many bitflips in a page (i.e., ECC error). After setting
1604 * a new threshold, the host should retry reading the page.
1606 static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
1608 struct nand_chip *chip = mtd->priv;
1610 pr_debug("setting READ RETRY mode %d\n", retry_mode);
1612 if (retry_mode >= chip->read_retries)
1615 if (!chip->setup_read_retry)
1618 return chip->setup_read_retry(mtd, retry_mode);
1622 * nand_do_read_ops - [INTERN] Read data with ECC
1623 * @mtd: MTD device structure
1624 * @from: offset to read from
1625 * @ops: oob ops structure
1627 * Internal function. Called with chip held.
1629 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1630 struct mtd_oob_ops *ops)
1632 int chipnr, page, realpage, col, bytes, aligned, oob_required;
1633 struct nand_chip *chip = mtd->priv;
1635 uint32_t readlen = ops->len;
1636 uint32_t oobreadlen = ops->ooblen;
1637 uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1638 mtd->oobavail : mtd->oobsize;
1640 uint8_t *bufpoi, *oob, *buf;
1641 unsigned int max_bitflips = 0;
1643 bool ecc_fail = false;
1645 chipnr = (int)(from >> chip->chip_shift);
1646 chip->select_chip(mtd, chipnr);
1648 realpage = (int)(from >> chip->page_shift);
1649 page = realpage & chip->pagemask;
1651 col = (int)(from & (mtd->writesize - 1));
1655 oob_required = oob ? 1 : 0;
1658 unsigned int ecc_failures = mtd->ecc_stats.failed;
1661 bytes = min(mtd->writesize - col, readlen);
1662 aligned = (bytes == mtd->writesize);
1664 /* Is the current page in the buffer? */
1665 if (realpage != chip->pagebuf || oob) {
1666 bufpoi = aligned ? buf : chip->buffers->databuf;
1669 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1672 * Now read the page into the buffer. Absent an error,
1673 * the read methods return max bitflips per ecc step.
1675 if (unlikely(ops->mode == MTD_OPS_RAW))
1676 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1679 else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1681 ret = chip->ecc.read_subpage(mtd, chip,
1685 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1686 oob_required, page);
1689 /* Invalidate page cache */
1694 max_bitflips = max_t(unsigned int, max_bitflips, ret);
1696 /* Transfer not aligned data */
1698 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1699 !(mtd->ecc_stats.failed - ecc_failures) &&
1700 (ops->mode != MTD_OPS_RAW)) {
1701 chip->pagebuf = realpage;
1702 chip->pagebuf_bitflips = ret;
1704 /* Invalidate page cache */
1707 memcpy(buf, chip->buffers->databuf + col, bytes);
1710 if (unlikely(oob)) {
1711 int toread = min(oobreadlen, max_oobsize);
1714 oob = nand_transfer_oob(chip,
1716 oobreadlen -= toread;
1720 if (chip->options & NAND_NEED_READRDY) {
1721 /* Apply delay or wait for ready/busy pin */
1722 if (!chip->dev_ready)
1723 udelay(chip->chip_delay);
1725 nand_wait_ready(mtd);
1728 if (mtd->ecc_stats.failed - ecc_failures) {
1729 if (retry_mode + 1 < chip->read_retries) {
1731 ret = nand_setup_read_retry(mtd,
1736 /* Reset failures; retry */
1737 mtd->ecc_stats.failed = ecc_failures;
1740 /* No more retry modes; real failure */
1747 memcpy(buf, chip->buffers->databuf + col, bytes);
1749 max_bitflips = max_t(unsigned int, max_bitflips,
1750 chip->pagebuf_bitflips);
1755 /* Reset to retry mode 0 */
1757 ret = nand_setup_read_retry(mtd, 0);
1766 /* For subsequent reads align to page boundary */
1768 /* Increment page address */
1771 page = realpage & chip->pagemask;
1772 /* Check, if we cross a chip boundary */
1775 chip->select_chip(mtd, -1);
1776 chip->select_chip(mtd, chipnr);
1779 chip->select_chip(mtd, -1);
1781 ops->retlen = ops->len - (size_t) readlen;
1783 ops->oobretlen = ops->ooblen - oobreadlen;
1791 return max_bitflips;
1795 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1796 * @mtd: MTD device structure
1797 * @from: offset to read from
1798 * @len: number of bytes to read
1799 * @retlen: pointer to variable to store the number of read bytes
1800 * @buf: the databuffer to put data
1802 * Get hold of the chip and call nand_do_read.
1804 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1805 size_t *retlen, uint8_t *buf)
1807 struct mtd_oob_ops ops;
1810 nand_get_device(mtd, FL_READING);
1814 ops.mode = MTD_OPS_PLACE_OOB;
1815 ret = nand_do_read_ops(mtd, from, &ops);
1816 *retlen = ops.retlen;
1817 nand_release_device(mtd);
1822 * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1823 * @mtd: mtd info structure
1824 * @chip: nand chip info structure
1825 * @page: page number to read
1827 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1830 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1831 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1836 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1838 * @mtd: mtd info structure
1839 * @chip: nand chip info structure
1840 * @page: page number to read
1842 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1845 uint8_t *buf = chip->oob_poi;
1846 int length = mtd->oobsize;
1847 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1848 int eccsize = chip->ecc.size;
1849 uint8_t *bufpoi = buf;
1850 int i, toread, sndrnd = 0, pos;
1852 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1853 for (i = 0; i < chip->ecc.steps; i++) {
1855 pos = eccsize + i * (eccsize + chunk);
1856 if (mtd->writesize > 512)
1857 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1859 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1862 toread = min_t(int, length, chunk);
1863 chip->read_buf(mtd, bufpoi, toread);
1868 chip->read_buf(mtd, bufpoi, length);
1874 * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1875 * @mtd: mtd info structure
1876 * @chip: nand chip info structure
1877 * @page: page number to write
1879 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1883 const uint8_t *buf = chip->oob_poi;
1884 int length = mtd->oobsize;
1886 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1887 chip->write_buf(mtd, buf, length);
1888 /* Send command to program the OOB data */
1889 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1891 status = chip->waitfunc(mtd, chip);
1893 return status & NAND_STATUS_FAIL ? -EIO : 0;
1897 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1898 * with syndrome - only for large page flash
1899 * @mtd: mtd info structure
1900 * @chip: nand chip info structure
1901 * @page: page number to write
1903 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1904 struct nand_chip *chip, int page)
1906 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1907 int eccsize = chip->ecc.size, length = mtd->oobsize;
1908 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1909 const uint8_t *bufpoi = chip->oob_poi;
1912 * data-ecc-data-ecc ... ecc-oob
1914 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1916 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1917 pos = steps * (eccsize + chunk);
1922 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1923 for (i = 0; i < steps; i++) {
1925 if (mtd->writesize <= 512) {
1926 uint32_t fill = 0xFFFFFFFF;
1930 int num = min_t(int, len, 4);
1931 chip->write_buf(mtd, (uint8_t *)&fill,
1936 pos = eccsize + i * (eccsize + chunk);
1937 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1941 len = min_t(int, length, chunk);
1942 chip->write_buf(mtd, bufpoi, len);
1947 chip->write_buf(mtd, bufpoi, length);
1949 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1950 status = chip->waitfunc(mtd, chip);
1952 return status & NAND_STATUS_FAIL ? -EIO : 0;
1956 * nand_do_read_oob - [INTERN] NAND read out-of-band
1957 * @mtd: MTD device structure
1958 * @from: offset to read from
1959 * @ops: oob operations description structure
1961 * NAND read out-of-band data from the spare area.
1963 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1964 struct mtd_oob_ops *ops)
1966 int page, realpage, chipnr;
1967 struct nand_chip *chip = mtd->priv;
1968 struct mtd_ecc_stats stats;
1969 int readlen = ops->ooblen;
1971 uint8_t *buf = ops->oobbuf;
1974 pr_debug("%s: from = 0x%08Lx, len = %i\n",
1975 __func__, (unsigned long long)from, readlen);
1977 stats = mtd->ecc_stats;
1979 if (ops->mode == MTD_OPS_AUTO_OOB)
1980 len = chip->ecc.layout->oobavail;
1984 if (unlikely(ops->ooboffs >= len)) {
1985 pr_debug("%s: attempt to start read outside oob\n",
1990 /* Do not allow reads past end of device */
1991 if (unlikely(from >= mtd->size ||
1992 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1993 (from >> chip->page_shift)) * len)) {
1994 pr_debug("%s: attempt to read beyond end of device\n",
1999 chipnr = (int)(from >> chip->chip_shift);
2000 chip->select_chip(mtd, chipnr);
2002 /* Shift to get page */
2003 realpage = (int)(from >> chip->page_shift);
2004 page = realpage & chip->pagemask;
2009 if (ops->mode == MTD_OPS_RAW)
2010 ret = chip->ecc.read_oob_raw(mtd, chip, page);
2012 ret = chip->ecc.read_oob(mtd, chip, page);
2017 len = min(len, readlen);
2018 buf = nand_transfer_oob(chip, buf, ops, len);
2020 if (chip->options & NAND_NEED_READRDY) {
2021 /* Apply delay or wait for ready/busy pin */
2022 if (!chip->dev_ready)
2023 udelay(chip->chip_delay);
2025 nand_wait_ready(mtd);
2032 /* Increment page address */
2035 page = realpage & chip->pagemask;
2036 /* Check, if we cross a chip boundary */
2039 chip->select_chip(mtd, -1);
2040 chip->select_chip(mtd, chipnr);
2043 chip->select_chip(mtd, -1);
2045 ops->oobretlen = ops->ooblen - readlen;
2050 if (mtd->ecc_stats.failed - stats.failed)
2053 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
2057 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
2058 * @mtd: MTD device structure
2059 * @from: offset to read from
2060 * @ops: oob operation description structure
2062 * NAND read data and/or out-of-band data.
2064 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
2065 struct mtd_oob_ops *ops)
2067 int ret = -ENOTSUPP;
2071 /* Do not allow reads past end of device */
2072 if (ops->datbuf && (from + ops->len) > mtd->size) {
2073 pr_debug("%s: attempt to read beyond end of device\n",
2078 nand_get_device(mtd, FL_READING);
2080 switch (ops->mode) {
2081 case MTD_OPS_PLACE_OOB:
2082 case MTD_OPS_AUTO_OOB:
2091 ret = nand_do_read_oob(mtd, from, ops);
2093 ret = nand_do_read_ops(mtd, from, ops);
2096 nand_release_device(mtd);
2102 * nand_write_page_raw - [INTERN] raw page write function
2103 * @mtd: mtd info structure
2104 * @chip: nand chip info structure
2106 * @oob_required: must write chip->oob_poi to OOB
2108 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2110 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
2111 const uint8_t *buf, int oob_required)
2113 chip->write_buf(mtd, buf, mtd->writesize);
2115 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2121 * nand_write_page_raw_syndrome - [INTERN] raw page write function
2122 * @mtd: mtd info structure
2123 * @chip: nand chip info structure
2125 * @oob_required: must write chip->oob_poi to OOB
2127 * We need a special oob layout and handling even when ECC isn't checked.
2129 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
2130 struct nand_chip *chip,
2131 const uint8_t *buf, int oob_required)
2133 int eccsize = chip->ecc.size;
2134 int eccbytes = chip->ecc.bytes;
2135 uint8_t *oob = chip->oob_poi;
2138 for (steps = chip->ecc.steps; steps > 0; steps--) {
2139 chip->write_buf(mtd, buf, eccsize);
2142 if (chip->ecc.prepad) {
2143 chip->write_buf(mtd, oob, chip->ecc.prepad);
2144 oob += chip->ecc.prepad;
2147 chip->write_buf(mtd, oob, eccbytes);
2150 if (chip->ecc.postpad) {
2151 chip->write_buf(mtd, oob, chip->ecc.postpad);
2152 oob += chip->ecc.postpad;
2156 size = mtd->oobsize - (oob - chip->oob_poi);
2158 chip->write_buf(mtd, oob, size);
2163 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
2164 * @mtd: mtd info structure
2165 * @chip: nand chip info structure
2167 * @oob_required: must write chip->oob_poi to OOB
2169 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
2170 const uint8_t *buf, int oob_required)
2172 int i, eccsize = chip->ecc.size;
2173 int eccbytes = chip->ecc.bytes;
2174 int eccsteps = chip->ecc.steps;
2175 uint8_t *ecc_calc = chip->buffers->ecccalc;
2176 const uint8_t *p = buf;
2177 uint32_t *eccpos = chip->ecc.layout->eccpos;
2179 /* Software ECC calculation */
2180 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
2181 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2183 for (i = 0; i < chip->ecc.total; i++)
2184 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2186 return chip->ecc.write_page_raw(mtd, chip, buf, 1);
2190 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
2191 * @mtd: mtd info structure
2192 * @chip: nand chip info structure
2194 * @oob_required: must write chip->oob_poi to OOB
2196 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
2197 const uint8_t *buf, int oob_required)
2199 int i, eccsize = chip->ecc.size;
2200 int eccbytes = chip->ecc.bytes;
2201 int eccsteps = chip->ecc.steps;
2202 uint8_t *ecc_calc = chip->buffers->ecccalc;
2203 const uint8_t *p = buf;
2204 uint32_t *eccpos = chip->ecc.layout->eccpos;
2206 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2207 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2208 chip->write_buf(mtd, p, eccsize);
2209 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2212 for (i = 0; i < chip->ecc.total; i++)
2213 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2215 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2222 * nand_write_subpage_hwecc - [REPLACABLE] hardware ECC based subpage write
2223 * @mtd: mtd info structure
2224 * @chip: nand chip info structure
2225 * @offset: column address of subpage within the page
2226 * @data_len: data length
2228 * @oob_required: must write chip->oob_poi to OOB
2230 static int nand_write_subpage_hwecc(struct mtd_info *mtd,
2231 struct nand_chip *chip, uint32_t offset,
2232 uint32_t data_len, const uint8_t *buf,
2235 uint8_t *oob_buf = chip->oob_poi;
2236 uint8_t *ecc_calc = chip->buffers->ecccalc;
2237 int ecc_size = chip->ecc.size;
2238 int ecc_bytes = chip->ecc.bytes;
2239 int ecc_steps = chip->ecc.steps;
2240 uint32_t *eccpos = chip->ecc.layout->eccpos;
2241 uint32_t start_step = offset / ecc_size;
2242 uint32_t end_step = (offset + data_len - 1) / ecc_size;
2243 int oob_bytes = mtd->oobsize / ecc_steps;
2246 for (step = 0; step < ecc_steps; step++) {
2247 /* configure controller for WRITE access */
2248 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2250 /* write data (untouched subpages already masked by 0xFF) */
2251 chip->write_buf(mtd, buf, ecc_size);
2253 /* mask ECC of un-touched subpages by padding 0xFF */
2254 if ((step < start_step) || (step > end_step))
2255 memset(ecc_calc, 0xff, ecc_bytes);
2257 chip->ecc.calculate(mtd, buf, ecc_calc);
2259 /* mask OOB of un-touched subpages by padding 0xFF */
2260 /* if oob_required, preserve OOB metadata of written subpage */
2261 if (!oob_required || (step < start_step) || (step > end_step))
2262 memset(oob_buf, 0xff, oob_bytes);
2265 ecc_calc += ecc_bytes;
2266 oob_buf += oob_bytes;
2269 /* copy calculated ECC for whole page to chip->buffer->oob */
2270 /* this include masked-value(0xFF) for unwritten subpages */
2271 ecc_calc = chip->buffers->ecccalc;
2272 for (i = 0; i < chip->ecc.total; i++)
2273 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2275 /* write OOB buffer to NAND device */
2276 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2283 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2284 * @mtd: mtd info structure
2285 * @chip: nand chip info structure
2287 * @oob_required: must write chip->oob_poi to OOB
2289 * The hw generator calculates the error syndrome automatically. Therefore we
2290 * need a special oob layout and handling.
2292 static int nand_write_page_syndrome(struct mtd_info *mtd,
2293 struct nand_chip *chip,
2294 const uint8_t *buf, int oob_required)
2296 int i, eccsize = chip->ecc.size;
2297 int eccbytes = chip->ecc.bytes;
2298 int eccsteps = chip->ecc.steps;
2299 const uint8_t *p = buf;
2300 uint8_t *oob = chip->oob_poi;
2302 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2304 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2305 chip->write_buf(mtd, p, eccsize);
2307 if (chip->ecc.prepad) {
2308 chip->write_buf(mtd, oob, chip->ecc.prepad);
2309 oob += chip->ecc.prepad;
2312 chip->ecc.calculate(mtd, p, oob);
2313 chip->write_buf(mtd, oob, eccbytes);
2316 if (chip->ecc.postpad) {
2317 chip->write_buf(mtd, oob, chip->ecc.postpad);
2318 oob += chip->ecc.postpad;
2322 /* Calculate remaining oob bytes */
2323 i = mtd->oobsize - (oob - chip->oob_poi);
2325 chip->write_buf(mtd, oob, i);
2331 * nand_write_page - [REPLACEABLE] write one page
2332 * @mtd: MTD device structure
2333 * @chip: NAND chip descriptor
2334 * @offset: address offset within the page
2335 * @data_len: length of actual data to be written
2336 * @buf: the data to write
2337 * @oob_required: must write chip->oob_poi to OOB
2338 * @page: page number to write
2339 * @cached: cached programming
2340 * @raw: use _raw version of write_page
2342 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2343 uint32_t offset, int data_len, const uint8_t *buf,
2344 int oob_required, int page, int cached, int raw)
2346 int status, subpage;
2348 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2349 chip->ecc.write_subpage)
2350 subpage = offset || (data_len < mtd->writesize);
2354 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2357 status = chip->ecc.write_page_raw(mtd, chip, buf,
2360 status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
2363 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2369 * Cached progamming disabled for now. Not sure if it's worth the
2370 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2374 if (!cached || !NAND_HAS_CACHEPROG(chip)) {
2376 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2377 status = chip->waitfunc(mtd, chip);
2379 * See if operation failed and additional status checks are
2382 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2383 status = chip->errstat(mtd, chip, FL_WRITING, status,
2386 if (status & NAND_STATUS_FAIL)
2389 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2390 status = chip->waitfunc(mtd, chip);
2397 * nand_fill_oob - [INTERN] Transfer client buffer to oob
2398 * @mtd: MTD device structure
2399 * @oob: oob data buffer
2400 * @len: oob data write length
2401 * @ops: oob ops structure
2403 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2404 struct mtd_oob_ops *ops)
2406 struct nand_chip *chip = mtd->priv;
2409 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2410 * data from a previous OOB read.
2412 memset(chip->oob_poi, 0xff, mtd->oobsize);
2414 switch (ops->mode) {
2416 case MTD_OPS_PLACE_OOB:
2418 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2421 case MTD_OPS_AUTO_OOB: {
2422 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2423 uint32_t boffs = 0, woffs = ops->ooboffs;
2426 for (; free->length && len; free++, len -= bytes) {
2427 /* Write request not from offset 0? */
2428 if (unlikely(woffs)) {
2429 if (woffs >= free->length) {
2430 woffs -= free->length;
2433 boffs = free->offset + woffs;
2434 bytes = min_t(size_t, len,
2435 (free->length - woffs));
2438 bytes = min_t(size_t, len, free->length);
2439 boffs = free->offset;
2441 memcpy(chip->oob_poi + boffs, oob, bytes);
2452 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2455 * nand_do_write_ops - [INTERN] NAND write with ECC
2456 * @mtd: MTD device structure
2457 * @to: offset to write to
2458 * @ops: oob operations description structure
2460 * NAND write with ECC.
2462 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2463 struct mtd_oob_ops *ops)
2465 int chipnr, realpage, page, blockmask, column;
2466 struct nand_chip *chip = mtd->priv;
2467 uint32_t writelen = ops->len;
2469 uint32_t oobwritelen = ops->ooblen;
2470 uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2471 mtd->oobavail : mtd->oobsize;
2473 uint8_t *oob = ops->oobbuf;
2474 uint8_t *buf = ops->datbuf;
2476 int oob_required = oob ? 1 : 0;
2483 /* Reject writes, which are not page aligned */
2484 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2486 /* Reject writes, which are not page aligned */
2487 if (NOTALIGNED(to)) {
2489 pr_notice("%s: attempt to write non page aligned data\n",
2494 column = to & (mtd->writesize - 1);
2496 chipnr = (int)(to >> chip->chip_shift);
2497 chip->select_chip(mtd, chipnr);
2499 /* Check, if it is write protected */
2500 if (nand_check_wp(mtd)) {
2505 realpage = (int)(to >> chip->page_shift);
2506 page = realpage & chip->pagemask;
2507 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2509 /* Invalidate the page cache, when we write to the cached page */
2510 if (to <= (chip->pagebuf << chip->page_shift) &&
2511 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2514 /* Don't allow multipage oob writes with offset */
2515 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
2521 int bytes = mtd->writesize;
2522 int cached = writelen > bytes && page != blockmask;
2523 uint8_t *wbuf = buf;
2526 /* Partial page write? */
2527 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2529 bytes = min_t(int, bytes - column, (int) writelen);
2531 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2532 memcpy(&chip->buffers->databuf[column], buf, bytes);
2533 wbuf = chip->buffers->databuf;
2536 if (unlikely(oob)) {
2537 size_t len = min(oobwritelen, oobmaxlen);
2538 oob = nand_fill_oob(mtd, oob, len, ops);
2541 /* We still need to erase leftover OOB data */
2542 memset(chip->oob_poi, 0xff, mtd->oobsize);
2544 ret = chip->write_page(mtd, chip, column, bytes, wbuf,
2545 oob_required, page, cached,
2546 (ops->mode == MTD_OPS_RAW));
2558 page = realpage & chip->pagemask;
2559 /* Check, if we cross a chip boundary */
2562 chip->select_chip(mtd, -1);
2563 chip->select_chip(mtd, chipnr);
2567 ops->retlen = ops->len - writelen;
2569 ops->oobretlen = ops->ooblen;
2572 chip->select_chip(mtd, -1);
2577 * panic_nand_write - [MTD Interface] NAND write with ECC
2578 * @mtd: MTD device structure
2579 * @to: offset to write to
2580 * @len: number of bytes to write
2581 * @retlen: pointer to variable to store the number of written bytes
2582 * @buf: the data to write
2584 * NAND write with ECC. Used when performing writes in interrupt context, this
2585 * may for example be called by mtdoops when writing an oops while in panic.
2587 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2588 size_t *retlen, const uint8_t *buf)
2590 struct nand_chip *chip = mtd->priv;
2591 struct mtd_oob_ops ops;
2594 /* Wait for the device to get ready */
2595 panic_nand_wait(mtd, chip, 400);
2597 /* Grab the device */
2598 panic_nand_get_device(chip, mtd, FL_WRITING);
2601 ops.datbuf = (uint8_t *)buf;
2603 ops.mode = MTD_OPS_PLACE_OOB;
2605 ret = nand_do_write_ops(mtd, to, &ops);
2607 *retlen = ops.retlen;
2612 * nand_write - [MTD Interface] NAND write with ECC
2613 * @mtd: MTD device structure
2614 * @to: offset to write to
2615 * @len: number of bytes to write
2616 * @retlen: pointer to variable to store the number of written bytes
2617 * @buf: the data to write
2619 * NAND write with ECC.
2621 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2622 size_t *retlen, const uint8_t *buf)
2624 struct mtd_oob_ops ops;
2627 nand_get_device(mtd, FL_WRITING);
2629 ops.datbuf = (uint8_t *)buf;
2631 ops.mode = MTD_OPS_PLACE_OOB;
2632 ret = nand_do_write_ops(mtd, to, &ops);
2633 *retlen = ops.retlen;
2634 nand_release_device(mtd);
2639 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2640 * @mtd: MTD device structure
2641 * @to: offset to write to
2642 * @ops: oob operation description structure
2644 * NAND write out-of-band.
2646 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2647 struct mtd_oob_ops *ops)
2649 int chipnr, page, status, len;
2650 struct nand_chip *chip = mtd->priv;
2652 pr_debug("%s: to = 0x%08x, len = %i\n",
2653 __func__, (unsigned int)to, (int)ops->ooblen);
2655 if (ops->mode == MTD_OPS_AUTO_OOB)
2656 len = chip->ecc.layout->oobavail;
2660 /* Do not allow write past end of page */
2661 if ((ops->ooboffs + ops->ooblen) > len) {
2662 pr_debug("%s: attempt to write past end of page\n",
2667 if (unlikely(ops->ooboffs >= len)) {
2668 pr_debug("%s: attempt to start write outside oob\n",
2673 /* Do not allow write past end of device */
2674 if (unlikely(to >= mtd->size ||
2675 ops->ooboffs + ops->ooblen >
2676 ((mtd->size >> chip->page_shift) -
2677 (to >> chip->page_shift)) * len)) {
2678 pr_debug("%s: attempt to write beyond end of device\n",
2683 chipnr = (int)(to >> chip->chip_shift);
2684 chip->select_chip(mtd, chipnr);
2686 /* Shift to get page */
2687 page = (int)(to >> chip->page_shift);
2690 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2691 * of my DiskOnChip 2000 test units) will clear the whole data page too
2692 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2693 * it in the doc2000 driver in August 1999. dwmw2.
2695 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2697 /* Check, if it is write protected */
2698 if (nand_check_wp(mtd)) {
2699 chip->select_chip(mtd, -1);
2703 /* Invalidate the page cache, if we write to the cached page */
2704 if (page == chip->pagebuf)
2707 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2709 if (ops->mode == MTD_OPS_RAW)
2710 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2712 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2714 chip->select_chip(mtd, -1);
2719 ops->oobretlen = ops->ooblen;
2725 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2726 * @mtd: MTD device structure
2727 * @to: offset to write to
2728 * @ops: oob operation description structure
2730 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2731 struct mtd_oob_ops *ops)
2733 int ret = -ENOTSUPP;
2737 /* Do not allow writes past end of device */
2738 if (ops->datbuf && (to + ops->len) > mtd->size) {
2739 pr_debug("%s: attempt to write beyond end of device\n",
2744 nand_get_device(mtd, FL_WRITING);
2746 switch (ops->mode) {
2747 case MTD_OPS_PLACE_OOB:
2748 case MTD_OPS_AUTO_OOB:
2757 ret = nand_do_write_oob(mtd, to, ops);
2759 ret = nand_do_write_ops(mtd, to, ops);
2762 nand_release_device(mtd);
2767 * single_erase_cmd - [GENERIC] NAND standard block erase command function
2768 * @mtd: MTD device structure
2769 * @page: the page address of the block which will be erased
2771 * Standard erase command for NAND chips.
2773 static void single_erase_cmd(struct mtd_info *mtd, int page)
2775 struct nand_chip *chip = mtd->priv;
2776 /* Send commands to erase a block */
2777 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2778 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2782 * nand_erase - [MTD Interface] erase block(s)
2783 * @mtd: MTD device structure
2784 * @instr: erase instruction
2786 * Erase one ore more blocks.
2788 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2790 return nand_erase_nand(mtd, instr, 0);
2794 * nand_erase_nand - [INTERN] erase block(s)
2795 * @mtd: MTD device structure
2796 * @instr: erase instruction
2797 * @allowbbt: allow erasing the bbt area
2799 * Erase one ore more blocks.
2801 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2804 int page, status, pages_per_block, ret, chipnr;
2805 struct nand_chip *chip = mtd->priv;
2808 pr_debug("%s: start = 0x%012llx, len = %llu\n",
2809 __func__, (unsigned long long)instr->addr,
2810 (unsigned long long)instr->len);
2812 if (check_offs_len(mtd, instr->addr, instr->len))
2815 /* Grab the lock and see if the device is available */
2816 nand_get_device(mtd, FL_ERASING);
2818 /* Shift to get first page */
2819 page = (int)(instr->addr >> chip->page_shift);
2820 chipnr = (int)(instr->addr >> chip->chip_shift);
2822 /* Calculate pages in each block */
2823 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2825 /* Select the NAND device */
2826 chip->select_chip(mtd, chipnr);
2828 /* Check, if it is write protected */
2829 if (nand_check_wp(mtd)) {
2830 pr_debug("%s: device is write protected!\n",
2832 instr->state = MTD_ERASE_FAILED;
2836 /* Loop through the pages */
2839 instr->state = MTD_ERASING;
2844 /* Check if we have a bad block, we do not erase bad blocks! */
2845 if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
2846 chip->page_shift, 0, allowbbt)) {
2847 pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2849 instr->state = MTD_ERASE_FAILED;
2854 * Invalidate the page cache, if we erase the block which
2855 * contains the current cached page.
2857 if (page <= chip->pagebuf && chip->pagebuf <
2858 (page + pages_per_block))
2861 chip->erase_cmd(mtd, page & chip->pagemask);
2863 status = chip->waitfunc(mtd, chip);
2866 * See if operation failed and additional status checks are
2869 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2870 status = chip->errstat(mtd, chip, FL_ERASING,
2873 /* See if block erase succeeded */
2874 if (status & NAND_STATUS_FAIL) {
2875 pr_debug("%s: failed erase, page 0x%08x\n",
2877 instr->state = MTD_ERASE_FAILED;
2879 ((loff_t)page << chip->page_shift);
2883 /* Increment page address and decrement length */
2884 len -= (1ULL << chip->phys_erase_shift);
2885 page += pages_per_block;
2887 /* Check, if we cross a chip boundary */
2888 if (len && !(page & chip->pagemask)) {
2890 chip->select_chip(mtd, -1);
2891 chip->select_chip(mtd, chipnr);
2894 instr->state = MTD_ERASE_DONE;
2898 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2900 /* Deselect and wake up anyone waiting on the device */
2901 chip->select_chip(mtd, -1);
2902 nand_release_device(mtd);
2904 /* Do call back function */
2906 mtd_erase_callback(instr);
2908 /* Return more or less happy */
2913 * nand_sync - [MTD Interface] sync
2914 * @mtd: MTD device structure
2916 * Sync is actually a wait for chip ready function.
2918 static void nand_sync(struct mtd_info *mtd)
2920 pr_debug("%s: called\n", __func__);
2922 /* Grab the lock and see if the device is available */
2923 nand_get_device(mtd, FL_SYNCING);
2924 /* Release it and go back */
2925 nand_release_device(mtd);
2929 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2930 * @mtd: MTD device structure
2931 * @offs: offset relative to mtd start
2933 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2935 return nand_block_checkbad(mtd, offs, 1, 0);
2939 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2940 * @mtd: MTD device structure
2941 * @ofs: offset relative to mtd start
2943 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2947 ret = nand_block_isbad(mtd, ofs);
2949 /* If it was bad already, return success and do nothing */
2955 return nand_block_markbad_lowlevel(mtd, ofs);
2959 * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2960 * @mtd: MTD device structure
2961 * @chip: nand chip info structure
2962 * @addr: feature address.
2963 * @subfeature_param: the subfeature parameters, a four bytes array.
2965 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2966 int addr, uint8_t *subfeature_param)
2971 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
2972 if (!chip->onfi_version ||
2973 !(le16_to_cpu(chip->onfi_params.opt_cmd)
2974 & ONFI_OPT_CMD_SET_GET_FEATURES))
2978 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2979 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
2980 chip->write_byte(mtd, subfeature_param[i]);
2982 status = chip->waitfunc(mtd, chip);
2983 if (status & NAND_STATUS_FAIL)
2989 * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2990 * @mtd: MTD device structure
2991 * @chip: nand chip info structure
2992 * @addr: feature address.
2993 * @subfeature_param: the subfeature parameters, a four bytes array.
2995 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2996 int addr, uint8_t *subfeature_param)
3000 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3001 if (!chip->onfi_version ||
3002 !(le16_to_cpu(chip->onfi_params.opt_cmd)
3003 & ONFI_OPT_CMD_SET_GET_FEATURES))
3007 /* clear the sub feature parameters */
3008 memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
3010 chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
3011 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
3012 *subfeature_param++ = chip->read_byte(mtd);
3018 * nand_suspend - [MTD Interface] Suspend the NAND flash
3019 * @mtd: MTD device structure
3021 static int nand_suspend(struct mtd_info *mtd)
3023 return nand_get_device(mtd, FL_PM_SUSPENDED);
3027 * nand_resume - [MTD Interface] Resume the NAND flash
3028 * @mtd: MTD device structure
3030 static void nand_resume(struct mtd_info *mtd)
3032 struct nand_chip *chip = mtd->priv;
3034 if (chip->state == FL_PM_SUSPENDED)
3035 nand_release_device(mtd);
3037 pr_err("%s called for a chip which is not in suspended state\n",
3042 /* Set default functions */
3043 static void nand_set_defaults(struct nand_chip *chip, int busw)
3045 /* check for proper chip_delay setup, set 20us if not */
3046 if (!chip->chip_delay)
3047 chip->chip_delay = 20;
3049 /* check, if a user supplied command function given */
3050 if (chip->cmdfunc == NULL)
3051 chip->cmdfunc = nand_command;
3053 /* check, if a user supplied wait function given */
3054 if (chip->waitfunc == NULL)
3055 chip->waitfunc = nand_wait;
3057 if (!chip->select_chip)
3058 chip->select_chip = nand_select_chip;
3060 /* set for ONFI nand */
3061 if (!chip->onfi_set_features)
3062 chip->onfi_set_features = nand_onfi_set_features;
3063 if (!chip->onfi_get_features)
3064 chip->onfi_get_features = nand_onfi_get_features;
3066 /* If called twice, pointers that depend on busw may need to be reset */
3067 if (!chip->read_byte || chip->read_byte == nand_read_byte)
3068 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
3069 if (!chip->read_word)
3070 chip->read_word = nand_read_word;
3071 if (!chip->block_bad)
3072 chip->block_bad = nand_block_bad;
3073 if (!chip->block_markbad)
3074 chip->block_markbad = nand_default_block_markbad;
3075 if (!chip->write_buf || chip->write_buf == nand_write_buf)
3076 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
3077 if (!chip->write_byte || chip->write_byte == nand_write_byte)
3078 chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
3079 if (!chip->read_buf || chip->read_buf == nand_read_buf)
3080 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
3081 if (!chip->scan_bbt)
3082 chip->scan_bbt = nand_default_bbt;
3084 if (!chip->controller) {
3085 chip->controller = &chip->hwcontrol;
3086 spin_lock_init(&chip->controller->lock);
3087 init_waitqueue_head(&chip->controller->wq);
3092 /* Sanitize ONFI strings so we can safely print them */
3094 static void sanitize_string(uint8_t *s, size_t len)
3096 static void sanitize_string(char *s, size_t len)
3101 /* Null terminate */
3104 /* Remove non printable chars */
3105 for (i = 0; i < len - 1; i++) {
3106 if (s[i] < ' ' || s[i] > 127)
3110 /* Remove trailing spaces */
3114 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
3119 for (i = 0; i < 8; i++)
3120 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
3126 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3127 /* Parse the Extended Parameter Page. */
3128 static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
3129 struct nand_chip *chip, struct nand_onfi_params *p)
3131 struct onfi_ext_param_page *ep;
3132 struct onfi_ext_section *s;
3133 struct onfi_ext_ecc_info *ecc;
3139 len = le16_to_cpu(p->ext_param_page_length) * 16;
3140 ep = kmalloc(len, GFP_KERNEL);
3144 /* Send our own NAND_CMD_PARAM. */
3145 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3147 /* Use the Change Read Column command to skip the ONFI param pages. */
3148 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
3149 sizeof(*p) * p->num_of_param_pages , -1);
3151 /* Read out the Extended Parameter Page. */
3152 chip->read_buf(mtd, (uint8_t *)ep, len);
3153 if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
3154 != le16_to_cpu(ep->crc))) {
3155 pr_debug("fail in the CRC.\n");
3160 * Check the signature.
3161 * Do not strictly follow the ONFI spec, maybe changed in future.
3164 if (strncmp(ep->sig, "EPPS", 4)) {
3166 if (strncmp((char *)ep->sig, "EPPS", 4)) {
3168 pr_debug("The signature is invalid.\n");
3172 /* find the ECC section. */
3173 cursor = (uint8_t *)(ep + 1);
3174 for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
3175 s = ep->sections + i;
3176 if (s->type == ONFI_SECTION_TYPE_2)
3178 cursor += s->length * 16;
3180 if (i == ONFI_EXT_SECTION_MAX) {
3181 pr_debug("We can not find the ECC section.\n");
3185 /* get the info we want. */
3186 ecc = (struct onfi_ext_ecc_info *)cursor;
3188 if (!ecc->codeword_size) {
3189 pr_debug("Invalid codeword size\n");
3193 chip->ecc_strength_ds = ecc->ecc_bits;
3194 chip->ecc_step_ds = 1 << ecc->codeword_size;
3202 static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
3204 struct nand_chip *chip = mtd->priv;
3205 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
3207 return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
3212 * Configure chip properties from Micron vendor-specific ONFI table
3214 static void nand_onfi_detect_micron(struct nand_chip *chip,
3215 struct nand_onfi_params *p)
3217 struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
3219 if (le16_to_cpu(p->vendor_revision) < 1)
3222 chip->read_retries = micron->read_retry_options;
3223 chip->setup_read_retry = nand_setup_read_retry_micron;
3227 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
3229 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3232 struct nand_onfi_params *p = &chip->onfi_params;
3236 /* Try ONFI for unknown chip or LP */
3237 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
3238 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
3239 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
3242 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
3243 for (i = 0; i < 3; i++) {
3244 for (j = 0; j < sizeof(*p); j++)
3245 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3246 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
3247 le16_to_cpu(p->crc)) {
3253 pr_err("Could not find valid ONFI parameter page; aborting\n");
3258 val = le16_to_cpu(p->revision);
3260 chip->onfi_version = 23;
3261 else if (val & (1 << 4))
3262 chip->onfi_version = 22;
3263 else if (val & (1 << 3))
3264 chip->onfi_version = 21;
3265 else if (val & (1 << 2))
3266 chip->onfi_version = 20;
3267 else if (val & (1 << 1))
3268 chip->onfi_version = 10;
3270 if (!chip->onfi_version) {
3271 pr_info("unsupported ONFI version: %d\n", val);
3275 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3276 sanitize_string(p->model, sizeof(p->model));
3278 mtd->name = p->model;
3280 mtd->writesize = le32_to_cpu(p->byte_per_page);
3283 * pages_per_block and blocks_per_lun may not be a power-of-2 size
3284 * (don't ask me who thought of this...). MTD assumes that these
3285 * dimensions will be power-of-2, so just truncate the remaining area.
3287 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3288 mtd->erasesize *= mtd->writesize;
3290 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3292 /* See erasesize comment */
3293 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3294 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3295 chip->bits_per_cell = p->bits_per_cell;
3297 if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
3298 *busw = NAND_BUSWIDTH_16;
3302 if (p->ecc_bits != 0xff) {
3303 chip->ecc_strength_ds = p->ecc_bits;
3304 chip->ecc_step_ds = 512;
3305 } else if (chip->onfi_version >= 21 &&
3306 (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
3309 * The nand_flash_detect_ext_param_page() uses the
3310 * Change Read Column command which maybe not supported
3311 * by the chip->cmdfunc. So try to update the chip->cmdfunc
3312 * now. We do not replace user supplied command function.
3314 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3315 chip->cmdfunc = nand_command_lp;
3317 /* The Extended Parameter Page is supported since ONFI 2.1. */
3318 if (nand_flash_detect_ext_param_page(mtd, chip, p))
3319 pr_warn("Failed to detect ONFI extended param page\n");
3321 pr_warn("Could not retrieve ONFI ECC requirements\n");
3324 if (p->jedec_id == NAND_MFR_MICRON)
3325 nand_onfi_detect_micron(chip, p);
3330 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
3338 * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
3340 static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
3343 struct nand_jedec_params *p = &chip->jedec_params;
3344 struct jedec_ecc_info *ecc;
3348 /* Try JEDEC for unknown chip or LP */
3349 chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
3350 if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
3351 chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
3352 chip->read_byte(mtd) != 'C')
3355 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
3356 for (i = 0; i < 3; i++) {
3357 for (j = 0; j < sizeof(*p); j++)
3358 ((uint8_t *)p)[j] = chip->read_byte(mtd);
3360 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
3361 le16_to_cpu(p->crc))
3366 pr_err("Could not find valid JEDEC parameter page; aborting\n");
3371 val = le16_to_cpu(p->revision);
3373 chip->jedec_version = 10;
3374 else if (val & (1 << 1))
3375 chip->jedec_version = 1; /* vendor specific version */
3377 if (!chip->jedec_version) {
3378 pr_info("unsupported JEDEC version: %d\n", val);
3382 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
3383 sanitize_string(p->model, sizeof(p->model));
3385 mtd->name = p->model;
3387 mtd->writesize = le32_to_cpu(p->byte_per_page);
3389 /* Please reference to the comment for nand_flash_detect_onfi. */
3390 mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
3391 mtd->erasesize *= mtd->writesize;
3393 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
3395 /* Please reference to the comment for nand_flash_detect_onfi. */
3396 chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
3397 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
3398 chip->bits_per_cell = p->bits_per_cell;
3400 if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
3401 *busw = NAND_BUSWIDTH_16;
3406 ecc = &p->ecc_info[0];
3408 if (ecc->codeword_size >= 9) {
3409 chip->ecc_strength_ds = ecc->ecc_bits;
3410 chip->ecc_step_ds = 1 << ecc->codeword_size;
3412 pr_warn("Invalid codeword size\n");
3419 * nand_id_has_period - Check if an ID string has a given wraparound period
3420 * @id_data: the ID string
3421 * @arrlen: the length of the @id_data array
3422 * @period: the period of repitition
3424 * Check if an ID string is repeated within a given sequence of bytes at
3425 * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
3426 * period of 3). This is a helper function for nand_id_len(). Returns non-zero
3427 * if the repetition has a period of @period; otherwise, returns zero.
3429 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
3432 for (i = 0; i < period; i++)
3433 for (j = i + period; j < arrlen; j += period)
3434 if (id_data[i] != id_data[j])
3440 * nand_id_len - Get the length of an ID string returned by CMD_READID
3441 * @id_data: the ID string
3442 * @arrlen: the length of the @id_data array
3444 * Returns the length of the ID string, according to known wraparound/trailing
3445 * zero patterns. If no pattern exists, returns the length of the array.
3447 static int nand_id_len(u8 *id_data, int arrlen)
3449 int last_nonzero, period;
3451 /* Find last non-zero byte */
3452 for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
3453 if (id_data[last_nonzero])
3457 if (last_nonzero < 0)
3460 /* Calculate wraparound period */
3461 for (period = 1; period < arrlen; period++)
3462 if (nand_id_has_period(id_data, arrlen, period))
3465 /* There's a repeated pattern */
3466 if (period < arrlen)
3469 /* There are trailing zeros */
3470 if (last_nonzero < arrlen - 1)
3471 return last_nonzero + 1;
3473 /* No pattern detected */
3477 /* Extract the bits of per cell from the 3rd byte of the extended ID */
3478 static int nand_get_bits_per_cell(u8 cellinfo)
3482 bits = cellinfo & NAND_CI_CELLTYPE_MSK;
3483 bits >>= NAND_CI_CELLTYPE_SHIFT;
3488 * Many new NAND share similar device ID codes, which represent the size of the
3489 * chip. The rest of the parameters must be decoded according to generic or
3490 * manufacturer-specific "extended ID" decoding patterns.
3492 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
3493 u8 id_data[8], int *busw)
3496 /* The 3rd id byte holds MLC / multichip data */
3497 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3498 /* The 4th id byte is the important one */
3501 id_len = nand_id_len(id_data, 8);
3504 * Field definitions are in the following datasheets:
3505 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3506 * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
3507 * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
3509 * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
3510 * ID to decide what to do.
3512 if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
3513 !nand_is_slc(chip) && id_data[5] != 0x00) {
3515 mtd->writesize = 2048 << (extid & 0x03);
3518 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3538 default: /* Other cases are "reserved" (unknown) */
3539 mtd->oobsize = 1024;
3543 /* Calc blocksize */
3544 mtd->erasesize = (128 * 1024) <<
3545 (((extid >> 1) & 0x04) | (extid & 0x03));
3547 } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3548 !nand_is_slc(chip)) {
3552 mtd->writesize = 2048 << (extid & 0x03);
3555 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3579 /* Calc blocksize */
3580 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3582 mtd->erasesize = (128 * 1024) << tmp;
3583 else if (tmp == 0x03)
3584 mtd->erasesize = 768 * 1024;
3586 mtd->erasesize = (64 * 1024) << tmp;
3590 mtd->writesize = 1024 << (extid & 0x03);
3593 mtd->oobsize = (8 << (extid & 0x01)) *
3594 (mtd->writesize >> 9);
3596 /* Calc blocksize. Blocksize is multiples of 64KiB */
3597 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3599 /* Get buswidth information */
3600 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3603 * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
3604 * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
3606 * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
3608 * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
3610 if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
3611 nand_is_slc(chip) &&
3612 (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
3613 !(id_data[4] & 0x80) /* !BENAND */) {
3614 mtd->oobsize = 32 * mtd->writesize >> 9;
3621 * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3622 * decodes a matching ID table entry and assigns the MTD size parameters for
3625 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3626 struct nand_flash_dev *type, u8 id_data[8],
3629 int maf_id = id_data[0];
3631 mtd->erasesize = type->erasesize;
3632 mtd->writesize = type->pagesize;
3633 mtd->oobsize = mtd->writesize / 32;
3634 *busw = type->options & NAND_BUSWIDTH_16;
3636 /* All legacy ID NAND are small-page, SLC */
3637 chip->bits_per_cell = 1;
3640 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3641 * some Spansion chips have erasesize that conflicts with size
3642 * listed in nand_ids table.
3643 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3645 if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3646 && id_data[6] == 0x00 && id_data[7] == 0x00
3647 && mtd->writesize == 512) {
3648 mtd->erasesize = 128 * 1024;
3649 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3654 * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3655 * heuristic patterns using various detected parameters (e.g., manufacturer,
3656 * page size, cell-type information).
3658 static void nand_decode_bbm_options(struct mtd_info *mtd,
3659 struct nand_chip *chip, u8 id_data[8])
3661 int maf_id = id_data[0];
3663 /* Set the bad block position */
3664 if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3665 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3667 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3670 * Bad block marker is stored in the last page of each block on Samsung
3671 * and Hynix MLC devices; stored in first two pages of each block on
3672 * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3673 * AMD/Spansion, and Macronix. All others scan only the first page.
3675 if (!nand_is_slc(chip) &&
3676 (maf_id == NAND_MFR_SAMSUNG ||
3677 maf_id == NAND_MFR_HYNIX))
3678 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3679 else if ((nand_is_slc(chip) &&
3680 (maf_id == NAND_MFR_SAMSUNG ||
3681 maf_id == NAND_MFR_HYNIX ||
3682 maf_id == NAND_MFR_TOSHIBA ||
3683 maf_id == NAND_MFR_AMD ||
3684 maf_id == NAND_MFR_MACRONIX)) ||
3685 (mtd->writesize == 2048 &&
3686 maf_id == NAND_MFR_MICRON))
3687 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3690 static inline bool is_full_id_nand(struct nand_flash_dev *type)
3692 return type->id_len;
3695 static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
3696 struct nand_flash_dev *type, u8 *id_data, int *busw)
3699 if (!strncmp(type->id, id_data, type->id_len)) {
3701 if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
3703 mtd->writesize = type->pagesize;
3704 mtd->erasesize = type->erasesize;
3705 mtd->oobsize = type->oobsize;
3707 chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
3708 chip->chipsize = (uint64_t)type->chipsize << 20;
3709 chip->options |= type->options;
3710 chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
3711 chip->ecc_step_ds = NAND_ECC_STEP(type);
3713 *busw = type->options & NAND_BUSWIDTH_16;
3716 mtd->name = type->name;
3724 * Get the flash and manufacturer id and lookup if the type is supported.
3726 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3727 struct nand_chip *chip,
3728 int *maf_id, int *dev_id,
3729 struct nand_flash_dev *type)
3735 /* Select the device */
3736 chip->select_chip(mtd, 0);
3739 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3742 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3744 /* Send the command for reading device ID */
3745 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3747 /* Read manufacturer and device IDs */
3748 *maf_id = chip->read_byte(mtd);
3749 *dev_id = chip->read_byte(mtd);
3752 * Try again to make sure, as some systems the bus-hold or other
3753 * interface concerns can cause random data which looks like a
3754 * possibly credible NAND flash to appear. If the two results do
3755 * not match, ignore the device completely.
3758 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3760 /* Read entire ID string */
3761 for (i = 0; i < 8; i++)
3762 id_data[i] = chip->read_byte(mtd);
3764 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3765 pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
3766 *maf_id, *dev_id, id_data[0], id_data[1]);
3767 return ERR_PTR(-ENODEV);
3771 type = nand_flash_ids;
3773 for (; type->name != NULL; type++) {
3774 if (is_full_id_nand(type)) {
3775 if (find_full_id_nand(mtd, chip, type, id_data, &busw))
3777 } else if (*dev_id == type->dev_id) {
3782 chip->onfi_version = 0;
3783 if (!type->name || !type->pagesize) {
3784 /* Check is chip is ONFI compliant */
3785 if (nand_flash_detect_onfi(mtd, chip, &busw))
3788 /* Check if the chip is JEDEC compliant */
3789 if (nand_flash_detect_jedec(mtd, chip, &busw))
3794 return ERR_PTR(-ENODEV);
3797 mtd->name = type->name;
3799 chip->chipsize = (uint64_t)type->chipsize << 20;
3801 if (!type->pagesize && chip->init_size) {
3802 /* Set the pagesize, oobsize, erasesize by the driver */
3803 busw = chip->init_size(mtd, chip, id_data);
3804 } else if (!type->pagesize) {
3805 /* Decode parameters from extended ID */
3806 nand_decode_ext_id(mtd, chip, id_data, &busw);
3808 nand_decode_id(mtd, chip, type, id_data, &busw);
3810 /* Get chip options */
3811 chip->options |= type->options;
3814 * Check if chip is not a Samsung device. Do not clear the
3815 * options for chips which do not have an extended id.
3817 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3818 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3821 /* Try to identify manufacturer */
3822 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3823 if (nand_manuf_ids[maf_idx].id == *maf_id)
3827 if (chip->options & NAND_BUSWIDTH_AUTO) {
3828 WARN_ON(chip->options & NAND_BUSWIDTH_16);
3829 chip->options |= busw;
3830 nand_set_defaults(chip, busw);
3831 } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3833 * Check, if buswidth is correct. Hardware drivers should set
3836 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3838 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
3839 pr_warn("bus width %d instead %d bit\n",
3840 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3842 return ERR_PTR(-EINVAL);
3845 nand_decode_bbm_options(mtd, chip, id_data);
3847 /* Calculate the address shift from the page size */
3848 chip->page_shift = ffs(mtd->writesize) - 1;
3849 /* Convert chipsize to number of pages per chip -1 */
3850 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3852 chip->bbt_erase_shift = chip->phys_erase_shift =
3853 ffs(mtd->erasesize) - 1;
3854 if (chip->chipsize & 0xffffffff)
3855 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3857 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3858 chip->chip_shift += 32 - 1;
3861 chip->badblockbits = 8;
3862 chip->erase_cmd = single_erase_cmd;
3864 /* Do not replace user supplied command function! */
3865 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3866 chip->cmdfunc = nand_command_lp;
3868 pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
3871 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
3872 if (chip->onfi_version)
3873 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3874 chip->onfi_params.model);
3875 else if (chip->jedec_version)
3876 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3877 chip->jedec_params.model);
3879 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3882 if (chip->jedec_version)
3883 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3884 chip->jedec_params.model);
3886 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3889 pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
3893 pr_info("%dMiB, %s, page size: %d, OOB size: %d\n",
3894 (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
3895 mtd->writesize, mtd->oobsize);
3900 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3901 * @mtd: MTD device structure
3902 * @maxchips: number of chips to scan for
3903 * @table: alternative NAND ID table
3905 * This is the first phase of the normal nand_scan() function. It reads the
3906 * flash ID and sets up MTD fields accordingly.
3908 * The mtd->owner field must be set to the module of the caller.
3910 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3911 struct nand_flash_dev *table)
3913 int i, nand_maf_id, nand_dev_id;
3914 struct nand_chip *chip = mtd->priv;
3915 struct nand_flash_dev *type;
3917 /* Set the default functions */
3918 nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
3920 /* Read the flash type */
3921 type = nand_get_flash_type(mtd, chip, &nand_maf_id,
3922 &nand_dev_id, table);
3925 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3926 pr_warn("No NAND device found\n");
3927 chip->select_chip(mtd, -1);
3928 return PTR_ERR(type);
3931 chip->select_chip(mtd, -1);
3933 /* Check for a chip array */
3934 for (i = 1; i < maxchips; i++) {
3935 chip->select_chip(mtd, i);
3936 /* See comment in nand_get_flash_type for reset */
3937 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3938 /* Send the command for reading device ID */
3939 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3940 /* Read manufacturer and device IDs */
3941 if (nand_maf_id != chip->read_byte(mtd) ||
3942 nand_dev_id != chip->read_byte(mtd)) {
3943 chip->select_chip(mtd, -1);
3946 chip->select_chip(mtd, -1);
3951 pr_info("%d chips detected\n", i);
3954 /* Store the number of chips and calc total size for mtd */
3956 mtd->size = i * chip->chipsize;
3960 EXPORT_SYMBOL(nand_scan_ident);
3964 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3965 * @mtd: MTD device structure
3967 * This is the second phase of the normal nand_scan() function. It fills out
3968 * all the uninitialized function pointers with the defaults and scans for a
3969 * bad block table if appropriate.
3971 int nand_scan_tail(struct mtd_info *mtd)
3974 struct nand_chip *chip = mtd->priv;
3975 struct nand_ecc_ctrl *ecc = &chip->ecc;
3976 struct nand_buffers *nbuf;
3978 /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3979 BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3980 !(chip->bbt_options & NAND_BBT_USE_FLASH));
3982 if (!(chip->options & NAND_OWN_BUFFERS)) {
3984 nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize
3985 + mtd->oobsize * 3, GFP_KERNEL);
3988 nbuf->ecccalc = (uint8_t *)(nbuf + 1);
3989 nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
3990 nbuf->databuf = nbuf->ecccode + mtd->oobsize;
3992 nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
3995 chip->buffers = nbuf;
4001 /* Set the internal oob buffer location, just after the page data */
4002 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
4005 * If no default placement scheme is given, select an appropriate one.
4007 if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
4008 switch (mtd->oobsize) {
4010 ecc->layout = &nand_oob_8;
4013 ecc->layout = &nand_oob_16;
4016 ecc->layout = &nand_oob_64;
4019 ecc->layout = &nand_oob_128;
4022 pr_warn("No oob scheme defined for oobsize %d\n",
4028 if (!chip->write_page)
4029 chip->write_page = nand_write_page;
4032 * Check ECC mode, default to software if 3byte/512byte hardware ECC is
4033 * selected and we have 256 byte pagesize fallback to software ECC
4036 switch (ecc->mode) {
4037 case NAND_ECC_HW_OOB_FIRST:
4038 /* Similar to NAND_ECC_HW, but a separate read_page handle */
4039 if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
4040 pr_warn("No ECC functions supplied; "
4041 "hardware ECC not possible\n");
4044 if (!ecc->read_page)
4045 ecc->read_page = nand_read_page_hwecc_oob_first;
4048 /* Use standard hwecc read page function? */
4049 if (!ecc->read_page)
4050 ecc->read_page = nand_read_page_hwecc;
4051 if (!ecc->write_page)
4052 ecc->write_page = nand_write_page_hwecc;
4053 if (!ecc->read_page_raw)
4054 ecc->read_page_raw = nand_read_page_raw;
4055 if (!ecc->write_page_raw)
4056 ecc->write_page_raw = nand_write_page_raw;
4058 ecc->read_oob = nand_read_oob_std;
4059 if (!ecc->write_oob)
4060 ecc->write_oob = nand_write_oob_std;
4061 if (!ecc->read_subpage)
4062 ecc->read_subpage = nand_read_subpage;
4063 if (!ecc->write_subpage)
4064 ecc->write_subpage = nand_write_subpage_hwecc;
4066 case NAND_ECC_HW_SYNDROME:
4067 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
4069 ecc->read_page == nand_read_page_hwecc ||
4071 ecc->write_page == nand_write_page_hwecc)) {
4072 pr_warn("No ECC functions supplied; "
4073 "hardware ECC not possible\n");
4076 /* Use standard syndrome read/write page function? */
4077 if (!ecc->read_page)
4078 ecc->read_page = nand_read_page_syndrome;
4079 if (!ecc->write_page)
4080 ecc->write_page = nand_write_page_syndrome;
4081 if (!ecc->read_page_raw)
4082 ecc->read_page_raw = nand_read_page_raw_syndrome;
4083 if (!ecc->write_page_raw)
4084 ecc->write_page_raw = nand_write_page_raw_syndrome;
4086 ecc->read_oob = nand_read_oob_syndrome;
4087 if (!ecc->write_oob)
4088 ecc->write_oob = nand_write_oob_syndrome;
4090 if (mtd->writesize >= ecc->size) {
4091 if (!ecc->strength) {
4092 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
4097 pr_warn("%d byte HW ECC not possible on "
4098 "%d byte page size, fallback to SW ECC\n",
4099 ecc->size, mtd->writesize);
4100 ecc->mode = NAND_ECC_SOFT;
4103 ecc->calculate = nand_calculate_ecc;
4104 ecc->correct = nand_correct_data;
4105 ecc->read_page = nand_read_page_swecc;
4106 ecc->read_subpage = nand_read_subpage;
4107 ecc->write_page = nand_write_page_swecc;
4108 ecc->read_page_raw = nand_read_page_raw;
4109 ecc->write_page_raw = nand_write_page_raw;
4110 ecc->read_oob = nand_read_oob_std;
4111 ecc->write_oob = nand_write_oob_std;
4118 case NAND_ECC_SOFT_BCH:
4119 if (!mtd_nand_has_bch()) {
4120 pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
4123 ecc->calculate = nand_bch_calculate_ecc;
4124 ecc->correct = nand_bch_correct_data;
4125 ecc->read_page = nand_read_page_swecc;
4126 ecc->read_subpage = nand_read_subpage;
4127 ecc->write_page = nand_write_page_swecc;
4128 ecc->read_page_raw = nand_read_page_raw;
4129 ecc->write_page_raw = nand_write_page_raw;
4130 ecc->read_oob = nand_read_oob_std;
4131 ecc->write_oob = nand_write_oob_std;
4133 * Board driver should supply ecc.size and ecc.bytes values to
4134 * select how many bits are correctable; see nand_bch_init()
4135 * for details. Otherwise, default to 4 bits for large page
4138 if (!ecc->size && (mtd->oobsize >= 64)) {
4142 ecc->priv = nand_bch_init(mtd, ecc->size, ecc->bytes,
4145 pr_warn("BCH ECC initialization failed!\n");
4148 ecc->strength = ecc->bytes * 8 / fls(8 * ecc->size);
4152 pr_warn("NAND_ECC_NONE selected by board driver. "
4153 "This is not recommended!\n");
4154 ecc->read_page = nand_read_page_raw;
4155 ecc->write_page = nand_write_page_raw;
4156 ecc->read_oob = nand_read_oob_std;
4157 ecc->read_page_raw = nand_read_page_raw;
4158 ecc->write_page_raw = nand_write_page_raw;
4159 ecc->write_oob = nand_write_oob_std;
4160 ecc->size = mtd->writesize;
4166 pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
4170 /* For many systems, the standard OOB write also works for raw */
4171 if (!ecc->read_oob_raw)
4172 ecc->read_oob_raw = ecc->read_oob;
4173 if (!ecc->write_oob_raw)
4174 ecc->write_oob_raw = ecc->write_oob;
4177 * The number of bytes available for a client to place data into
4178 * the out of band area.
4180 ecc->layout->oobavail = 0;
4181 for (i = 0; ecc->layout->oobfree[i].length
4182 && i < ARRAY_SIZE(ecc->layout->oobfree); i++)
4183 ecc->layout->oobavail += ecc->layout->oobfree[i].length;
4184 mtd->oobavail = ecc->layout->oobavail;
4187 * Set the number of read / write steps for one page depending on ECC
4190 ecc->steps = mtd->writesize / ecc->size;
4191 if (ecc->steps * ecc->size != mtd->writesize) {
4192 pr_warn("Invalid ECC parameters\n");
4195 ecc->total = ecc->steps * ecc->bytes;
4197 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
4198 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
4199 switch (ecc->steps) {
4201 mtd->subpage_sft = 1;
4206 mtd->subpage_sft = 2;
4210 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
4212 /* Initialize state */
4213 chip->state = FL_READY;
4215 /* Invalidate the pagebuffer reference */
4218 /* Large page NAND with SOFT_ECC should support subpage reads */
4219 if ((ecc->mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
4220 chip->options |= NAND_SUBPAGE_READ;
4222 /* Fill in remaining MTD driver data */
4223 mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
4224 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
4226 mtd->_erase = nand_erase;
4229 mtd->_unpoint = NULL;
4231 mtd->_read = nand_read;
4232 mtd->_write = nand_write;
4233 mtd->_panic_write = panic_nand_write;
4234 mtd->_read_oob = nand_read_oob;
4235 mtd->_write_oob = nand_write_oob;
4236 mtd->_sync = nand_sync;
4238 mtd->_unlock = NULL;
4240 mtd->_suspend = nand_suspend;
4241 mtd->_resume = nand_resume;
4243 mtd->_block_isbad = nand_block_isbad;
4244 mtd->_block_markbad = nand_block_markbad;
4245 mtd->writebufsize = mtd->writesize;
4247 /* propagate ecc info to mtd_info */
4248 mtd->ecclayout = ecc->layout;
4249 mtd->ecc_strength = ecc->strength;
4250 mtd->ecc_step_size = ecc->size;
4252 * Initialize bitflip_threshold to its default prior scan_bbt() call.
4253 * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
4256 if (!mtd->bitflip_threshold)
4257 mtd->bitflip_threshold = mtd->ecc_strength;
4261 EXPORT_SYMBOL(nand_scan_tail);
4264 * is_module_text_address() isn't exported, and it's mostly a pointless
4265 * test if this is a module _anyway_ -- they'd have to try _really_ hard
4266 * to call us from in-kernel code if the core NAND support is modular.
4269 #define caller_is_module() (1)
4271 #define caller_is_module() \
4272 is_module_text_address((unsigned long)__builtin_return_address(0))
4276 * nand_scan - [NAND Interface] Scan for the NAND device
4277 * @mtd: MTD device structure
4278 * @maxchips: number of chips to scan for
4280 * This fills out all the uninitialized function pointers with the defaults.
4281 * The flash ID is read and the mtd/chip structures are filled with the
4282 * appropriate values. The mtd->owner field must be set to the module of the
4285 int nand_scan(struct mtd_info *mtd, int maxchips)
4289 /* Many callers got this wrong, so check for it for a while... */
4290 if (!mtd->owner && caller_is_module()) {
4291 pr_crit("%s called with NULL mtd->owner!\n", __func__);
4295 ret = nand_scan_ident(mtd, maxchips, NULL);
4297 ret = nand_scan_tail(mtd);
4300 EXPORT_SYMBOL(nand_scan);
4304 * nand_release - [NAND Interface] Free resources held by the NAND device
4305 * @mtd: MTD device structure
4307 void nand_release(struct mtd_info *mtd)
4309 struct nand_chip *chip = mtd->priv;
4311 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
4312 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
4314 mtd_device_unregister(mtd);
4316 /* Free bad block table memory */
4318 if (!(chip->options & NAND_OWN_BUFFERS))
4319 kfree(chip->buffers);
4321 /* Free bad block descriptor memory */
4322 if (chip->badblock_pattern && chip->badblock_pattern->options
4323 & NAND_BBT_DYNAMICSTRUCT)
4324 kfree(chip->badblock_pattern);
4326 EXPORT_SYMBOL_GPL(nand_release);
4328 static int __init nand_base_init(void)
4330 led_trigger_register_simple("nand-disk", &nand_led_trigger);
4334 static void __exit nand_base_exit(void)
4336 led_trigger_unregister_simple(nand_led_trigger);
4340 module_init(nand_base_init);
4341 module_exit(nand_base_exit);
4343 MODULE_LICENSE("GPL");
4344 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
4345 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
4346 MODULE_DESCRIPTION("Generic NAND flash driver code");