1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 NAND flash driver
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
8 * Based on code from LTIB:
9 * Freescale GPMI NFC NAND Flash Driver
11 * Copyright (C) 2010 Freescale Semiconductor, Inc.
12 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/types.h>
21 #include <linux/errno.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/imx-regs.h>
25 #include <asm/mach-imx/regs-bch.h>
26 #include <asm/mach-imx/regs-gpmi.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/mach-imx/dma.h>
31 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
33 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
34 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
36 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
38 #define MXS_NAND_METADATA_SIZE 10
39 #define MXS_NAND_BITS_PER_ECC_LEVEL 13
41 #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
42 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
44 #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
47 #define MXS_NAND_BCH_TIMEOUT 10000
50 * @gf_len: The length of Galois Field. (e.g., 13 or 14)
51 * @ecc_strength: A number that describes the strength of the ECC
53 * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
54 * the first chunk in the page includes both data and
55 * metadata, so it's a bit larger than this value.
56 * @ecc_chunk_count: The number of ECC chunks in the page,
57 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
58 * which the underlying physical block mark appears.
59 * @block_mark_bit_offset: The bit offset into the ECC-based page view at
60 * which the underlying physical block mark appears.
64 unsigned int ecc_strength;
65 unsigned int ecc_chunk_size;
66 unsigned int ecc_chunk_count;
67 unsigned int block_mark_byte_offset;
68 unsigned int block_mark_bit_offset;
71 struct mxs_nand_info {
72 struct nand_chip chip;
75 uint32_t cmd_queue_len;
76 uint32_t data_buf_size;
77 struct bch_geometry bch_geometry;
83 uint8_t marking_block_bad;
86 /* Functions with altered behaviour */
87 int (*hooked_read_oob)(struct mtd_info *mtd,
88 loff_t from, struct mtd_oob_ops *ops);
89 int (*hooked_write_oob)(struct mtd_info *mtd,
90 loff_t to, struct mtd_oob_ops *ops);
91 int (*hooked_block_markbad)(struct mtd_info *mtd,
95 struct mxs_dma_desc **desc;
99 struct nand_ecclayout fake_ecc_layout;
102 * Cache management functions
104 #ifndef CONFIG_SYS_DCACHE_OFF
105 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
107 uint32_t addr = (uint32_t)info->data_buf;
109 flush_dcache_range(addr, addr + info->data_buf_size);
112 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
114 uint32_t addr = (uint32_t)info->data_buf;
116 invalidate_dcache_range(addr, addr + info->data_buf_size);
119 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
121 uint32_t addr = (uint32_t)info->cmd_buf;
123 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
126 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
127 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
128 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
131 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
133 struct mxs_dma_desc *desc;
135 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
136 printf("MXS NAND: Too many DMA descriptors requested\n");
140 desc = info->desc[info->desc_index];
146 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
149 struct mxs_dma_desc *desc;
151 for (i = 0; i < info->desc_index; i++) {
152 desc = info->desc[i];
153 memset(desc, 0, sizeof(struct mxs_dma_desc));
154 desc->address = (dma_addr_t)desc;
157 info->desc_index = 0;
160 static uint32_t mxs_nand_aux_status_offset(void)
162 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
165 static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo,
166 uint32_t page_data_size)
168 uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8;
169 uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len;
170 uint32_t chunk_total_size_in_bits;
171 uint32_t block_mark_chunk_number;
172 uint32_t block_mark_chunk_bit_offset;
173 uint32_t block_mark_bit_offset;
175 chunk_total_size_in_bits =
176 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
178 /* Compute the bit offset of the block mark within the physical page. */
179 block_mark_bit_offset = page_data_size * 8;
181 /* Subtract the metadata bits. */
182 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
185 * Compute the chunk number (starting at zero) in which the block mark
188 block_mark_chunk_number =
189 block_mark_bit_offset / chunk_total_size_in_bits;
192 * Compute the bit offset of the block mark within its chunk, and
195 block_mark_chunk_bit_offset = block_mark_bit_offset -
196 (block_mark_chunk_number * chunk_total_size_in_bits);
198 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
202 * Now that we know the chunk number in which the block mark appears,
203 * we can subtract all the ECC bits that appear before it.
205 block_mark_bit_offset -=
206 block_mark_chunk_number * chunk_ecc_size_in_bits;
208 geo->block_mark_byte_offset = block_mark_bit_offset >> 3;
209 geo->block_mark_bit_offset = block_mark_bit_offset & 0x7;
214 static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo,
215 struct mtd_info *mtd)
217 unsigned int max_ecc_strength_supported;
219 /* The default for the length of Galois Field. */
222 /* The default for chunk size. */
223 geo->ecc_chunk_size = 512;
225 if (geo->ecc_chunk_size < mtd->oobsize) {
227 geo->ecc_chunk_size *= 2;
230 if (mtd->oobsize > geo->ecc_chunk_size) {
231 printf("Not support the NAND chips whose oob size is larger then %d bytes!\n",
232 geo->ecc_chunk_size);
236 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
238 /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
239 if (is_mx6sx() || is_mx7())
240 max_ecc_strength_supported = 62;
242 max_ecc_strength_supported = 40;
245 * Determine the ECC layout with the formula:
246 * ECC bits per chunk = (total page spare data bits) /
247 * (bits per ECC level) / (chunks per page)
249 * total page spare data bits =
250 * (page oob size - meta data size) * (bits per byte)
252 geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
253 / (geo->gf_len * geo->ecc_chunk_count);
255 geo->ecc_strength = min(round_down(geo->ecc_strength, 2), max_ecc_strength_supported);
257 if (mxs_nand_calc_mark_offset(geo, mtd->writesize) < 0)
264 * Wait for BCH complete IRQ and clear the IRQ
266 static int mxs_nand_wait_for_bch_complete(void)
268 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
269 int timeout = MXS_NAND_BCH_TIMEOUT;
272 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
273 BCH_CTRL_COMPLETE_IRQ, timeout);
275 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
281 * This is the function that we install in the cmd_ctrl function pointer of the
282 * owning struct nand_chip. The only functions in the reference implementation
283 * that use these functions pointers are cmdfunc and select_chip.
285 * In this driver, we implement our own select_chip, so this function will only
286 * be called by the reference implementation's cmdfunc. For this reason, we can
287 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
290 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
292 struct nand_chip *nand = mtd_to_nand(mtd);
293 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
294 struct mxs_dma_desc *d;
295 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
299 * If this condition is true, something is _VERY_ wrong in MTD
302 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
303 printf("MXS NAND: Command queue too long\n");
308 * Every operation begins with a command byte and a series of zero or
309 * more address bytes. These are distinguished by either the Address
310 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
311 * asserted. When MTD is ready to execute the command, it will
312 * deasert both latch enables.
314 * Rather than run a separate DMA operation for every single byte, we
315 * queue them up and run a single DMA operation for the entire series
316 * of command and data bytes.
318 if (ctrl & (NAND_ALE | NAND_CLE)) {
319 if (data != NAND_CMD_NONE)
320 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
325 * If control arrives here, MTD has deasserted both the ALE and CLE,
326 * which means it's ready to run an operation. Check if we have any
329 if (nand_info->cmd_queue_len == 0)
332 /* Compile the DMA descriptor -- a descriptor that sends command. */
333 d = mxs_nand_get_dma_desc(nand_info);
335 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
336 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
337 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
338 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
340 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
342 d->cmd.pio_words[0] =
343 GPMI_CTRL0_COMMAND_MODE_WRITE |
344 GPMI_CTRL0_WORD_LENGTH |
345 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
346 GPMI_CTRL0_ADDRESS_NAND_CLE |
347 GPMI_CTRL0_ADDRESS_INCREMENT |
348 nand_info->cmd_queue_len;
350 mxs_dma_desc_append(channel, d);
353 mxs_nand_flush_cmd_buf(nand_info);
355 /* Execute the DMA chain. */
356 ret = mxs_dma_go(channel);
358 printf("MXS NAND: Error sending command\n");
360 mxs_nand_return_dma_descs(nand_info);
362 /* Reset the command queue. */
363 nand_info->cmd_queue_len = 0;
367 * Test if the NAND flash is ready.
369 static int mxs_nand_device_ready(struct mtd_info *mtd)
371 struct nand_chip *chip = mtd_to_nand(mtd);
372 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
373 struct mxs_gpmi_regs *gpmi_regs =
374 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
377 tmp = readl(&gpmi_regs->hw_gpmi_stat);
378 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
384 * Select the NAND chip.
386 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
388 struct nand_chip *nand = mtd_to_nand(mtd);
389 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
391 nand_info->cur_chip = chip;
395 * Handle block mark swapping.
397 * Note that, when this function is called, it doesn't know whether it's
398 * swapping the block mark, or swapping it *back* -- but it doesn't matter
399 * because the the operation is the same.
401 static void mxs_nand_swap_block_mark(struct bch_geometry *geo,
402 uint8_t *data_buf, uint8_t *oob_buf)
404 uint32_t bit_offset = geo->block_mark_bit_offset;
405 uint32_t buf_offset = geo->block_mark_byte_offset;
411 * Get the byte from the data area that overlays the block mark. Since
412 * the ECC engine applies its own view to the bits in the page, the
413 * physical block mark won't (in general) appear on a byte boundary in
416 src = data_buf[buf_offset] >> bit_offset;
417 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
423 data_buf[buf_offset] &= ~(0xff << bit_offset);
424 data_buf[buf_offset + 1] &= 0xff << bit_offset;
426 data_buf[buf_offset] |= dst << bit_offset;
427 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
431 * Read data from NAND.
433 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
435 struct nand_chip *nand = mtd_to_nand(mtd);
436 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
437 struct mxs_dma_desc *d;
438 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
441 if (length > NAND_MAX_PAGESIZE) {
442 printf("MXS NAND: DMA buffer too big\n");
447 printf("MXS NAND: DMA buffer is NULL\n");
451 /* Compile the DMA descriptor - a descriptor that reads data. */
452 d = mxs_nand_get_dma_desc(nand_info);
454 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
455 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
456 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
457 (length << MXS_DMA_DESC_BYTES_OFFSET);
459 d->cmd.address = (dma_addr_t)nand_info->data_buf;
461 d->cmd.pio_words[0] =
462 GPMI_CTRL0_COMMAND_MODE_READ |
463 GPMI_CTRL0_WORD_LENGTH |
464 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
465 GPMI_CTRL0_ADDRESS_NAND_DATA |
468 mxs_dma_desc_append(channel, d);
471 * A DMA descriptor that waits for the command to end and the chip to
474 * I think we actually should *not* be waiting for the chip to become
475 * ready because, after all, we don't care. I think the original code
476 * did that and no one has re-thought it yet.
478 d = mxs_nand_get_dma_desc(nand_info);
480 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
481 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
482 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
486 d->cmd.pio_words[0] =
487 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
488 GPMI_CTRL0_WORD_LENGTH |
489 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
490 GPMI_CTRL0_ADDRESS_NAND_DATA;
492 mxs_dma_desc_append(channel, d);
494 /* Invalidate caches */
495 mxs_nand_inval_data_buf(nand_info);
497 /* Execute the DMA chain. */
498 ret = mxs_dma_go(channel);
500 printf("MXS NAND: DMA read error\n");
504 /* Invalidate caches */
505 mxs_nand_inval_data_buf(nand_info);
507 memcpy(buf, nand_info->data_buf, length);
510 mxs_nand_return_dma_descs(nand_info);
514 * Write data to NAND.
516 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
519 struct nand_chip *nand = mtd_to_nand(mtd);
520 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
521 struct mxs_dma_desc *d;
522 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
525 if (length > NAND_MAX_PAGESIZE) {
526 printf("MXS NAND: DMA buffer too big\n");
531 printf("MXS NAND: DMA buffer is NULL\n");
535 memcpy(nand_info->data_buf, buf, length);
537 /* Compile the DMA descriptor - a descriptor that writes data. */
538 d = mxs_nand_get_dma_desc(nand_info);
540 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
541 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
542 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
543 (length << MXS_DMA_DESC_BYTES_OFFSET);
545 d->cmd.address = (dma_addr_t)nand_info->data_buf;
547 d->cmd.pio_words[0] =
548 GPMI_CTRL0_COMMAND_MODE_WRITE |
549 GPMI_CTRL0_WORD_LENGTH |
550 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
551 GPMI_CTRL0_ADDRESS_NAND_DATA |
554 mxs_dma_desc_append(channel, d);
557 mxs_nand_flush_data_buf(nand_info);
559 /* Execute the DMA chain. */
560 ret = mxs_dma_go(channel);
562 printf("MXS NAND: DMA write error\n");
564 mxs_nand_return_dma_descs(nand_info);
568 * Read a single byte from NAND.
570 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
573 mxs_nand_read_buf(mtd, &buf, 1);
578 * Read a page from NAND.
580 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
581 uint8_t *buf, int oob_required,
584 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
585 struct bch_geometry *geo = &nand_info->bch_geometry;
586 struct mxs_dma_desc *d;
587 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
588 uint32_t corrected = 0, failed = 0;
592 /* Compile the DMA descriptor - wait for ready. */
593 d = mxs_nand_get_dma_desc(nand_info);
595 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
596 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
597 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
601 d->cmd.pio_words[0] =
602 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
603 GPMI_CTRL0_WORD_LENGTH |
604 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
605 GPMI_CTRL0_ADDRESS_NAND_DATA;
607 mxs_dma_desc_append(channel, d);
609 /* Compile the DMA descriptor - enable the BCH block and read. */
610 d = mxs_nand_get_dma_desc(nand_info);
612 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
613 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
617 d->cmd.pio_words[0] =
618 GPMI_CTRL0_COMMAND_MODE_READ |
619 GPMI_CTRL0_WORD_LENGTH |
620 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
621 GPMI_CTRL0_ADDRESS_NAND_DATA |
622 (mtd->writesize + mtd->oobsize);
623 d->cmd.pio_words[1] = 0;
624 d->cmd.pio_words[2] =
625 GPMI_ECCCTRL_ENABLE_ECC |
626 GPMI_ECCCTRL_ECC_CMD_DECODE |
627 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
628 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
629 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
630 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
632 mxs_dma_desc_append(channel, d);
634 /* Compile the DMA descriptor - disable the BCH block. */
635 d = mxs_nand_get_dma_desc(nand_info);
637 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
638 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
639 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
643 d->cmd.pio_words[0] =
644 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
645 GPMI_CTRL0_WORD_LENGTH |
646 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
647 GPMI_CTRL0_ADDRESS_NAND_DATA |
648 (mtd->writesize + mtd->oobsize);
649 d->cmd.pio_words[1] = 0;
650 d->cmd.pio_words[2] = 0;
652 mxs_dma_desc_append(channel, d);
654 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
655 d = mxs_nand_get_dma_desc(nand_info);
657 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
658 MXS_DMA_DESC_DEC_SEM;
662 mxs_dma_desc_append(channel, d);
664 /* Invalidate caches */
665 mxs_nand_inval_data_buf(nand_info);
667 /* Execute the DMA chain. */
668 ret = mxs_dma_go(channel);
670 printf("MXS NAND: DMA read error\n");
674 ret = mxs_nand_wait_for_bch_complete();
676 printf("MXS NAND: BCH read timeout\n");
680 /* Invalidate caches */
681 mxs_nand_inval_data_buf(nand_info);
683 /* Read DMA completed, now do the mark swapping. */
684 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
686 /* Loop over status bytes, accumulating ECC status. */
687 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
688 for (i = 0; i < geo->ecc_chunk_count; i++) {
689 if (status[i] == 0x00)
692 if (status[i] == 0xff)
695 if (status[i] == 0xfe) {
700 corrected += status[i];
703 /* Propagate ECC status to the owning MTD. */
704 mtd->ecc_stats.failed += failed;
705 mtd->ecc_stats.corrected += corrected;
708 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
709 * details about our policy for delivering the OOB.
711 * We fill the caller's buffer with set bits, and then copy the block
712 * mark to the caller's buffer. Note that, if block mark swapping was
713 * necessary, it has already been done, so we can rely on the first
714 * byte of the auxiliary buffer to contain the block mark.
716 memset(nand->oob_poi, 0xff, mtd->oobsize);
718 nand->oob_poi[0] = nand_info->oob_buf[0];
720 memcpy(buf, nand_info->data_buf, mtd->writesize);
723 mxs_nand_return_dma_descs(nand_info);
729 * Write a page to NAND.
731 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
732 struct nand_chip *nand, const uint8_t *buf,
733 int oob_required, int page)
735 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
736 struct bch_geometry *geo = &nand_info->bch_geometry;
737 struct mxs_dma_desc *d;
738 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
741 memcpy(nand_info->data_buf, buf, mtd->writesize);
742 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
744 /* Handle block mark swapping. */
745 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
747 /* Compile the DMA descriptor - write data. */
748 d = mxs_nand_get_dma_desc(nand_info);
750 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
751 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
752 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
756 d->cmd.pio_words[0] =
757 GPMI_CTRL0_COMMAND_MODE_WRITE |
758 GPMI_CTRL0_WORD_LENGTH |
759 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
760 GPMI_CTRL0_ADDRESS_NAND_DATA;
761 d->cmd.pio_words[1] = 0;
762 d->cmd.pio_words[2] =
763 GPMI_ECCCTRL_ENABLE_ECC |
764 GPMI_ECCCTRL_ECC_CMD_ENCODE |
765 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
766 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
767 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
768 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
770 mxs_dma_desc_append(channel, d);
773 mxs_nand_flush_data_buf(nand_info);
775 /* Execute the DMA chain. */
776 ret = mxs_dma_go(channel);
778 printf("MXS NAND: DMA write error\n");
782 ret = mxs_nand_wait_for_bch_complete();
784 printf("MXS NAND: BCH write timeout\n");
789 mxs_nand_return_dma_descs(nand_info);
794 * Read OOB from NAND.
796 * This function is a veneer that replaces the function originally installed by
797 * the NAND Flash MTD code.
799 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
800 struct mtd_oob_ops *ops)
802 struct nand_chip *chip = mtd_to_nand(mtd);
803 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
806 if (ops->mode == MTD_OPS_RAW)
807 nand_info->raw_oob_mode = 1;
809 nand_info->raw_oob_mode = 0;
811 ret = nand_info->hooked_read_oob(mtd, from, ops);
813 nand_info->raw_oob_mode = 0;
821 * This function is a veneer that replaces the function originally installed by
822 * the NAND Flash MTD code.
824 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
825 struct mtd_oob_ops *ops)
827 struct nand_chip *chip = mtd_to_nand(mtd);
828 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
831 if (ops->mode == MTD_OPS_RAW)
832 nand_info->raw_oob_mode = 1;
834 nand_info->raw_oob_mode = 0;
836 ret = nand_info->hooked_write_oob(mtd, to, ops);
838 nand_info->raw_oob_mode = 0;
844 * Mark a block bad in NAND.
846 * This function is a veneer that replaces the function originally installed by
847 * the NAND Flash MTD code.
849 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
851 struct nand_chip *chip = mtd_to_nand(mtd);
852 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
855 nand_info->marking_block_bad = 1;
857 ret = nand_info->hooked_block_markbad(mtd, ofs);
859 nand_info->marking_block_bad = 0;
865 * There are several places in this driver where we have to handle the OOB and
866 * block marks. This is the function where things are the most complicated, so
867 * this is where we try to explain it all. All the other places refer back to
870 * These are the rules, in order of decreasing importance:
872 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
873 * write operations take measures to protect it.
875 * 2) In read operations, the first byte of the OOB we return must reflect the
876 * true state of the block mark, no matter where that block mark appears in
879 * 3) ECC-based read operations return an OOB full of set bits (since we never
880 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
883 * 4) "Raw" read operations return a direct view of the physical bytes in the
884 * page, using the conventional definition of which bytes are data and which
885 * are OOB. This gives the caller a way to see the actual, physical bytes
886 * in the page, without the distortions applied by our ECC engine.
888 * What we do for this specific read operation depends on whether we're doing
889 * "raw" read, or an ECC-based read.
891 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
892 * easy. When reading a page, for example, the NAND Flash MTD code calls our
893 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
894 * ECC-based or raw view of the page is implicit in which function it calls
895 * (there is a similar pair of ECC-based/raw functions for writing).
897 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
898 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
899 * caller wants an ECC-based or raw view of the page is not propagated down to
902 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
903 * ecc.read_oob and ecc.write_oob function pointers in the owning
904 * struct mtd_info with our own functions. These hook functions set the
905 * raw_oob_mode field so that, when control finally arrives here, we'll know
908 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
911 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
914 * First, fill in the OOB buffer. If we're doing a raw read, we need to
915 * get the bytes from the physical page. If we're not doing a raw read,
916 * we need to fill the buffer with set bits.
918 if (nand_info->raw_oob_mode) {
920 * If control arrives here, we're doing a "raw" read. Send the
921 * command to read the conventional OOB and read it.
923 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
924 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
927 * If control arrives here, we're not doing a "raw" read. Fill
928 * the OOB buffer with set bits and correct the block mark.
930 memset(nand->oob_poi, 0xff, mtd->oobsize);
932 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
933 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
941 * Write OOB data to NAND.
943 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
946 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
947 uint8_t block_mark = 0;
950 * There are fundamental incompatibilities between the i.MX GPMI NFC and
951 * the NAND Flash MTD model that make it essentially impossible to write
952 * the out-of-band bytes.
954 * We permit *ONE* exception. If the *intent* of writing the OOB is to
955 * mark a block bad, we can do that.
958 if (!nand_info->marking_block_bad) {
959 printf("NXS NAND: Writing OOB isn't supported\n");
963 /* Write the block mark. */
964 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
965 nand->write_buf(mtd, &block_mark, 1);
966 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
968 /* Check if it worked. */
969 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
976 * Claims all blocks are good.
978 * In principle, this function is *only* called when the NAND Flash MTD system
979 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
980 * the driver for bad block information.
982 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
983 * this function is *only* called when we take it away.
985 * Thus, this function is only called when we want *all* blocks to look good,
986 * so it *always* return success.
988 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
994 * At this point, the physical NAND Flash chips have been identified and
995 * counted, so we know the physical geometry. This enables us to make some
996 * important configuration decisions.
998 * The return value of this function propagates directly back to this driver's
999 * board_nand_init(). Anything other than zero will cause this driver to
1000 * tear everything down and declare failure.
1002 int mxs_nand_setup_ecc(struct mtd_info *mtd)
1004 struct nand_chip *nand = mtd_to_nand(mtd);
1005 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1006 struct bch_geometry *geo = &nand_info->bch_geometry;
1007 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1010 if (mxs_nand_calc_ecc_layout(geo, mtd))
1013 /* Configure BCH and set NFC geometry */
1014 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1016 /* Configure layout 0 */
1017 tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1018 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1019 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1020 tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1021 tmp |= (geo->gf_len == 14 ? 1 : 0) <<
1022 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
1023 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1025 tmp = (mtd->writesize + mtd->oobsize)
1026 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1027 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1028 tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1029 tmp |= (geo->gf_len == 14 ? 1 : 0) <<
1030 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1031 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1033 /* Set *all* chip selects to use layout 0 */
1034 writel(0, &bch_regs->hw_bch_layoutselect);
1036 /* Enable BCH complete interrupt */
1037 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1039 /* Hook some operations at the MTD level. */
1040 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1041 nand_info->hooked_read_oob = mtd->_read_oob;
1042 mtd->_read_oob = mxs_nand_hook_read_oob;
1045 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1046 nand_info->hooked_write_oob = mtd->_write_oob;
1047 mtd->_write_oob = mxs_nand_hook_write_oob;
1050 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1051 nand_info->hooked_block_markbad = mtd->_block_markbad;
1052 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1059 * Allocate DMA buffers
1061 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1064 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1066 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1069 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1071 printf("MXS NAND: Error allocating DMA buffers\n");
1075 memset(buf, 0, nand_info->data_buf_size);
1077 nand_info->data_buf = buf;
1078 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1079 /* Command buffers */
1080 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1081 MXS_NAND_COMMAND_BUFFER_SIZE);
1082 if (!nand_info->cmd_buf) {
1084 printf("MXS NAND: Error allocating command buffers\n");
1087 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1088 nand_info->cmd_queue_len = 0;
1094 * Initializes the NFC hardware.
1096 int mxs_nand_init(struct mxs_nand_info *info)
1098 struct mxs_gpmi_regs *gpmi_regs =
1099 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1100 struct mxs_bch_regs *bch_regs =
1101 (struct mxs_bch_regs *)MXS_BCH_BASE;
1102 int i = 0, j, ret = 0;
1104 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1105 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1111 /* Allocate the DMA descriptors. */
1112 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1113 info->desc[i] = mxs_dma_desc_alloc();
1114 if (!info->desc[i]) {
1120 /* Init the DMA controller. */
1122 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1123 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1124 ret = mxs_dma_init_channel(j);
1129 /* Reset the GPMI block. */
1130 mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
1131 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1134 * Choose NAND mode, set IRQ polarity, disable write protection and
1137 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
1138 GPMI_CTRL1_GPMI_MODE,
1139 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1140 GPMI_CTRL1_BCH_MODE);
1145 for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
1148 for (--i; i >= 0; i--)
1149 mxs_dma_desc_free(info->desc[i]);
1153 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1157 int mxs_nand_init_spl(struct nand_chip *nand)
1159 struct mxs_nand_info *nand_info;
1162 nand_info = malloc(sizeof(struct mxs_nand_info));
1164 printf("MXS NAND: Failed to allocate private data\n");
1167 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1169 err = mxs_nand_alloc_buffers(nand_info);
1173 err = mxs_nand_init(nand_info);
1177 nand_set_controller_data(nand, nand_info);
1179 nand->options |= NAND_NO_SUBPAGE_WRITE;
1181 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1182 nand->dev_ready = mxs_nand_device_ready;
1183 nand->select_chip = mxs_nand_select_chip;
1185 nand->read_byte = mxs_nand_read_byte;
1186 nand->read_buf = mxs_nand_read_buf;
1188 nand->ecc.read_page = mxs_nand_ecc_read_page;
1190 nand->ecc.mode = NAND_ECC_HW;
1191 nand->ecc.bytes = 9;
1192 nand->ecc.size = 512;
1193 nand->ecc.strength = 8;
1198 void board_nand_init(void)
1200 struct mtd_info *mtd;
1201 struct mxs_nand_info *nand_info;
1202 struct nand_chip *nand;
1205 nand_info = malloc(sizeof(struct mxs_nand_info));
1207 printf("MXS NAND: Failed to allocate private data\n");
1210 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1212 nand = &nand_info->chip;
1213 mtd = nand_to_mtd(nand);
1214 err = mxs_nand_alloc_buffers(nand_info);
1218 err = mxs_nand_init(nand_info);
1222 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1224 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1225 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1228 nand_set_controller_data(nand, nand_info);
1229 nand->options |= NAND_NO_SUBPAGE_WRITE;
1231 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1233 nand->dev_ready = mxs_nand_device_ready;
1234 nand->select_chip = mxs_nand_select_chip;
1235 nand->block_bad = mxs_nand_block_bad;
1237 nand->read_byte = mxs_nand_read_byte;
1239 nand->read_buf = mxs_nand_read_buf;
1240 nand->write_buf = mxs_nand_write_buf;
1242 /* first scan to find the device and get the page size */
1243 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
1246 if (mxs_nand_setup_ecc(mtd))
1249 nand->ecc.read_page = mxs_nand_ecc_read_page;
1250 nand->ecc.write_page = mxs_nand_ecc_write_page;
1251 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1252 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1254 nand->ecc.layout = &fake_ecc_layout;
1255 nand->ecc.mode = NAND_ECC_HW;
1256 nand->ecc.bytes = 9;
1257 nand->ecc.size = 512;
1258 nand->ecc.strength = 8;
1260 /* second phase scan */
1261 err = nand_scan_tail(mtd);
1265 err = nand_register(0, mtd);
1272 free(nand_info->data_buf);
1273 free(nand_info->cmd_buf);