2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/nand.h>
31 #include <linux/types.h>
33 #include <asm/errno.h>
35 #include <asm/arch/clock.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/imx-common/regs-bch.h>
38 #include <asm/imx-common/regs-gpmi.h>
39 #include <asm/arch/sys_proto.h>
40 #include <asm/imx-common/dma.h>
42 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
44 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
45 #if defined(CONFIG_MX6)
46 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
48 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
50 #define MXS_NAND_METADATA_SIZE 10
52 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
54 #define MXS_NAND_BCH_TIMEOUT 10000
56 struct mxs_nand_info {
59 uint32_t cmd_queue_len;
60 uint32_t data_buf_size;
66 uint8_t marking_block_bad;
69 /* Functions with altered behaviour */
70 int (*hooked_read_oob)(struct mtd_info *mtd,
71 loff_t from, struct mtd_oob_ops *ops);
72 int (*hooked_write_oob)(struct mtd_info *mtd,
73 loff_t to, struct mtd_oob_ops *ops);
74 int (*hooked_block_markbad)(struct mtd_info *mtd,
78 struct mxs_dma_desc **desc;
82 struct nand_ecclayout fake_ecc_layout;
85 * Cache management functions
87 #ifndef CONFIG_SYS_DCACHE_OFF
88 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
90 uint32_t addr = (uint32_t)info->data_buf;
92 flush_dcache_range(addr, addr + info->data_buf_size);
95 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
97 uint32_t addr = (uint32_t)info->data_buf;
99 invalidate_dcache_range(addr, addr + info->data_buf_size);
102 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
104 uint32_t addr = (uint32_t)info->cmd_buf;
106 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
109 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
110 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
111 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
114 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
116 struct mxs_dma_desc *desc;
118 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
119 printf("MXS NAND: Too many DMA descriptors requested\n");
123 desc = info->desc[info->desc_index];
129 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
132 struct mxs_dma_desc *desc;
134 for (i = 0; i < info->desc_index; i++) {
135 desc = info->desc[i];
136 memset(desc, 0, sizeof(struct mxs_dma_desc));
137 desc->address = (dma_addr_t)desc;
140 info->desc_index = 0;
143 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
145 return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
148 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
150 return ecc_strength * 13;
153 static uint32_t mxs_nand_aux_status_offset(void)
155 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
158 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
159 uint32_t page_oob_size)
161 if (page_data_size == 2048)
164 if (page_data_size == 4096) {
165 if (page_oob_size == 128)
168 if (page_oob_size == 218)
175 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
176 uint32_t ecc_strength)
178 uint32_t chunk_data_size_in_bits;
179 uint32_t chunk_ecc_size_in_bits;
180 uint32_t chunk_total_size_in_bits;
181 uint32_t block_mark_chunk_number;
182 uint32_t block_mark_chunk_bit_offset;
183 uint32_t block_mark_bit_offset;
185 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
186 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
188 chunk_total_size_in_bits =
189 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
191 /* Compute the bit offset of the block mark within the physical page. */
192 block_mark_bit_offset = page_data_size * 8;
194 /* Subtract the metadata bits. */
195 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
198 * Compute the chunk number (starting at zero) in which the block mark
201 block_mark_chunk_number =
202 block_mark_bit_offset / chunk_total_size_in_bits;
205 * Compute the bit offset of the block mark within its chunk, and
208 block_mark_chunk_bit_offset = block_mark_bit_offset -
209 (block_mark_chunk_number * chunk_total_size_in_bits);
211 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
215 * Now that we know the chunk number in which the block mark appears,
216 * we can subtract all the ECC bits that appear before it.
218 block_mark_bit_offset -=
219 block_mark_chunk_number * chunk_ecc_size_in_bits;
221 return block_mark_bit_offset;
224 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
226 uint32_t ecc_strength;
227 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
228 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
231 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
233 uint32_t ecc_strength;
234 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
235 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
239 * Wait for BCH complete IRQ and clear the IRQ
241 static int mxs_nand_wait_for_bch_complete(void)
243 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
244 int timeout = MXS_NAND_BCH_TIMEOUT;
247 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
248 BCH_CTRL_COMPLETE_IRQ, timeout);
250 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
256 * This is the function that we install in the cmd_ctrl function pointer of the
257 * owning struct nand_chip. The only functions in the reference implementation
258 * that use these functions pointers are cmdfunc and select_chip.
260 * In this driver, we implement our own select_chip, so this function will only
261 * be called by the reference implementation's cmdfunc. For this reason, we can
262 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
265 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
267 struct nand_chip *nand = mtd->priv;
268 struct mxs_nand_info *nand_info = nand->priv;
269 struct mxs_dma_desc *d;
270 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
274 * If this condition is true, something is _VERY_ wrong in MTD
277 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
278 printf("MXS NAND: Command queue too long\n");
283 * Every operation begins with a command byte and a series of zero or
284 * more address bytes. These are distinguished by either the Address
285 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
286 * asserted. When MTD is ready to execute the command, it will
287 * deasert both latch enables.
289 * Rather than run a separate DMA operation for every single byte, we
290 * queue them up and run a single DMA operation for the entire series
291 * of command and data bytes.
293 if (ctrl & (NAND_ALE | NAND_CLE)) {
294 if (data != NAND_CMD_NONE)
295 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
300 * If control arrives here, MTD has deasserted both the ALE and CLE,
301 * which means it's ready to run an operation. Check if we have any
304 if (nand_info->cmd_queue_len == 0)
307 /* Compile the DMA descriptor -- a descriptor that sends command. */
308 d = mxs_nand_get_dma_desc(nand_info);
310 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
311 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
312 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
313 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
315 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
317 d->cmd.pio_words[0] =
318 GPMI_CTRL0_COMMAND_MODE_WRITE |
319 GPMI_CTRL0_WORD_LENGTH |
320 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
321 GPMI_CTRL0_ADDRESS_NAND_CLE |
322 GPMI_CTRL0_ADDRESS_INCREMENT |
323 nand_info->cmd_queue_len;
325 mxs_dma_desc_append(channel, d);
328 mxs_nand_flush_cmd_buf(nand_info);
330 /* Execute the DMA chain. */
331 ret = mxs_dma_go(channel);
333 printf("MXS NAND: Error sending command\n");
335 mxs_nand_return_dma_descs(nand_info);
337 /* Reset the command queue. */
338 nand_info->cmd_queue_len = 0;
342 * Test if the NAND flash is ready.
344 static int mxs_nand_device_ready(struct mtd_info *mtd)
346 struct nand_chip *chip = mtd->priv;
347 struct mxs_nand_info *nand_info = chip->priv;
348 struct mxs_gpmi_regs *gpmi_regs =
349 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
352 tmp = readl(&gpmi_regs->hw_gpmi_stat);
353 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
359 * Select the NAND chip.
361 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
363 struct nand_chip *nand = mtd->priv;
364 struct mxs_nand_info *nand_info = nand->priv;
366 nand_info->cur_chip = chip;
370 * Handle block mark swapping.
372 * Note that, when this function is called, it doesn't know whether it's
373 * swapping the block mark, or swapping it *back* -- but it doesn't matter
374 * because the the operation is the same.
376 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
377 uint8_t *data_buf, uint8_t *oob_buf)
385 bit_offset = mxs_nand_mark_bit_offset(mtd);
386 buf_offset = mxs_nand_mark_byte_offset(mtd);
389 * Get the byte from the data area that overlays the block mark. Since
390 * the ECC engine applies its own view to the bits in the page, the
391 * physical block mark won't (in general) appear on a byte boundary in
394 src = data_buf[buf_offset] >> bit_offset;
395 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
401 data_buf[buf_offset] &= ~(0xff << bit_offset);
402 data_buf[buf_offset + 1] &= 0xff << bit_offset;
404 data_buf[buf_offset] |= dst << bit_offset;
405 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
409 * Read data from NAND.
411 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
413 struct nand_chip *nand = mtd->priv;
414 struct mxs_nand_info *nand_info = nand->priv;
415 struct mxs_dma_desc *d;
416 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
419 if (length > NAND_MAX_PAGESIZE) {
420 printf("MXS NAND: DMA buffer too big\n");
425 printf("MXS NAND: DMA buffer is NULL\n");
429 /* Compile the DMA descriptor - a descriptor that reads data. */
430 d = mxs_nand_get_dma_desc(nand_info);
432 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
433 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
434 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
435 (length << MXS_DMA_DESC_BYTES_OFFSET);
437 d->cmd.address = (dma_addr_t)nand_info->data_buf;
439 d->cmd.pio_words[0] =
440 GPMI_CTRL0_COMMAND_MODE_READ |
441 GPMI_CTRL0_WORD_LENGTH |
442 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
443 GPMI_CTRL0_ADDRESS_NAND_DATA |
446 mxs_dma_desc_append(channel, d);
449 * A DMA descriptor that waits for the command to end and the chip to
452 * I think we actually should *not* be waiting for the chip to become
453 * ready because, after all, we don't care. I think the original code
454 * did that and no one has re-thought it yet.
456 d = mxs_nand_get_dma_desc(nand_info);
458 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
459 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
460 MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
464 d->cmd.pio_words[0] =
465 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
466 GPMI_CTRL0_WORD_LENGTH |
467 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
468 GPMI_CTRL0_ADDRESS_NAND_DATA;
470 mxs_dma_desc_append(channel, d);
472 /* Execute the DMA chain. */
473 ret = mxs_dma_go(channel);
475 printf("MXS NAND: DMA read error\n");
479 /* Invalidate caches */
480 mxs_nand_inval_data_buf(nand_info);
482 memcpy(buf, nand_info->data_buf, length);
485 mxs_nand_return_dma_descs(nand_info);
489 * Write data to NAND.
491 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
494 struct nand_chip *nand = mtd->priv;
495 struct mxs_nand_info *nand_info = nand->priv;
496 struct mxs_dma_desc *d;
497 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
500 if (length > NAND_MAX_PAGESIZE) {
501 printf("MXS NAND: DMA buffer too big\n");
506 printf("MXS NAND: DMA buffer is NULL\n");
510 memcpy(nand_info->data_buf, buf, length);
512 /* Compile the DMA descriptor - a descriptor that writes data. */
513 d = mxs_nand_get_dma_desc(nand_info);
515 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
516 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
517 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
518 (length << MXS_DMA_DESC_BYTES_OFFSET);
520 d->cmd.address = (dma_addr_t)nand_info->data_buf;
522 d->cmd.pio_words[0] =
523 GPMI_CTRL0_COMMAND_MODE_WRITE |
524 GPMI_CTRL0_WORD_LENGTH |
525 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
526 GPMI_CTRL0_ADDRESS_NAND_DATA |
529 mxs_dma_desc_append(channel, d);
532 mxs_nand_flush_data_buf(nand_info);
534 /* Execute the DMA chain. */
535 ret = mxs_dma_go(channel);
537 printf("MXS NAND: DMA write error\n");
539 mxs_nand_return_dma_descs(nand_info);
543 * Read a single byte from NAND.
545 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
548 mxs_nand_read_buf(mtd, &buf, 1);
553 * Read a page from NAND.
555 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
556 uint8_t *buf, int oob_required,
559 struct mxs_nand_info *nand_info = nand->priv;
560 struct mxs_dma_desc *d;
561 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
562 uint32_t corrected = 0, failed = 0;
566 /* Compile the DMA descriptor - wait for ready. */
567 d = mxs_nand_get_dma_desc(nand_info);
569 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
570 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
571 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
575 d->cmd.pio_words[0] =
576 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
577 GPMI_CTRL0_WORD_LENGTH |
578 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
579 GPMI_CTRL0_ADDRESS_NAND_DATA;
581 mxs_dma_desc_append(channel, d);
583 /* Compile the DMA descriptor - enable the BCH block and read. */
584 d = mxs_nand_get_dma_desc(nand_info);
586 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
587 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
591 d->cmd.pio_words[0] =
592 GPMI_CTRL0_COMMAND_MODE_READ |
593 GPMI_CTRL0_WORD_LENGTH |
594 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
595 GPMI_CTRL0_ADDRESS_NAND_DATA |
596 (mtd->writesize + mtd->oobsize);
597 d->cmd.pio_words[1] = 0;
598 d->cmd.pio_words[2] =
599 GPMI_ECCCTRL_ENABLE_ECC |
600 GPMI_ECCCTRL_ECC_CMD_DECODE |
601 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
602 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
603 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
604 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
606 mxs_dma_desc_append(channel, d);
608 /* Compile the DMA descriptor - disable the BCH block. */
609 d = mxs_nand_get_dma_desc(nand_info);
611 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
612 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
613 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
617 d->cmd.pio_words[0] =
618 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
619 GPMI_CTRL0_WORD_LENGTH |
620 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
621 GPMI_CTRL0_ADDRESS_NAND_DATA |
622 (mtd->writesize + mtd->oobsize);
623 d->cmd.pio_words[1] = 0;
624 d->cmd.pio_words[2] = 0;
626 mxs_dma_desc_append(channel, d);
628 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
629 d = mxs_nand_get_dma_desc(nand_info);
631 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
632 MXS_DMA_DESC_DEC_SEM;
636 mxs_dma_desc_append(channel, d);
638 /* Execute the DMA chain. */
639 ret = mxs_dma_go(channel);
641 printf("MXS NAND: DMA read error\n");
645 ret = mxs_nand_wait_for_bch_complete();
647 printf("MXS NAND: BCH read timeout\n");
651 /* Invalidate caches */
652 mxs_nand_inval_data_buf(nand_info);
654 /* Read DMA completed, now do the mark swapping. */
655 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
657 /* Loop over status bytes, accumulating ECC status. */
658 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
659 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
660 if (status[i] == 0x00)
663 if (status[i] == 0xff)
666 if (status[i] == 0xfe) {
671 corrected += status[i];
674 /* Propagate ECC status to the owning MTD. */
675 mtd->ecc_stats.failed += failed;
676 mtd->ecc_stats.corrected += corrected;
679 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
680 * details about our policy for delivering the OOB.
682 * We fill the caller's buffer with set bits, and then copy the block
683 * mark to the caller's buffer. Note that, if block mark swapping was
684 * necessary, it has already been done, so we can rely on the first
685 * byte of the auxiliary buffer to contain the block mark.
687 memset(nand->oob_poi, 0xff, mtd->oobsize);
689 nand->oob_poi[0] = nand_info->oob_buf[0];
691 memcpy(buf, nand_info->data_buf, mtd->writesize);
694 mxs_nand_return_dma_descs(nand_info);
700 * Write a page to NAND.
702 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
703 struct nand_chip *nand, const uint8_t *buf,
706 struct mxs_nand_info *nand_info = nand->priv;
707 struct mxs_dma_desc *d;
708 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
711 memcpy(nand_info->data_buf, buf, mtd->writesize);
712 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
714 /* Handle block mark swapping. */
715 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
717 /* Compile the DMA descriptor - write data. */
718 d = mxs_nand_get_dma_desc(nand_info);
720 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
721 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
722 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
726 d->cmd.pio_words[0] =
727 GPMI_CTRL0_COMMAND_MODE_WRITE |
728 GPMI_CTRL0_WORD_LENGTH |
729 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
730 GPMI_CTRL0_ADDRESS_NAND_DATA;
731 d->cmd.pio_words[1] = 0;
732 d->cmd.pio_words[2] =
733 GPMI_ECCCTRL_ENABLE_ECC |
734 GPMI_ECCCTRL_ECC_CMD_ENCODE |
735 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
736 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
737 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
738 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
740 mxs_dma_desc_append(channel, d);
743 mxs_nand_flush_data_buf(nand_info);
745 /* Execute the DMA chain. */
746 ret = mxs_dma_go(channel);
748 printf("MXS NAND: DMA write error\n");
752 ret = mxs_nand_wait_for_bch_complete();
754 printf("MXS NAND: BCH write timeout\n");
759 mxs_nand_return_dma_descs(nand_info);
764 * Read OOB from NAND.
766 * This function is a veneer that replaces the function originally installed by
767 * the NAND Flash MTD code.
769 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
770 struct mtd_oob_ops *ops)
772 struct nand_chip *chip = mtd->priv;
773 struct mxs_nand_info *nand_info = chip->priv;
776 if (ops->mode == MTD_OPS_RAW)
777 nand_info->raw_oob_mode = 1;
779 nand_info->raw_oob_mode = 0;
781 ret = nand_info->hooked_read_oob(mtd, from, ops);
783 nand_info->raw_oob_mode = 0;
791 * This function is a veneer that replaces the function originally installed by
792 * the NAND Flash MTD code.
794 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
795 struct mtd_oob_ops *ops)
797 struct nand_chip *chip = mtd->priv;
798 struct mxs_nand_info *nand_info = chip->priv;
801 if (ops->mode == MTD_OPS_RAW)
802 nand_info->raw_oob_mode = 1;
804 nand_info->raw_oob_mode = 0;
806 ret = nand_info->hooked_write_oob(mtd, to, ops);
808 nand_info->raw_oob_mode = 0;
814 * Mark a block bad in NAND.
816 * This function is a veneer that replaces the function originally installed by
817 * the NAND Flash MTD code.
819 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
821 struct nand_chip *chip = mtd->priv;
822 struct mxs_nand_info *nand_info = chip->priv;
825 nand_info->marking_block_bad = 1;
827 ret = nand_info->hooked_block_markbad(mtd, ofs);
829 nand_info->marking_block_bad = 0;
835 * There are several places in this driver where we have to handle the OOB and
836 * block marks. This is the function where things are the most complicated, so
837 * this is where we try to explain it all. All the other places refer back to
840 * These are the rules, in order of decreasing importance:
842 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
843 * write operations take measures to protect it.
845 * 2) In read operations, the first byte of the OOB we return must reflect the
846 * true state of the block mark, no matter where that block mark appears in
849 * 3) ECC-based read operations return an OOB full of set bits (since we never
850 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
853 * 4) "Raw" read operations return a direct view of the physical bytes in the
854 * page, using the conventional definition of which bytes are data and which
855 * are OOB. This gives the caller a way to see the actual, physical bytes
856 * in the page, without the distortions applied by our ECC engine.
858 * What we do for this specific read operation depends on whether we're doing
859 * "raw" read, or an ECC-based read.
861 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
862 * easy. When reading a page, for example, the NAND Flash MTD code calls our
863 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
864 * ECC-based or raw view of the page is implicit in which function it calls
865 * (there is a similar pair of ECC-based/raw functions for writing).
867 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
868 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
869 * caller wants an ECC-based or raw view of the page is not propagated down to
872 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
873 * ecc.read_oob and ecc.write_oob function pointers in the owning
874 * struct mtd_info with our own functions. These hook functions set the
875 * raw_oob_mode field so that, when control finally arrives here, we'll know
878 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
881 struct mxs_nand_info *nand_info = nand->priv;
884 * First, fill in the OOB buffer. If we're doing a raw read, we need to
885 * get the bytes from the physical page. If we're not doing a raw read,
886 * we need to fill the buffer with set bits.
888 if (nand_info->raw_oob_mode) {
890 * If control arrives here, we're doing a "raw" read. Send the
891 * command to read the conventional OOB and read it.
893 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
894 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
897 * If control arrives here, we're not doing a "raw" read. Fill
898 * the OOB buffer with set bits and correct the block mark.
900 memset(nand->oob_poi, 0xff, mtd->oobsize);
902 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
903 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
911 * Write OOB data to NAND.
913 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
916 struct mxs_nand_info *nand_info = nand->priv;
917 uint8_t block_mark = 0;
920 * There are fundamental incompatibilities between the i.MX GPMI NFC and
921 * the NAND Flash MTD model that make it essentially impossible to write
922 * the out-of-band bytes.
924 * We permit *ONE* exception. If the *intent* of writing the OOB is to
925 * mark a block bad, we can do that.
928 if (!nand_info->marking_block_bad) {
929 printf("NXS NAND: Writing OOB isn't supported\n");
933 /* Write the block mark. */
934 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
935 nand->write_buf(mtd, &block_mark, 1);
936 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
938 /* Check if it worked. */
939 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
946 * Claims all blocks are good.
948 * In principle, this function is *only* called when the NAND Flash MTD system
949 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
950 * the driver for bad block information.
952 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
953 * this function is *only* called when we take it away.
955 * Thus, this function is only called when we want *all* blocks to look good,
956 * so it *always* return success.
958 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
964 * Nominally, the purpose of this function is to look for or create the bad
965 * block table. In fact, since the we call this function at the very end of
966 * the initialization process started by nand_scan(), and we doesn't have a
967 * more formal mechanism, we "hook" this function to continue init process.
969 * At this point, the physical NAND Flash chips have been identified and
970 * counted, so we know the physical geometry. This enables us to make some
971 * important configuration decisions.
973 * The return value of this function propogates directly back to this driver's
974 * call to nand_scan(). Anything other than zero will cause this driver to
975 * tear everything down and declare failure.
977 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
979 struct nand_chip *nand = mtd->priv;
980 struct mxs_nand_info *nand_info = nand->priv;
981 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
984 /* Configure BCH and set NFC geometry */
985 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
987 /* Configure layout 0 */
988 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
989 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
990 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
991 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
992 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
993 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
994 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
995 writel(tmp, &bch_regs->hw_bch_flash0layout0);
997 tmp = (mtd->writesize + mtd->oobsize)
998 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
999 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1000 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1001 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
1002 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1003 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1005 /* Set *all* chip selects to use layout 0 */
1006 writel(0, &bch_regs->hw_bch_layoutselect);
1008 /* Enable BCH complete interrupt */
1009 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1011 /* Hook some operations at the MTD level. */
1012 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1013 nand_info->hooked_read_oob = mtd->_read_oob;
1014 mtd->_read_oob = mxs_nand_hook_read_oob;
1017 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1018 nand_info->hooked_write_oob = mtd->_write_oob;
1019 mtd->_write_oob = mxs_nand_hook_write_oob;
1022 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1023 nand_info->hooked_block_markbad = mtd->_block_markbad;
1024 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1027 /* We use the reference implementation for bad block management. */
1028 return nand_default_bbt(mtd);
1032 * Allocate DMA buffers
1034 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1037 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1039 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1042 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1044 printf("MXS NAND: Error allocating DMA buffers\n");
1048 memset(buf, 0, nand_info->data_buf_size);
1050 nand_info->data_buf = buf;
1051 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1052 /* Command buffers */
1053 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1054 MXS_NAND_COMMAND_BUFFER_SIZE);
1055 if (!nand_info->cmd_buf) {
1057 printf("MXS NAND: Error allocating command buffers\n");
1060 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1061 nand_info->cmd_queue_len = 0;
1067 * Initializes the NFC hardware.
1069 int mxs_nand_init(struct mxs_nand_info *info)
1071 struct mxs_gpmi_regs *gpmi_regs =
1072 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1073 struct mxs_bch_regs *bch_regs =
1074 (struct mxs_bch_regs *)MXS_BCH_BASE;
1077 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1078 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1082 /* Allocate the DMA descriptors. */
1083 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1084 info->desc[i] = mxs_dma_desc_alloc();
1089 /* Init the DMA controller. */
1090 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1091 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1092 if (mxs_dma_init_channel(j))
1096 /* Reset the GPMI block. */
1097 mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
1098 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1101 * Choose NAND mode, set IRQ polarity, disable write protection and
1104 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
1105 GPMI_CTRL1_GPMI_MODE,
1106 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1107 GPMI_CTRL1_BCH_MODE);
1112 for (--j; j >= 0; j--)
1117 for (--i; i >= 0; i--)
1118 mxs_dma_desc_free(info->desc[i]);
1119 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1124 * This function is called during the driver binding process.
1126 * @param pdev the device structure used to store device specific
1127 * information that is used by the suspend, resume and
1130 * @return The function always returns 0.
1132 int board_nand_init(struct nand_chip *nand)
1134 struct mxs_nand_info *nand_info;
1137 nand_info = malloc(sizeof(struct mxs_nand_info));
1139 printf("MXS NAND: Failed to allocate private data\n");
1142 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1144 err = mxs_nand_alloc_buffers(nand_info);
1148 err = mxs_nand_init(nand_info);
1152 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1154 nand->priv = nand_info;
1155 nand->options |= NAND_NO_SUBPAGE_WRITE;
1157 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1159 nand->dev_ready = mxs_nand_device_ready;
1160 nand->select_chip = mxs_nand_select_chip;
1161 nand->block_bad = mxs_nand_block_bad;
1162 nand->scan_bbt = mxs_nand_scan_bbt;
1164 nand->read_byte = mxs_nand_read_byte;
1166 nand->read_buf = mxs_nand_read_buf;
1167 nand->write_buf = mxs_nand_write_buf;
1169 nand->ecc.read_page = mxs_nand_ecc_read_page;
1170 nand->ecc.write_page = mxs_nand_ecc_write_page;
1171 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1172 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1174 nand->ecc.layout = &fake_ecc_layout;
1175 nand->ecc.mode = NAND_ECC_HW;
1176 nand->ecc.bytes = 9;
1177 nand->ecc.size = 512;
1178 nand->ecc.strength = 8;
1183 free(nand_info->data_buf);
1184 free(nand_info->cmd_buf);