2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/types.h>
21 #include <asm/errno.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/imx-regs.h>
25 #include <asm/imx-common/regs-bch.h>
26 #include <asm/imx-common/regs-gpmi.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/imx-common/dma.h>
30 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
32 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
33 #if defined(CONFIG_MX6)
34 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
36 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
38 #define MXS_NAND_METADATA_SIZE 10
40 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
42 #define MXS_NAND_BCH_TIMEOUT 10000
44 struct mxs_nand_info {
47 uint32_t cmd_queue_len;
48 uint32_t data_buf_size;
54 uint8_t marking_block_bad;
57 /* Functions with altered behaviour */
58 int (*hooked_read_oob)(struct mtd_info *mtd,
59 loff_t from, struct mtd_oob_ops *ops);
60 int (*hooked_write_oob)(struct mtd_info *mtd,
61 loff_t to, struct mtd_oob_ops *ops);
62 int (*hooked_block_markbad)(struct mtd_info *mtd,
66 struct mxs_dma_desc **desc;
70 struct nand_ecclayout fake_ecc_layout;
73 * Cache management functions
75 #ifndef CONFIG_SYS_DCACHE_OFF
76 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
78 uint32_t addr = (uint32_t)info->data_buf;
80 flush_dcache_range(addr, addr + info->data_buf_size);
83 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
85 uint32_t addr = (uint32_t)info->data_buf;
87 invalidate_dcache_range(addr, addr + info->data_buf_size);
90 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
92 uint32_t addr = (uint32_t)info->cmd_buf;
94 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
97 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
98 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
99 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
102 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
104 struct mxs_dma_desc *desc;
106 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
107 printf("MXS NAND: Too many DMA descriptors requested\n");
111 desc = info->desc[info->desc_index];
117 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
120 struct mxs_dma_desc *desc;
122 for (i = 0; i < info->desc_index; i++) {
123 desc = info->desc[i];
124 memset(desc, 0, sizeof(struct mxs_dma_desc));
125 desc->address = (dma_addr_t)desc;
128 info->desc_index = 0;
131 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
133 return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
136 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
138 return ecc_strength * 13;
141 static uint32_t mxs_nand_aux_status_offset(void)
143 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
146 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
147 uint32_t page_oob_size)
149 if (page_data_size == 2048) {
150 if (page_oob_size == 64)
153 if (page_oob_size == 112)
157 if (page_data_size == 4096) {
158 if (page_oob_size == 128)
161 if (page_oob_size == 218)
164 if (page_oob_size == 224)
171 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
172 uint32_t ecc_strength)
174 uint32_t chunk_data_size_in_bits;
175 uint32_t chunk_ecc_size_in_bits;
176 uint32_t chunk_total_size_in_bits;
177 uint32_t block_mark_chunk_number;
178 uint32_t block_mark_chunk_bit_offset;
179 uint32_t block_mark_bit_offset;
181 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
182 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
184 chunk_total_size_in_bits =
185 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
187 /* Compute the bit offset of the block mark within the physical page. */
188 block_mark_bit_offset = page_data_size * 8;
190 /* Subtract the metadata bits. */
191 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
194 * Compute the chunk number (starting at zero) in which the block mark
197 block_mark_chunk_number =
198 block_mark_bit_offset / chunk_total_size_in_bits;
201 * Compute the bit offset of the block mark within its chunk, and
204 block_mark_chunk_bit_offset = block_mark_bit_offset -
205 (block_mark_chunk_number * chunk_total_size_in_bits);
207 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
211 * Now that we know the chunk number in which the block mark appears,
212 * we can subtract all the ECC bits that appear before it.
214 block_mark_bit_offset -=
215 block_mark_chunk_number * chunk_ecc_size_in_bits;
217 return block_mark_bit_offset;
220 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
222 uint32_t ecc_strength;
223 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
224 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
227 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
229 uint32_t ecc_strength;
230 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
231 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
235 * Wait for BCH complete IRQ and clear the IRQ
237 static int mxs_nand_wait_for_bch_complete(void)
239 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
240 int timeout = MXS_NAND_BCH_TIMEOUT;
243 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
244 BCH_CTRL_COMPLETE_IRQ, timeout);
246 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
252 * This is the function that we install in the cmd_ctrl function pointer of the
253 * owning struct nand_chip. The only functions in the reference implementation
254 * that use these functions pointers are cmdfunc and select_chip.
256 * In this driver, we implement our own select_chip, so this function will only
257 * be called by the reference implementation's cmdfunc. For this reason, we can
258 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
261 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
263 struct nand_chip *nand = mtd->priv;
264 struct mxs_nand_info *nand_info = nand->priv;
265 struct mxs_dma_desc *d;
266 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
270 * If this condition is true, something is _VERY_ wrong in MTD
273 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
274 printf("MXS NAND: Command queue too long\n");
279 * Every operation begins with a command byte and a series of zero or
280 * more address bytes. These are distinguished by either the Address
281 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
282 * asserted. When MTD is ready to execute the command, it will
283 * deasert both latch enables.
285 * Rather than run a separate DMA operation for every single byte, we
286 * queue them up and run a single DMA operation for the entire series
287 * of command and data bytes.
289 if (ctrl & (NAND_ALE | NAND_CLE)) {
290 if (data != NAND_CMD_NONE)
291 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
296 * If control arrives here, MTD has deasserted both the ALE and CLE,
297 * which means it's ready to run an operation. Check if we have any
300 if (nand_info->cmd_queue_len == 0)
303 /* Compile the DMA descriptor -- a descriptor that sends command. */
304 d = mxs_nand_get_dma_desc(nand_info);
306 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
307 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
308 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
309 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
311 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
313 d->cmd.pio_words[0] =
314 GPMI_CTRL0_COMMAND_MODE_WRITE |
315 GPMI_CTRL0_WORD_LENGTH |
316 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
317 GPMI_CTRL0_ADDRESS_NAND_CLE |
318 GPMI_CTRL0_ADDRESS_INCREMENT |
319 nand_info->cmd_queue_len;
321 mxs_dma_desc_append(channel, d);
324 mxs_nand_flush_cmd_buf(nand_info);
326 /* Execute the DMA chain. */
327 ret = mxs_dma_go(channel);
329 printf("MXS NAND: Error sending command\n");
331 mxs_nand_return_dma_descs(nand_info);
333 /* Reset the command queue. */
334 nand_info->cmd_queue_len = 0;
338 * Test if the NAND flash is ready.
340 static int mxs_nand_device_ready(struct mtd_info *mtd)
342 struct nand_chip *chip = mtd->priv;
343 struct mxs_nand_info *nand_info = chip->priv;
344 struct mxs_gpmi_regs *gpmi_regs =
345 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
348 tmp = readl(&gpmi_regs->hw_gpmi_stat);
349 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
355 * Select the NAND chip.
357 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
359 struct nand_chip *nand = mtd->priv;
360 struct mxs_nand_info *nand_info = nand->priv;
362 nand_info->cur_chip = chip;
366 * Handle block mark swapping.
368 * Note that, when this function is called, it doesn't know whether it's
369 * swapping the block mark, or swapping it *back* -- but it doesn't matter
370 * because the the operation is the same.
372 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
373 uint8_t *data_buf, uint8_t *oob_buf)
381 bit_offset = mxs_nand_mark_bit_offset(mtd);
382 buf_offset = mxs_nand_mark_byte_offset(mtd);
385 * Get the byte from the data area that overlays the block mark. Since
386 * the ECC engine applies its own view to the bits in the page, the
387 * physical block mark won't (in general) appear on a byte boundary in
390 src = data_buf[buf_offset] >> bit_offset;
391 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
397 data_buf[buf_offset] &= ~(0xff << bit_offset);
398 data_buf[buf_offset + 1] &= 0xff << bit_offset;
400 data_buf[buf_offset] |= dst << bit_offset;
401 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
405 * Read data from NAND.
407 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
409 struct nand_chip *nand = mtd->priv;
410 struct mxs_nand_info *nand_info = nand->priv;
411 struct mxs_dma_desc *d;
412 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
415 if (length > NAND_MAX_PAGESIZE) {
416 printf("MXS NAND: DMA buffer too big\n");
421 printf("MXS NAND: DMA buffer is NULL\n");
425 /* Compile the DMA descriptor - a descriptor that reads data. */
426 d = mxs_nand_get_dma_desc(nand_info);
428 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
429 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
430 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
431 (length << MXS_DMA_DESC_BYTES_OFFSET);
433 d->cmd.address = (dma_addr_t)nand_info->data_buf;
435 d->cmd.pio_words[0] =
436 GPMI_CTRL0_COMMAND_MODE_READ |
437 GPMI_CTRL0_WORD_LENGTH |
438 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
439 GPMI_CTRL0_ADDRESS_NAND_DATA |
442 mxs_dma_desc_append(channel, d);
445 * A DMA descriptor that waits for the command to end and the chip to
448 * I think we actually should *not* be waiting for the chip to become
449 * ready because, after all, we don't care. I think the original code
450 * did that and no one has re-thought it yet.
452 d = mxs_nand_get_dma_desc(nand_info);
454 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
455 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
456 MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
460 d->cmd.pio_words[0] =
461 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
462 GPMI_CTRL0_WORD_LENGTH |
463 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
464 GPMI_CTRL0_ADDRESS_NAND_DATA;
466 mxs_dma_desc_append(channel, d);
468 /* Execute the DMA chain. */
469 ret = mxs_dma_go(channel);
471 printf("MXS NAND: DMA read error\n");
475 /* Invalidate caches */
476 mxs_nand_inval_data_buf(nand_info);
478 memcpy(buf, nand_info->data_buf, length);
481 mxs_nand_return_dma_descs(nand_info);
485 * Write data to NAND.
487 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
490 struct nand_chip *nand = mtd->priv;
491 struct mxs_nand_info *nand_info = nand->priv;
492 struct mxs_dma_desc *d;
493 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
496 if (length > NAND_MAX_PAGESIZE) {
497 printf("MXS NAND: DMA buffer too big\n");
502 printf("MXS NAND: DMA buffer is NULL\n");
506 memcpy(nand_info->data_buf, buf, length);
508 /* Compile the DMA descriptor - a descriptor that writes data. */
509 d = mxs_nand_get_dma_desc(nand_info);
511 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
512 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
513 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
514 (length << MXS_DMA_DESC_BYTES_OFFSET);
516 d->cmd.address = (dma_addr_t)nand_info->data_buf;
518 d->cmd.pio_words[0] =
519 GPMI_CTRL0_COMMAND_MODE_WRITE |
520 GPMI_CTRL0_WORD_LENGTH |
521 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
522 GPMI_CTRL0_ADDRESS_NAND_DATA |
525 mxs_dma_desc_append(channel, d);
528 mxs_nand_flush_data_buf(nand_info);
530 /* Execute the DMA chain. */
531 ret = mxs_dma_go(channel);
533 printf("MXS NAND: DMA write error\n");
535 mxs_nand_return_dma_descs(nand_info);
539 * Read a single byte from NAND.
541 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
544 mxs_nand_read_buf(mtd, &buf, 1);
549 * Read a page from NAND.
551 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
552 uint8_t *buf, int oob_required,
555 struct mxs_nand_info *nand_info = nand->priv;
556 struct mxs_dma_desc *d;
557 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
558 uint32_t corrected = 0, failed = 0;
562 /* Compile the DMA descriptor - wait for ready. */
563 d = mxs_nand_get_dma_desc(nand_info);
565 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
566 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
567 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
571 d->cmd.pio_words[0] =
572 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
573 GPMI_CTRL0_WORD_LENGTH |
574 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
575 GPMI_CTRL0_ADDRESS_NAND_DATA;
577 mxs_dma_desc_append(channel, d);
579 /* Compile the DMA descriptor - enable the BCH block and read. */
580 d = mxs_nand_get_dma_desc(nand_info);
582 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
583 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
587 d->cmd.pio_words[0] =
588 GPMI_CTRL0_COMMAND_MODE_READ |
589 GPMI_CTRL0_WORD_LENGTH |
590 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
591 GPMI_CTRL0_ADDRESS_NAND_DATA |
592 (mtd->writesize + mtd->oobsize);
593 d->cmd.pio_words[1] = 0;
594 d->cmd.pio_words[2] =
595 GPMI_ECCCTRL_ENABLE_ECC |
596 GPMI_ECCCTRL_ECC_CMD_DECODE |
597 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
598 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
599 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
600 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
602 mxs_dma_desc_append(channel, d);
604 /* Compile the DMA descriptor - disable the BCH block. */
605 d = mxs_nand_get_dma_desc(nand_info);
607 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
608 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
609 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
613 d->cmd.pio_words[0] =
614 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
615 GPMI_CTRL0_WORD_LENGTH |
616 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
617 GPMI_CTRL0_ADDRESS_NAND_DATA |
618 (mtd->writesize + mtd->oobsize);
619 d->cmd.pio_words[1] = 0;
620 d->cmd.pio_words[2] = 0;
622 mxs_dma_desc_append(channel, d);
624 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
625 d = mxs_nand_get_dma_desc(nand_info);
627 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
628 MXS_DMA_DESC_DEC_SEM;
632 mxs_dma_desc_append(channel, d);
634 /* Execute the DMA chain. */
635 ret = mxs_dma_go(channel);
637 printf("MXS NAND: DMA read error\n");
641 ret = mxs_nand_wait_for_bch_complete();
643 printf("MXS NAND: BCH read timeout\n");
647 /* Invalidate caches */
648 mxs_nand_inval_data_buf(nand_info);
650 /* Read DMA completed, now do the mark swapping. */
651 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
653 /* Loop over status bytes, accumulating ECC status. */
654 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
655 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
656 if (status[i] == 0x00)
659 if (status[i] == 0xff)
662 if (status[i] == 0xfe) {
667 corrected += status[i];
670 /* Propagate ECC status to the owning MTD. */
671 mtd->ecc_stats.failed += failed;
672 mtd->ecc_stats.corrected += corrected;
675 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
676 * details about our policy for delivering the OOB.
678 * We fill the caller's buffer with set bits, and then copy the block
679 * mark to the caller's buffer. Note that, if block mark swapping was
680 * necessary, it has already been done, so we can rely on the first
681 * byte of the auxiliary buffer to contain the block mark.
683 memset(nand->oob_poi, 0xff, mtd->oobsize);
685 nand->oob_poi[0] = nand_info->oob_buf[0];
687 memcpy(buf, nand_info->data_buf, mtd->writesize);
690 mxs_nand_return_dma_descs(nand_info);
696 * Write a page to NAND.
698 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
699 struct nand_chip *nand, const uint8_t *buf,
702 struct mxs_nand_info *nand_info = nand->priv;
703 struct mxs_dma_desc *d;
704 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
707 memcpy(nand_info->data_buf, buf, mtd->writesize);
708 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
710 /* Handle block mark swapping. */
711 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
713 /* Compile the DMA descriptor - write data. */
714 d = mxs_nand_get_dma_desc(nand_info);
716 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
717 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
718 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
722 d->cmd.pio_words[0] =
723 GPMI_CTRL0_COMMAND_MODE_WRITE |
724 GPMI_CTRL0_WORD_LENGTH |
725 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
726 GPMI_CTRL0_ADDRESS_NAND_DATA;
727 d->cmd.pio_words[1] = 0;
728 d->cmd.pio_words[2] =
729 GPMI_ECCCTRL_ENABLE_ECC |
730 GPMI_ECCCTRL_ECC_CMD_ENCODE |
731 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
732 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
733 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
734 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
736 mxs_dma_desc_append(channel, d);
739 mxs_nand_flush_data_buf(nand_info);
741 /* Execute the DMA chain. */
742 ret = mxs_dma_go(channel);
744 printf("MXS NAND: DMA write error\n");
748 ret = mxs_nand_wait_for_bch_complete();
750 printf("MXS NAND: BCH write timeout\n");
755 mxs_nand_return_dma_descs(nand_info);
760 * Read OOB from NAND.
762 * This function is a veneer that replaces the function originally installed by
763 * the NAND Flash MTD code.
765 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
766 struct mtd_oob_ops *ops)
768 struct nand_chip *chip = mtd->priv;
769 struct mxs_nand_info *nand_info = chip->priv;
772 if (ops->mode == MTD_OPS_RAW)
773 nand_info->raw_oob_mode = 1;
775 nand_info->raw_oob_mode = 0;
777 ret = nand_info->hooked_read_oob(mtd, from, ops);
779 nand_info->raw_oob_mode = 0;
787 * This function is a veneer that replaces the function originally installed by
788 * the NAND Flash MTD code.
790 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
791 struct mtd_oob_ops *ops)
793 struct nand_chip *chip = mtd->priv;
794 struct mxs_nand_info *nand_info = chip->priv;
797 if (ops->mode == MTD_OPS_RAW)
798 nand_info->raw_oob_mode = 1;
800 nand_info->raw_oob_mode = 0;
802 ret = nand_info->hooked_write_oob(mtd, to, ops);
804 nand_info->raw_oob_mode = 0;
810 * Mark a block bad in NAND.
812 * This function is a veneer that replaces the function originally installed by
813 * the NAND Flash MTD code.
815 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
817 struct nand_chip *chip = mtd->priv;
818 struct mxs_nand_info *nand_info = chip->priv;
821 nand_info->marking_block_bad = 1;
823 ret = nand_info->hooked_block_markbad(mtd, ofs);
825 nand_info->marking_block_bad = 0;
831 * There are several places in this driver where we have to handle the OOB and
832 * block marks. This is the function where things are the most complicated, so
833 * this is where we try to explain it all. All the other places refer back to
836 * These are the rules, in order of decreasing importance:
838 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
839 * write operations take measures to protect it.
841 * 2) In read operations, the first byte of the OOB we return must reflect the
842 * true state of the block mark, no matter where that block mark appears in
845 * 3) ECC-based read operations return an OOB full of set bits (since we never
846 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
849 * 4) "Raw" read operations return a direct view of the physical bytes in the
850 * page, using the conventional definition of which bytes are data and which
851 * are OOB. This gives the caller a way to see the actual, physical bytes
852 * in the page, without the distortions applied by our ECC engine.
854 * What we do for this specific read operation depends on whether we're doing
855 * "raw" read, or an ECC-based read.
857 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
858 * easy. When reading a page, for example, the NAND Flash MTD code calls our
859 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
860 * ECC-based or raw view of the page is implicit in which function it calls
861 * (there is a similar pair of ECC-based/raw functions for writing).
863 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
864 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
865 * caller wants an ECC-based or raw view of the page is not propagated down to
868 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
869 * ecc.read_oob and ecc.write_oob function pointers in the owning
870 * struct mtd_info with our own functions. These hook functions set the
871 * raw_oob_mode field so that, when control finally arrives here, we'll know
874 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
877 struct mxs_nand_info *nand_info = nand->priv;
880 * First, fill in the OOB buffer. If we're doing a raw read, we need to
881 * get the bytes from the physical page. If we're not doing a raw read,
882 * we need to fill the buffer with set bits.
884 if (nand_info->raw_oob_mode) {
886 * If control arrives here, we're doing a "raw" read. Send the
887 * command to read the conventional OOB and read it.
889 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
890 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
893 * If control arrives here, we're not doing a "raw" read. Fill
894 * the OOB buffer with set bits and correct the block mark.
896 memset(nand->oob_poi, 0xff, mtd->oobsize);
898 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
899 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
907 * Write OOB data to NAND.
909 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
912 struct mxs_nand_info *nand_info = nand->priv;
913 uint8_t block_mark = 0;
916 * There are fundamental incompatibilities between the i.MX GPMI NFC and
917 * the NAND Flash MTD model that make it essentially impossible to write
918 * the out-of-band bytes.
920 * We permit *ONE* exception. If the *intent* of writing the OOB is to
921 * mark a block bad, we can do that.
924 if (!nand_info->marking_block_bad) {
925 printf("NXS NAND: Writing OOB isn't supported\n");
929 /* Write the block mark. */
930 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
931 nand->write_buf(mtd, &block_mark, 1);
932 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
934 /* Check if it worked. */
935 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
942 * Claims all blocks are good.
944 * In principle, this function is *only* called when the NAND Flash MTD system
945 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
946 * the driver for bad block information.
948 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
949 * this function is *only* called when we take it away.
951 * Thus, this function is only called when we want *all* blocks to look good,
952 * so it *always* return success.
954 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
960 * Nominally, the purpose of this function is to look for or create the bad
961 * block table. In fact, since the we call this function at the very end of
962 * the initialization process started by nand_scan(), and we doesn't have a
963 * more formal mechanism, we "hook" this function to continue init process.
965 * At this point, the physical NAND Flash chips have been identified and
966 * counted, so we know the physical geometry. This enables us to make some
967 * important configuration decisions.
969 * The return value of this function propogates directly back to this driver's
970 * call to nand_scan(). Anything other than zero will cause this driver to
971 * tear everything down and declare failure.
973 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
975 struct nand_chip *nand = mtd->priv;
976 struct mxs_nand_info *nand_info = nand->priv;
977 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
980 /* Configure BCH and set NFC geometry */
981 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
983 /* Configure layout 0 */
984 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
985 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
986 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
987 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
988 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
989 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
990 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
991 writel(tmp, &bch_regs->hw_bch_flash0layout0);
993 tmp = (mtd->writesize + mtd->oobsize)
994 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
995 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
996 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
997 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
998 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
999 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1001 /* Set *all* chip selects to use layout 0 */
1002 writel(0, &bch_regs->hw_bch_layoutselect);
1004 /* Enable BCH complete interrupt */
1005 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1007 /* Hook some operations at the MTD level. */
1008 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1009 nand_info->hooked_read_oob = mtd->_read_oob;
1010 mtd->_read_oob = mxs_nand_hook_read_oob;
1013 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1014 nand_info->hooked_write_oob = mtd->_write_oob;
1015 mtd->_write_oob = mxs_nand_hook_write_oob;
1018 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1019 nand_info->hooked_block_markbad = mtd->_block_markbad;
1020 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1023 /* We use the reference implementation for bad block management. */
1024 return nand_default_bbt(mtd);
1028 * Allocate DMA buffers
1030 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1033 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1035 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1038 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1040 printf("MXS NAND: Error allocating DMA buffers\n");
1044 memset(buf, 0, nand_info->data_buf_size);
1046 nand_info->data_buf = buf;
1047 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1048 /* Command buffers */
1049 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1050 MXS_NAND_COMMAND_BUFFER_SIZE);
1051 if (!nand_info->cmd_buf) {
1053 printf("MXS NAND: Error allocating command buffers\n");
1056 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1057 nand_info->cmd_queue_len = 0;
1063 * Initializes the NFC hardware.
1065 int mxs_nand_init(struct mxs_nand_info *info)
1067 struct mxs_gpmi_regs *gpmi_regs =
1068 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1069 struct mxs_bch_regs *bch_regs =
1070 (struct mxs_bch_regs *)MXS_BCH_BASE;
1073 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1074 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1078 /* Allocate the DMA descriptors. */
1079 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1080 info->desc[i] = mxs_dma_desc_alloc();
1085 /* Init the DMA controller. */
1086 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1087 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1088 if (mxs_dma_init_channel(j))
1092 /* Reset the GPMI block. */
1093 mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
1094 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1097 * Choose NAND mode, set IRQ polarity, disable write protection and
1100 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
1101 GPMI_CTRL1_GPMI_MODE,
1102 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1103 GPMI_CTRL1_BCH_MODE);
1108 for (--j; j >= 0; j--)
1113 for (--i; i >= 0; i--)
1114 mxs_dma_desc_free(info->desc[i]);
1115 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1120 * This function is called during the driver binding process.
1122 * @param pdev the device structure used to store device specific
1123 * information that is used by the suspend, resume and
1126 * @return The function always returns 0.
1128 int board_nand_init(struct nand_chip *nand)
1130 struct mxs_nand_info *nand_info;
1133 nand_info = malloc(sizeof(struct mxs_nand_info));
1135 printf("MXS NAND: Failed to allocate private data\n");
1138 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1140 err = mxs_nand_alloc_buffers(nand_info);
1144 err = mxs_nand_init(nand_info);
1148 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1150 nand->priv = nand_info;
1151 nand->options |= NAND_NO_SUBPAGE_WRITE;
1153 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1155 nand->dev_ready = mxs_nand_device_ready;
1156 nand->select_chip = mxs_nand_select_chip;
1157 nand->block_bad = mxs_nand_block_bad;
1158 nand->scan_bbt = mxs_nand_scan_bbt;
1160 nand->read_byte = mxs_nand_read_byte;
1162 nand->read_buf = mxs_nand_read_buf;
1163 nand->write_buf = mxs_nand_write_buf;
1165 nand->ecc.read_page = mxs_nand_ecc_read_page;
1166 nand->ecc.write_page = mxs_nand_ecc_write_page;
1167 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1168 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1170 nand->ecc.layout = &fake_ecc_layout;
1171 nand->ecc.mode = NAND_ECC_HW;
1172 nand->ecc.bytes = 9;
1173 nand->ecc.size = 512;
1174 nand->ecc.strength = 8;
1179 free(nand_info->data_buf);
1180 free(nand_info->cmd_buf);