1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale i.MX28 NAND flash driver
5 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
6 * on behalf of DENX Software Engineering GmbH
8 * Based on code from LTIB:
9 * Freescale GPMI NFC NAND Flash Driver
11 * Copyright (C) 2010 Freescale Semiconductor, Inc.
12 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/rawnand.h>
18 #include <linux/sizes.h>
19 #include <linux/types.h>
22 #include <linux/errno.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/imx-regs.h>
26 #include <asm/mach-imx/regs-bch.h>
27 #include <asm/mach-imx/regs-gpmi.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/mach-imx/dma.h>
32 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
34 #if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
35 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
37 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
39 #define MXS_NAND_METADATA_SIZE 10
40 #define MXS_NAND_BITS_PER_ECC_LEVEL 13
42 #if !defined(CONFIG_SYS_CACHELINE_SIZE) || CONFIG_SYS_CACHELINE_SIZE < 32
43 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
45 #define MXS_NAND_COMMAND_BUFFER_SIZE CONFIG_SYS_CACHELINE_SIZE
48 #define MXS_NAND_BCH_TIMEOUT 10000
51 * @gf_len: The length of Galois Field. (e.g., 13 or 14)
52 * @ecc_strength: A number that describes the strength of the ECC
54 * @ecc_chunk_size: The size, in bytes, of a single ECC chunk. Note
55 * the first chunk in the page includes both data and
56 * metadata, so it's a bit larger than this value.
57 * @ecc_chunk_count: The number of ECC chunks in the page,
58 * @block_mark_byte_offset: The byte offset in the ECC-based page view at
59 * which the underlying physical block mark appears.
60 * @block_mark_bit_offset: The bit offset into the ECC-based page view at
61 * which the underlying physical block mark appears.
65 unsigned int ecc_strength;
66 unsigned int ecc_chunk_size;
67 unsigned int ecc_chunk_count;
68 unsigned int block_mark_byte_offset;
69 unsigned int block_mark_bit_offset;
72 struct mxs_nand_info {
73 struct nand_chip chip;
76 uint32_t cmd_queue_len;
77 uint32_t data_buf_size;
78 struct bch_geometry bch_geometry;
84 uint8_t marking_block_bad;
87 struct mxs_gpmi_regs *gpmi_regs;
88 struct mxs_bch_regs *bch_regs;
90 /* Functions with altered behaviour */
91 int (*hooked_read_oob)(struct mtd_info *mtd,
92 loff_t from, struct mtd_oob_ops *ops);
93 int (*hooked_write_oob)(struct mtd_info *mtd,
94 loff_t to, struct mtd_oob_ops *ops);
95 int (*hooked_block_markbad)(struct mtd_info *mtd,
99 struct mxs_dma_desc **desc;
103 struct nand_ecclayout fake_ecc_layout;
106 * Cache management functions
108 #ifndef CONFIG_SYS_DCACHE_OFF
109 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
111 uint32_t addr = (uint32_t)info->data_buf;
113 flush_dcache_range(addr, addr + info->data_buf_size);
116 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
118 uint32_t addr = (uint32_t)info->data_buf;
120 invalidate_dcache_range(addr, addr + info->data_buf_size);
123 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
125 uint32_t addr = (uint32_t)info->cmd_buf;
127 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
130 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
131 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
132 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
135 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
137 struct mxs_dma_desc *desc;
139 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
140 printf("MXS NAND: Too many DMA descriptors requested\n");
144 desc = info->desc[info->desc_index];
150 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
153 struct mxs_dma_desc *desc;
155 for (i = 0; i < info->desc_index; i++) {
156 desc = info->desc[i];
157 memset(desc, 0, sizeof(struct mxs_dma_desc));
158 desc->address = (dma_addr_t)desc;
161 info->desc_index = 0;
164 static uint32_t mxs_nand_aux_status_offset(void)
166 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
169 static inline int mxs_nand_calc_mark_offset(struct bch_geometry *geo,
170 uint32_t page_data_size)
172 uint32_t chunk_data_size_in_bits = geo->ecc_chunk_size * 8;
173 uint32_t chunk_ecc_size_in_bits = geo->ecc_strength * geo->gf_len;
174 uint32_t chunk_total_size_in_bits;
175 uint32_t block_mark_chunk_number;
176 uint32_t block_mark_chunk_bit_offset;
177 uint32_t block_mark_bit_offset;
179 chunk_total_size_in_bits =
180 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
182 /* Compute the bit offset of the block mark within the physical page. */
183 block_mark_bit_offset = page_data_size * 8;
185 /* Subtract the metadata bits. */
186 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
189 * Compute the chunk number (starting at zero) in which the block mark
192 block_mark_chunk_number =
193 block_mark_bit_offset / chunk_total_size_in_bits;
196 * Compute the bit offset of the block mark within its chunk, and
199 block_mark_chunk_bit_offset = block_mark_bit_offset -
200 (block_mark_chunk_number * chunk_total_size_in_bits);
202 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
206 * Now that we know the chunk number in which the block mark appears,
207 * we can subtract all the ECC bits that appear before it.
209 block_mark_bit_offset -=
210 block_mark_chunk_number * chunk_ecc_size_in_bits;
212 geo->block_mark_byte_offset = block_mark_bit_offset >> 3;
213 geo->block_mark_bit_offset = block_mark_bit_offset & 0x7;
218 static inline unsigned int mxs_nand_max_ecc_strength_supported(void)
220 /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
221 if (is_mx6sx() || is_mx7())
227 static inline int mxs_nand_calc_ecc_layout_by_info(struct bch_geometry *geo,
228 struct mtd_info *mtd)
230 struct nand_chip *chip = mtd_to_nand(mtd);
232 if (!(chip->ecc_strength_ds > 0 && chip->ecc_step_ds > 0))
235 switch (chip->ecc_step_ds) {
246 geo->ecc_chunk_size = chip->ecc_step_ds;
247 geo->ecc_strength = round_up(chip->ecc_strength_ds, 2);
249 /* Keep the C >= O */
250 if (geo->ecc_chunk_size < mtd->oobsize)
253 if (geo->ecc_strength > mxs_nand_max_ecc_strength_supported())
256 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
261 static inline int mxs_nand_calc_ecc_layout(struct bch_geometry *geo,
262 struct mtd_info *mtd)
264 /* The default for the length of Galois Field. */
267 /* The default for chunk size. */
268 geo->ecc_chunk_size = 512;
270 if (geo->ecc_chunk_size < mtd->oobsize) {
272 geo->ecc_chunk_size *= 2;
275 if (mtd->oobsize > geo->ecc_chunk_size) {
276 printf("Not support the NAND chips whose oob size is larger then %d bytes!\n",
277 geo->ecc_chunk_size);
281 geo->ecc_chunk_count = mtd->writesize / geo->ecc_chunk_size;
284 * Determine the ECC layout with the formula:
285 * ECC bits per chunk = (total page spare data bits) /
286 * (bits per ECC level) / (chunks per page)
288 * total page spare data bits =
289 * (page oob size - meta data size) * (bits per byte)
291 geo->ecc_strength = ((mtd->oobsize - MXS_NAND_METADATA_SIZE) * 8)
292 / (geo->gf_len * geo->ecc_chunk_count);
294 geo->ecc_strength = min(round_down(geo->ecc_strength, 2),
295 mxs_nand_max_ecc_strength_supported());
301 * Wait for BCH complete IRQ and clear the IRQ
303 static int mxs_nand_wait_for_bch_complete(struct mxs_nand_info *nand_info)
305 int timeout = MXS_NAND_BCH_TIMEOUT;
308 ret = mxs_wait_mask_set(&nand_info->bch_regs->hw_bch_ctrl_reg,
309 BCH_CTRL_COMPLETE_IRQ, timeout);
311 writel(BCH_CTRL_COMPLETE_IRQ, &nand_info->bch_regs->hw_bch_ctrl_clr);
317 * This is the function that we install in the cmd_ctrl function pointer of the
318 * owning struct nand_chip. The only functions in the reference implementation
319 * that use these functions pointers are cmdfunc and select_chip.
321 * In this driver, we implement our own select_chip, so this function will only
322 * be called by the reference implementation's cmdfunc. For this reason, we can
323 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
326 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
328 struct nand_chip *nand = mtd_to_nand(mtd);
329 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
330 struct mxs_dma_desc *d;
331 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
335 * If this condition is true, something is _VERY_ wrong in MTD
338 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
339 printf("MXS NAND: Command queue too long\n");
344 * Every operation begins with a command byte and a series of zero or
345 * more address bytes. These are distinguished by either the Address
346 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
347 * asserted. When MTD is ready to execute the command, it will
348 * deasert both latch enables.
350 * Rather than run a separate DMA operation for every single byte, we
351 * queue them up and run a single DMA operation for the entire series
352 * of command and data bytes.
354 if (ctrl & (NAND_ALE | NAND_CLE)) {
355 if (data != NAND_CMD_NONE)
356 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
361 * If control arrives here, MTD has deasserted both the ALE and CLE,
362 * which means it's ready to run an operation. Check if we have any
365 if (nand_info->cmd_queue_len == 0)
368 /* Compile the DMA descriptor -- a descriptor that sends command. */
369 d = mxs_nand_get_dma_desc(nand_info);
371 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
372 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
373 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
374 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
376 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
378 d->cmd.pio_words[0] =
379 GPMI_CTRL0_COMMAND_MODE_WRITE |
380 GPMI_CTRL0_WORD_LENGTH |
381 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
382 GPMI_CTRL0_ADDRESS_NAND_CLE |
383 GPMI_CTRL0_ADDRESS_INCREMENT |
384 nand_info->cmd_queue_len;
386 mxs_dma_desc_append(channel, d);
389 mxs_nand_flush_cmd_buf(nand_info);
391 /* Execute the DMA chain. */
392 ret = mxs_dma_go(channel);
394 printf("MXS NAND: Error sending command\n");
396 mxs_nand_return_dma_descs(nand_info);
398 /* Reset the command queue. */
399 nand_info->cmd_queue_len = 0;
403 * Test if the NAND flash is ready.
405 static int mxs_nand_device_ready(struct mtd_info *mtd)
407 struct nand_chip *chip = mtd_to_nand(mtd);
408 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
411 tmp = readl(&nand_info->gpmi_regs->hw_gpmi_stat);
412 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
418 * Select the NAND chip.
420 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
422 struct nand_chip *nand = mtd_to_nand(mtd);
423 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
425 nand_info->cur_chip = chip;
429 * Handle block mark swapping.
431 * Note that, when this function is called, it doesn't know whether it's
432 * swapping the block mark, or swapping it *back* -- but it doesn't matter
433 * because the the operation is the same.
435 static void mxs_nand_swap_block_mark(struct bch_geometry *geo,
436 uint8_t *data_buf, uint8_t *oob_buf)
438 uint32_t bit_offset = geo->block_mark_bit_offset;
439 uint32_t buf_offset = geo->block_mark_byte_offset;
445 * Get the byte from the data area that overlays the block mark. Since
446 * the ECC engine applies its own view to the bits in the page, the
447 * physical block mark won't (in general) appear on a byte boundary in
450 src = data_buf[buf_offset] >> bit_offset;
451 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
457 data_buf[buf_offset] &= ~(0xff << bit_offset);
458 data_buf[buf_offset + 1] &= 0xff << bit_offset;
460 data_buf[buf_offset] |= dst << bit_offset;
461 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
465 * Read data from NAND.
467 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
469 struct nand_chip *nand = mtd_to_nand(mtd);
470 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
471 struct mxs_dma_desc *d;
472 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
475 if (length > NAND_MAX_PAGESIZE) {
476 printf("MXS NAND: DMA buffer too big\n");
481 printf("MXS NAND: DMA buffer is NULL\n");
485 /* Compile the DMA descriptor - a descriptor that reads data. */
486 d = mxs_nand_get_dma_desc(nand_info);
488 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
489 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
490 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
491 (length << MXS_DMA_DESC_BYTES_OFFSET);
493 d->cmd.address = (dma_addr_t)nand_info->data_buf;
495 d->cmd.pio_words[0] =
496 GPMI_CTRL0_COMMAND_MODE_READ |
497 GPMI_CTRL0_WORD_LENGTH |
498 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
499 GPMI_CTRL0_ADDRESS_NAND_DATA |
502 mxs_dma_desc_append(channel, d);
505 * A DMA descriptor that waits for the command to end and the chip to
508 * I think we actually should *not* be waiting for the chip to become
509 * ready because, after all, we don't care. I think the original code
510 * did that and no one has re-thought it yet.
512 d = mxs_nand_get_dma_desc(nand_info);
514 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
515 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
516 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
520 d->cmd.pio_words[0] =
521 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
522 GPMI_CTRL0_WORD_LENGTH |
523 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
524 GPMI_CTRL0_ADDRESS_NAND_DATA;
526 mxs_dma_desc_append(channel, d);
528 /* Invalidate caches */
529 mxs_nand_inval_data_buf(nand_info);
531 /* Execute the DMA chain. */
532 ret = mxs_dma_go(channel);
534 printf("MXS NAND: DMA read error\n");
538 /* Invalidate caches */
539 mxs_nand_inval_data_buf(nand_info);
541 memcpy(buf, nand_info->data_buf, length);
544 mxs_nand_return_dma_descs(nand_info);
548 * Write data to NAND.
550 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
553 struct nand_chip *nand = mtd_to_nand(mtd);
554 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
555 struct mxs_dma_desc *d;
556 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
559 if (length > NAND_MAX_PAGESIZE) {
560 printf("MXS NAND: DMA buffer too big\n");
565 printf("MXS NAND: DMA buffer is NULL\n");
569 memcpy(nand_info->data_buf, buf, length);
571 /* Compile the DMA descriptor - a descriptor that writes data. */
572 d = mxs_nand_get_dma_desc(nand_info);
574 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
575 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
576 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
577 (length << MXS_DMA_DESC_BYTES_OFFSET);
579 d->cmd.address = (dma_addr_t)nand_info->data_buf;
581 d->cmd.pio_words[0] =
582 GPMI_CTRL0_COMMAND_MODE_WRITE |
583 GPMI_CTRL0_WORD_LENGTH |
584 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
585 GPMI_CTRL0_ADDRESS_NAND_DATA |
588 mxs_dma_desc_append(channel, d);
591 mxs_nand_flush_data_buf(nand_info);
593 /* Execute the DMA chain. */
594 ret = mxs_dma_go(channel);
596 printf("MXS NAND: DMA write error\n");
598 mxs_nand_return_dma_descs(nand_info);
602 * Read a single byte from NAND.
604 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
607 mxs_nand_read_buf(mtd, &buf, 1);
612 * Read a page from NAND.
614 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
615 uint8_t *buf, int oob_required,
618 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
619 struct bch_geometry *geo = &nand_info->bch_geometry;
620 struct mxs_dma_desc *d;
621 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
622 uint32_t corrected = 0, failed = 0;
626 /* Compile the DMA descriptor - wait for ready. */
627 d = mxs_nand_get_dma_desc(nand_info);
629 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
630 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
631 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
635 d->cmd.pio_words[0] =
636 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
637 GPMI_CTRL0_WORD_LENGTH |
638 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
639 GPMI_CTRL0_ADDRESS_NAND_DATA;
641 mxs_dma_desc_append(channel, d);
643 /* Compile the DMA descriptor - enable the BCH block and read. */
644 d = mxs_nand_get_dma_desc(nand_info);
646 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
647 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
651 d->cmd.pio_words[0] =
652 GPMI_CTRL0_COMMAND_MODE_READ |
653 GPMI_CTRL0_WORD_LENGTH |
654 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
655 GPMI_CTRL0_ADDRESS_NAND_DATA |
656 (mtd->writesize + mtd->oobsize);
657 d->cmd.pio_words[1] = 0;
658 d->cmd.pio_words[2] =
659 GPMI_ECCCTRL_ENABLE_ECC |
660 GPMI_ECCCTRL_ECC_CMD_DECODE |
661 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
662 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
663 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
664 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
666 mxs_dma_desc_append(channel, d);
668 /* Compile the DMA descriptor - disable the BCH block. */
669 d = mxs_nand_get_dma_desc(nand_info);
671 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
672 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
673 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
677 d->cmd.pio_words[0] =
678 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
679 GPMI_CTRL0_WORD_LENGTH |
680 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
681 GPMI_CTRL0_ADDRESS_NAND_DATA |
682 (mtd->writesize + mtd->oobsize);
683 d->cmd.pio_words[1] = 0;
684 d->cmd.pio_words[2] = 0;
686 mxs_dma_desc_append(channel, d);
688 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
689 d = mxs_nand_get_dma_desc(nand_info);
691 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
692 MXS_DMA_DESC_DEC_SEM;
696 mxs_dma_desc_append(channel, d);
698 /* Invalidate caches */
699 mxs_nand_inval_data_buf(nand_info);
701 /* Execute the DMA chain. */
702 ret = mxs_dma_go(channel);
704 printf("MXS NAND: DMA read error\n");
708 ret = mxs_nand_wait_for_bch_complete(nand_info);
710 printf("MXS NAND: BCH read timeout\n");
714 /* Invalidate caches */
715 mxs_nand_inval_data_buf(nand_info);
717 /* Read DMA completed, now do the mark swapping. */
718 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
720 /* Loop over status bytes, accumulating ECC status. */
721 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
722 for (i = 0; i < geo->ecc_chunk_count; i++) {
723 if (status[i] == 0x00)
726 if (status[i] == 0xff)
729 if (status[i] == 0xfe) {
734 corrected += status[i];
737 /* Propagate ECC status to the owning MTD. */
738 mtd->ecc_stats.failed += failed;
739 mtd->ecc_stats.corrected += corrected;
742 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
743 * details about our policy for delivering the OOB.
745 * We fill the caller's buffer with set bits, and then copy the block
746 * mark to the caller's buffer. Note that, if block mark swapping was
747 * necessary, it has already been done, so we can rely on the first
748 * byte of the auxiliary buffer to contain the block mark.
750 memset(nand->oob_poi, 0xff, mtd->oobsize);
752 nand->oob_poi[0] = nand_info->oob_buf[0];
754 memcpy(buf, nand_info->data_buf, mtd->writesize);
757 mxs_nand_return_dma_descs(nand_info);
763 * Write a page to NAND.
765 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
766 struct nand_chip *nand, const uint8_t *buf,
767 int oob_required, int page)
769 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
770 struct bch_geometry *geo = &nand_info->bch_geometry;
771 struct mxs_dma_desc *d;
772 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
775 memcpy(nand_info->data_buf, buf, mtd->writesize);
776 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
778 /* Handle block mark swapping. */
779 mxs_nand_swap_block_mark(geo, nand_info->data_buf, nand_info->oob_buf);
781 /* Compile the DMA descriptor - write data. */
782 d = mxs_nand_get_dma_desc(nand_info);
784 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
785 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
786 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
790 d->cmd.pio_words[0] =
791 GPMI_CTRL0_COMMAND_MODE_WRITE |
792 GPMI_CTRL0_WORD_LENGTH |
793 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
794 GPMI_CTRL0_ADDRESS_NAND_DATA;
795 d->cmd.pio_words[1] = 0;
796 d->cmd.pio_words[2] =
797 GPMI_ECCCTRL_ENABLE_ECC |
798 GPMI_ECCCTRL_ECC_CMD_ENCODE |
799 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
800 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
801 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
802 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
804 mxs_dma_desc_append(channel, d);
807 mxs_nand_flush_data_buf(nand_info);
809 /* Execute the DMA chain. */
810 ret = mxs_dma_go(channel);
812 printf("MXS NAND: DMA write error\n");
816 ret = mxs_nand_wait_for_bch_complete(nand_info);
818 printf("MXS NAND: BCH write timeout\n");
823 mxs_nand_return_dma_descs(nand_info);
828 * Read OOB from NAND.
830 * This function is a veneer that replaces the function originally installed by
831 * the NAND Flash MTD code.
833 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
834 struct mtd_oob_ops *ops)
836 struct nand_chip *chip = mtd_to_nand(mtd);
837 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
840 if (ops->mode == MTD_OPS_RAW)
841 nand_info->raw_oob_mode = 1;
843 nand_info->raw_oob_mode = 0;
845 ret = nand_info->hooked_read_oob(mtd, from, ops);
847 nand_info->raw_oob_mode = 0;
855 * This function is a veneer that replaces the function originally installed by
856 * the NAND Flash MTD code.
858 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
859 struct mtd_oob_ops *ops)
861 struct nand_chip *chip = mtd_to_nand(mtd);
862 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
865 if (ops->mode == MTD_OPS_RAW)
866 nand_info->raw_oob_mode = 1;
868 nand_info->raw_oob_mode = 0;
870 ret = nand_info->hooked_write_oob(mtd, to, ops);
872 nand_info->raw_oob_mode = 0;
878 * Mark a block bad in NAND.
880 * This function is a veneer that replaces the function originally installed by
881 * the NAND Flash MTD code.
883 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
885 struct nand_chip *chip = mtd_to_nand(mtd);
886 struct mxs_nand_info *nand_info = nand_get_controller_data(chip);
889 nand_info->marking_block_bad = 1;
891 ret = nand_info->hooked_block_markbad(mtd, ofs);
893 nand_info->marking_block_bad = 0;
899 * There are several places in this driver where we have to handle the OOB and
900 * block marks. This is the function where things are the most complicated, so
901 * this is where we try to explain it all. All the other places refer back to
904 * These are the rules, in order of decreasing importance:
906 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
907 * write operations take measures to protect it.
909 * 2) In read operations, the first byte of the OOB we return must reflect the
910 * true state of the block mark, no matter where that block mark appears in
913 * 3) ECC-based read operations return an OOB full of set bits (since we never
914 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
917 * 4) "Raw" read operations return a direct view of the physical bytes in the
918 * page, using the conventional definition of which bytes are data and which
919 * are OOB. This gives the caller a way to see the actual, physical bytes
920 * in the page, without the distortions applied by our ECC engine.
922 * What we do for this specific read operation depends on whether we're doing
923 * "raw" read, or an ECC-based read.
925 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
926 * easy. When reading a page, for example, the NAND Flash MTD code calls our
927 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
928 * ECC-based or raw view of the page is implicit in which function it calls
929 * (there is a similar pair of ECC-based/raw functions for writing).
931 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
932 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
933 * caller wants an ECC-based or raw view of the page is not propagated down to
936 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
937 * ecc.read_oob and ecc.write_oob function pointers in the owning
938 * struct mtd_info with our own functions. These hook functions set the
939 * raw_oob_mode field so that, when control finally arrives here, we'll know
942 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
945 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
948 * First, fill in the OOB buffer. If we're doing a raw read, we need to
949 * get the bytes from the physical page. If we're not doing a raw read,
950 * we need to fill the buffer with set bits.
952 if (nand_info->raw_oob_mode) {
954 * If control arrives here, we're doing a "raw" read. Send the
955 * command to read the conventional OOB and read it.
957 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
958 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
961 * If control arrives here, we're not doing a "raw" read. Fill
962 * the OOB buffer with set bits and correct the block mark.
964 memset(nand->oob_poi, 0xff, mtd->oobsize);
966 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
967 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
975 * Write OOB data to NAND.
977 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
980 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
981 uint8_t block_mark = 0;
984 * There are fundamental incompatibilities between the i.MX GPMI NFC and
985 * the NAND Flash MTD model that make it essentially impossible to write
986 * the out-of-band bytes.
988 * We permit *ONE* exception. If the *intent* of writing the OOB is to
989 * mark a block bad, we can do that.
992 if (!nand_info->marking_block_bad) {
993 printf("NXS NAND: Writing OOB isn't supported\n");
997 /* Write the block mark. */
998 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
999 nand->write_buf(mtd, &block_mark, 1);
1000 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1002 /* Check if it worked. */
1003 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
1010 * Claims all blocks are good.
1012 * In principle, this function is *only* called when the NAND Flash MTD system
1013 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
1014 * the driver for bad block information.
1016 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
1017 * this function is *only* called when we take it away.
1019 * Thus, this function is only called when we want *all* blocks to look good,
1020 * so it *always* return success.
1022 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
1028 * At this point, the physical NAND Flash chips have been identified and
1029 * counted, so we know the physical geometry. This enables us to make some
1030 * important configuration decisions.
1032 * The return value of this function propagates directly back to this driver's
1033 * board_nand_init(). Anything other than zero will cause this driver to
1034 * tear everything down and declare failure.
1036 int mxs_nand_setup_ecc(struct mtd_info *mtd)
1038 struct nand_chip *nand = mtd_to_nand(mtd);
1039 struct mxs_nand_info *nand_info = nand_get_controller_data(nand);
1040 struct bch_geometry *geo = &nand_info->bch_geometry;
1041 struct mxs_bch_regs *bch_regs = nand_info->bch_regs;
1043 int ret = -ENOTSUPP;
1045 #ifdef CONFIG_NAND_MXS_USE_MINIMUM_ECC
1046 ret = mxs_nand_calc_ecc_layout_by_info(geo, mtd);
1049 if (ret == -ENOTSUPP)
1050 ret = mxs_nand_calc_ecc_layout(geo, mtd);
1055 mxs_nand_calc_mark_offset(geo, mtd->writesize);
1057 /* Configure BCH and set NFC geometry */
1058 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1060 /* Configure layout 0 */
1061 tmp = (geo->ecc_chunk_count - 1) << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1062 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1063 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT0_ECC0_OFFSET;
1064 tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1065 tmp |= (geo->gf_len == 14 ? 1 : 0) <<
1066 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
1067 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1069 tmp = (mtd->writesize + mtd->oobsize)
1070 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1071 tmp |= (geo->ecc_strength >> 1) << BCH_FLASHLAYOUT1_ECCN_OFFSET;
1072 tmp |= geo->ecc_chunk_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1073 tmp |= (geo->gf_len == 14 ? 1 : 0) <<
1074 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1075 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1077 /* Set *all* chip selects to use layout 0 */
1078 writel(0, &bch_regs->hw_bch_layoutselect);
1080 /* Enable BCH complete interrupt */
1081 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1083 /* Hook some operations at the MTD level. */
1084 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1085 nand_info->hooked_read_oob = mtd->_read_oob;
1086 mtd->_read_oob = mxs_nand_hook_read_oob;
1089 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1090 nand_info->hooked_write_oob = mtd->_write_oob;
1091 mtd->_write_oob = mxs_nand_hook_write_oob;
1094 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1095 nand_info->hooked_block_markbad = mtd->_block_markbad;
1096 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1103 * Allocate DMA buffers
1105 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1108 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1110 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1113 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1115 printf("MXS NAND: Error allocating DMA buffers\n");
1119 memset(buf, 0, nand_info->data_buf_size);
1121 nand_info->data_buf = buf;
1122 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1123 /* Command buffers */
1124 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1125 MXS_NAND_COMMAND_BUFFER_SIZE);
1126 if (!nand_info->cmd_buf) {
1128 printf("MXS NAND: Error allocating command buffers\n");
1131 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1132 nand_info->cmd_queue_len = 0;
1138 * Initializes the NFC hardware.
1140 int mxs_nand_init(struct mxs_nand_info *info)
1142 int i = 0, j, ret = 0;
1144 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1145 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1151 /* Allocate the DMA descriptors. */
1152 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1153 info->desc[i] = mxs_dma_desc_alloc();
1154 if (!info->desc[i]) {
1160 /* Init the DMA controller. */
1162 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1163 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1164 ret = mxs_dma_init_channel(j);
1169 /* Reset the GPMI block. */
1170 mxs_reset_block(&info->gpmi_regs->hw_gpmi_ctrl0_reg);
1171 mxs_reset_block(&info->bch_regs->hw_bch_ctrl_reg);
1174 * Choose NAND mode, set IRQ polarity, disable write protection and
1177 clrsetbits_le32(&info->gpmi_regs->hw_gpmi_ctrl1,
1178 GPMI_CTRL1_GPMI_MODE,
1179 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1180 GPMI_CTRL1_BCH_MODE);
1185 for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
1188 for (--i; i >= 0; i--)
1189 mxs_dma_desc_free(info->desc[i]);
1193 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1197 int mxs_nand_init_spl(struct nand_chip *nand)
1199 struct mxs_nand_info *nand_info;
1202 nand_info = malloc(sizeof(struct mxs_nand_info));
1204 printf("MXS NAND: Failed to allocate private data\n");
1207 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1209 nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1210 nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1211 err = mxs_nand_alloc_buffers(nand_info);
1215 err = mxs_nand_init(nand_info);
1219 nand_set_controller_data(nand, nand_info);
1221 nand->options |= NAND_NO_SUBPAGE_WRITE;
1223 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1224 nand->dev_ready = mxs_nand_device_ready;
1225 nand->select_chip = mxs_nand_select_chip;
1227 nand->read_byte = mxs_nand_read_byte;
1228 nand->read_buf = mxs_nand_read_buf;
1230 nand->ecc.read_page = mxs_nand_ecc_read_page;
1232 nand->ecc.mode = NAND_ECC_HW;
1233 nand->ecc.bytes = 9;
1234 nand->ecc.size = 512;
1235 nand->ecc.strength = 8;
1240 void board_nand_init(void)
1242 struct mtd_info *mtd;
1243 struct mxs_nand_info *nand_info;
1244 struct nand_chip *nand;
1247 nand_info = malloc(sizeof(struct mxs_nand_info));
1249 printf("MXS NAND: Failed to allocate private data\n");
1252 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1254 nand_info->gpmi_regs = (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1255 nand_info->bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
1256 nand = &nand_info->chip;
1257 mtd = nand_to_mtd(nand);
1258 err = mxs_nand_alloc_buffers(nand_info);
1262 err = mxs_nand_init(nand_info);
1266 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1268 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1269 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1272 nand_set_controller_data(nand, nand_info);
1273 nand->options |= NAND_NO_SUBPAGE_WRITE;
1275 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1277 nand->dev_ready = mxs_nand_device_ready;
1278 nand->select_chip = mxs_nand_select_chip;
1279 nand->block_bad = mxs_nand_block_bad;
1281 nand->read_byte = mxs_nand_read_byte;
1283 nand->read_buf = mxs_nand_read_buf;
1284 nand->write_buf = mxs_nand_write_buf;
1286 /* first scan to find the device and get the page size */
1287 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL))
1290 if (mxs_nand_setup_ecc(mtd))
1293 nand->ecc.read_page = mxs_nand_ecc_read_page;
1294 nand->ecc.write_page = mxs_nand_ecc_write_page;
1295 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1296 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1298 nand->ecc.layout = &fake_ecc_layout;
1299 nand->ecc.mode = NAND_ECC_HW;
1300 nand->ecc.size = nand_info->bch_geometry.ecc_chunk_size;
1301 nand->ecc.strength = nand_info->bch_geometry.ecc_strength;
1303 /* second phase scan */
1304 err = nand_scan_tail(mtd);
1308 err = nand_register(0, mtd);
1315 free(nand_info->data_buf);
1316 free(nand_info->cmd_buf);