2 * Freescale i.MX28 NAND flash driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
13 * SPDX-License-Identifier: GPL-2.0+
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/nand.h>
19 #include <linux/types.h>
21 #include <asm/errno.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/imx-regs.h>
25 #include <asm/imx-common/regs-bch.h>
26 #include <asm/imx-common/regs-gpmi.h>
27 #include <asm/arch/sys_proto.h>
28 #include <asm/imx-common/dma.h>
30 #define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
32 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
33 #if defined(CONFIG_MX6)
34 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
36 #define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
38 #define MXS_NAND_METADATA_SIZE 10
40 #define MXS_NAND_COMMAND_BUFFER_SIZE 32
42 #define MXS_NAND_BCH_TIMEOUT 10000
44 struct mxs_nand_info {
47 uint32_t cmd_queue_len;
48 uint32_t data_buf_size;
54 uint8_t marking_block_bad;
57 /* Functions with altered behaviour */
58 int (*hooked_read_oob)(struct mtd_info *mtd,
59 loff_t from, struct mtd_oob_ops *ops);
60 int (*hooked_write_oob)(struct mtd_info *mtd,
61 loff_t to, struct mtd_oob_ops *ops);
62 int (*hooked_block_markbad)(struct mtd_info *mtd,
66 struct mxs_dma_desc **desc;
70 struct nand_ecclayout fake_ecc_layout;
73 * Cache management functions
75 #ifndef CONFIG_SYS_DCACHE_OFF
76 static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
78 uint32_t addr = (uint32_t)info->data_buf;
80 flush_dcache_range(addr, addr + info->data_buf_size);
83 static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
85 uint32_t addr = (uint32_t)info->data_buf;
87 invalidate_dcache_range(addr, addr + info->data_buf_size);
90 static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
92 uint32_t addr = (uint32_t)info->cmd_buf;
94 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
97 static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
98 static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
99 static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
102 static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
104 struct mxs_dma_desc *desc;
106 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
107 printf("MXS NAND: Too many DMA descriptors requested\n");
111 desc = info->desc[info->desc_index];
117 static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
120 struct mxs_dma_desc *desc;
122 for (i = 0; i < info->desc_index; i++) {
123 desc = info->desc[i];
124 memset(desc, 0, sizeof(struct mxs_dma_desc));
125 desc->address = (dma_addr_t)desc;
128 info->desc_index = 0;
131 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
133 return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
136 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
138 return ecc_strength * 13;
141 static uint32_t mxs_nand_aux_status_offset(void)
143 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
146 static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
147 uint32_t page_oob_size)
149 if (page_data_size == 2048)
152 if (page_data_size == 4096) {
153 if (page_oob_size == 128)
156 if (page_oob_size == 218)
163 static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
164 uint32_t ecc_strength)
166 uint32_t chunk_data_size_in_bits;
167 uint32_t chunk_ecc_size_in_bits;
168 uint32_t chunk_total_size_in_bits;
169 uint32_t block_mark_chunk_number;
170 uint32_t block_mark_chunk_bit_offset;
171 uint32_t block_mark_bit_offset;
173 chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
174 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
176 chunk_total_size_in_bits =
177 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
179 /* Compute the bit offset of the block mark within the physical page. */
180 block_mark_bit_offset = page_data_size * 8;
182 /* Subtract the metadata bits. */
183 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
186 * Compute the chunk number (starting at zero) in which the block mark
189 block_mark_chunk_number =
190 block_mark_bit_offset / chunk_total_size_in_bits;
193 * Compute the bit offset of the block mark within its chunk, and
196 block_mark_chunk_bit_offset = block_mark_bit_offset -
197 (block_mark_chunk_number * chunk_total_size_in_bits);
199 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
203 * Now that we know the chunk number in which the block mark appears,
204 * we can subtract all the ECC bits that appear before it.
206 block_mark_bit_offset -=
207 block_mark_chunk_number * chunk_ecc_size_in_bits;
209 return block_mark_bit_offset;
212 static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
214 uint32_t ecc_strength;
215 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
216 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
219 static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
221 uint32_t ecc_strength;
222 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
223 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
227 * Wait for BCH complete IRQ and clear the IRQ
229 static int mxs_nand_wait_for_bch_complete(void)
231 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
232 int timeout = MXS_NAND_BCH_TIMEOUT;
235 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
236 BCH_CTRL_COMPLETE_IRQ, timeout);
238 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
244 * This is the function that we install in the cmd_ctrl function pointer of the
245 * owning struct nand_chip. The only functions in the reference implementation
246 * that use these functions pointers are cmdfunc and select_chip.
248 * In this driver, we implement our own select_chip, so this function will only
249 * be called by the reference implementation's cmdfunc. For this reason, we can
250 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
253 static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
255 struct nand_chip *nand = mtd->priv;
256 struct mxs_nand_info *nand_info = nand->priv;
257 struct mxs_dma_desc *d;
258 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
262 * If this condition is true, something is _VERY_ wrong in MTD
265 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
266 printf("MXS NAND: Command queue too long\n");
271 * Every operation begins with a command byte and a series of zero or
272 * more address bytes. These are distinguished by either the Address
273 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
274 * asserted. When MTD is ready to execute the command, it will
275 * deasert both latch enables.
277 * Rather than run a separate DMA operation for every single byte, we
278 * queue them up and run a single DMA operation for the entire series
279 * of command and data bytes.
281 if (ctrl & (NAND_ALE | NAND_CLE)) {
282 if (data != NAND_CMD_NONE)
283 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
288 * If control arrives here, MTD has deasserted both the ALE and CLE,
289 * which means it's ready to run an operation. Check if we have any
292 if (nand_info->cmd_queue_len == 0)
295 /* Compile the DMA descriptor -- a descriptor that sends command. */
296 d = mxs_nand_get_dma_desc(nand_info);
298 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
299 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
300 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
301 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
303 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
305 d->cmd.pio_words[0] =
306 GPMI_CTRL0_COMMAND_MODE_WRITE |
307 GPMI_CTRL0_WORD_LENGTH |
308 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
309 GPMI_CTRL0_ADDRESS_NAND_CLE |
310 GPMI_CTRL0_ADDRESS_INCREMENT |
311 nand_info->cmd_queue_len;
313 mxs_dma_desc_append(channel, d);
316 mxs_nand_flush_cmd_buf(nand_info);
318 /* Execute the DMA chain. */
319 ret = mxs_dma_go(channel);
321 printf("MXS NAND: Error sending command\n");
323 mxs_nand_return_dma_descs(nand_info);
325 /* Reset the command queue. */
326 nand_info->cmd_queue_len = 0;
330 * Test if the NAND flash is ready.
332 static int mxs_nand_device_ready(struct mtd_info *mtd)
334 struct nand_chip *chip = mtd->priv;
335 struct mxs_nand_info *nand_info = chip->priv;
336 struct mxs_gpmi_regs *gpmi_regs =
337 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
340 tmp = readl(&gpmi_regs->hw_gpmi_stat);
341 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
347 * Select the NAND chip.
349 static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
351 struct nand_chip *nand = mtd->priv;
352 struct mxs_nand_info *nand_info = nand->priv;
354 nand_info->cur_chip = chip;
358 * Handle block mark swapping.
360 * Note that, when this function is called, it doesn't know whether it's
361 * swapping the block mark, or swapping it *back* -- but it doesn't matter
362 * because the the operation is the same.
364 static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
365 uint8_t *data_buf, uint8_t *oob_buf)
373 bit_offset = mxs_nand_mark_bit_offset(mtd);
374 buf_offset = mxs_nand_mark_byte_offset(mtd);
377 * Get the byte from the data area that overlays the block mark. Since
378 * the ECC engine applies its own view to the bits in the page, the
379 * physical block mark won't (in general) appear on a byte boundary in
382 src = data_buf[buf_offset] >> bit_offset;
383 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
389 data_buf[buf_offset] &= ~(0xff << bit_offset);
390 data_buf[buf_offset + 1] &= 0xff << bit_offset;
392 data_buf[buf_offset] |= dst << bit_offset;
393 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
397 * Read data from NAND.
399 static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
401 struct nand_chip *nand = mtd->priv;
402 struct mxs_nand_info *nand_info = nand->priv;
403 struct mxs_dma_desc *d;
404 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
407 if (length > NAND_MAX_PAGESIZE) {
408 printf("MXS NAND: DMA buffer too big\n");
413 printf("MXS NAND: DMA buffer is NULL\n");
417 /* Compile the DMA descriptor - a descriptor that reads data. */
418 d = mxs_nand_get_dma_desc(nand_info);
420 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
421 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
422 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
423 (length << MXS_DMA_DESC_BYTES_OFFSET);
425 d->cmd.address = (dma_addr_t)nand_info->data_buf;
427 d->cmd.pio_words[0] =
428 GPMI_CTRL0_COMMAND_MODE_READ |
429 GPMI_CTRL0_WORD_LENGTH |
430 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
431 GPMI_CTRL0_ADDRESS_NAND_DATA |
434 mxs_dma_desc_append(channel, d);
437 * A DMA descriptor that waits for the command to end and the chip to
440 * I think we actually should *not* be waiting for the chip to become
441 * ready because, after all, we don't care. I think the original code
442 * did that and no one has re-thought it yet.
444 d = mxs_nand_get_dma_desc(nand_info);
446 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
447 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
448 MXS_DMA_DESC_WAIT4END | (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
452 d->cmd.pio_words[0] =
453 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
454 GPMI_CTRL0_WORD_LENGTH |
455 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
456 GPMI_CTRL0_ADDRESS_NAND_DATA;
458 mxs_dma_desc_append(channel, d);
460 /* Execute the DMA chain. */
461 ret = mxs_dma_go(channel);
463 printf("MXS NAND: DMA read error\n");
467 /* Invalidate caches */
468 mxs_nand_inval_data_buf(nand_info);
470 memcpy(buf, nand_info->data_buf, length);
473 mxs_nand_return_dma_descs(nand_info);
477 * Write data to NAND.
479 static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
482 struct nand_chip *nand = mtd->priv;
483 struct mxs_nand_info *nand_info = nand->priv;
484 struct mxs_dma_desc *d;
485 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
488 if (length > NAND_MAX_PAGESIZE) {
489 printf("MXS NAND: DMA buffer too big\n");
494 printf("MXS NAND: DMA buffer is NULL\n");
498 memcpy(nand_info->data_buf, buf, length);
500 /* Compile the DMA descriptor - a descriptor that writes data. */
501 d = mxs_nand_get_dma_desc(nand_info);
503 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
504 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
505 (4 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
506 (length << MXS_DMA_DESC_BYTES_OFFSET);
508 d->cmd.address = (dma_addr_t)nand_info->data_buf;
510 d->cmd.pio_words[0] =
511 GPMI_CTRL0_COMMAND_MODE_WRITE |
512 GPMI_CTRL0_WORD_LENGTH |
513 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
514 GPMI_CTRL0_ADDRESS_NAND_DATA |
517 mxs_dma_desc_append(channel, d);
520 mxs_nand_flush_data_buf(nand_info);
522 /* Execute the DMA chain. */
523 ret = mxs_dma_go(channel);
525 printf("MXS NAND: DMA write error\n");
527 mxs_nand_return_dma_descs(nand_info);
531 * Read a single byte from NAND.
533 static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
536 mxs_nand_read_buf(mtd, &buf, 1);
541 * Read a page from NAND.
543 static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
544 uint8_t *buf, int oob_required,
547 struct mxs_nand_info *nand_info = nand->priv;
548 struct mxs_dma_desc *d;
549 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
550 uint32_t corrected = 0, failed = 0;
554 /* Compile the DMA descriptor - wait for ready. */
555 d = mxs_nand_get_dma_desc(nand_info);
557 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
558 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
559 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
563 d->cmd.pio_words[0] =
564 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
565 GPMI_CTRL0_WORD_LENGTH |
566 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
567 GPMI_CTRL0_ADDRESS_NAND_DATA;
569 mxs_dma_desc_append(channel, d);
571 /* Compile the DMA descriptor - enable the BCH block and read. */
572 d = mxs_nand_get_dma_desc(nand_info);
574 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
575 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
579 d->cmd.pio_words[0] =
580 GPMI_CTRL0_COMMAND_MODE_READ |
581 GPMI_CTRL0_WORD_LENGTH |
582 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
583 GPMI_CTRL0_ADDRESS_NAND_DATA |
584 (mtd->writesize + mtd->oobsize);
585 d->cmd.pio_words[1] = 0;
586 d->cmd.pio_words[2] =
587 GPMI_ECCCTRL_ENABLE_ECC |
588 GPMI_ECCCTRL_ECC_CMD_DECODE |
589 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
590 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
591 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
592 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
594 mxs_dma_desc_append(channel, d);
596 /* Compile the DMA descriptor - disable the BCH block. */
597 d = mxs_nand_get_dma_desc(nand_info);
599 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
600 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
601 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
605 d->cmd.pio_words[0] =
606 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
607 GPMI_CTRL0_WORD_LENGTH |
608 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
609 GPMI_CTRL0_ADDRESS_NAND_DATA |
610 (mtd->writesize + mtd->oobsize);
611 d->cmd.pio_words[1] = 0;
612 d->cmd.pio_words[2] = 0;
614 mxs_dma_desc_append(channel, d);
616 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
617 d = mxs_nand_get_dma_desc(nand_info);
619 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
620 MXS_DMA_DESC_DEC_SEM;
624 mxs_dma_desc_append(channel, d);
626 /* Execute the DMA chain. */
627 ret = mxs_dma_go(channel);
629 printf("MXS NAND: DMA read error\n");
633 ret = mxs_nand_wait_for_bch_complete();
635 printf("MXS NAND: BCH read timeout\n");
639 /* Invalidate caches */
640 mxs_nand_inval_data_buf(nand_info);
642 /* Read DMA completed, now do the mark swapping. */
643 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
645 /* Loop over status bytes, accumulating ECC status. */
646 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
647 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
648 if (status[i] == 0x00)
651 if (status[i] == 0xff)
654 if (status[i] == 0xfe) {
659 corrected += status[i];
662 /* Propagate ECC status to the owning MTD. */
663 mtd->ecc_stats.failed += failed;
664 mtd->ecc_stats.corrected += corrected;
667 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
668 * details about our policy for delivering the OOB.
670 * We fill the caller's buffer with set bits, and then copy the block
671 * mark to the caller's buffer. Note that, if block mark swapping was
672 * necessary, it has already been done, so we can rely on the first
673 * byte of the auxiliary buffer to contain the block mark.
675 memset(nand->oob_poi, 0xff, mtd->oobsize);
677 nand->oob_poi[0] = nand_info->oob_buf[0];
679 memcpy(buf, nand_info->data_buf, mtd->writesize);
682 mxs_nand_return_dma_descs(nand_info);
688 * Write a page to NAND.
690 static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
691 struct nand_chip *nand, const uint8_t *buf,
694 struct mxs_nand_info *nand_info = nand->priv;
695 struct mxs_dma_desc *d;
696 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
699 memcpy(nand_info->data_buf, buf, mtd->writesize);
700 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
702 /* Handle block mark swapping. */
703 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
705 /* Compile the DMA descriptor - write data. */
706 d = mxs_nand_get_dma_desc(nand_info);
708 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
709 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
710 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
714 d->cmd.pio_words[0] =
715 GPMI_CTRL0_COMMAND_MODE_WRITE |
716 GPMI_CTRL0_WORD_LENGTH |
717 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
718 GPMI_CTRL0_ADDRESS_NAND_DATA;
719 d->cmd.pio_words[1] = 0;
720 d->cmd.pio_words[2] =
721 GPMI_ECCCTRL_ENABLE_ECC |
722 GPMI_ECCCTRL_ECC_CMD_ENCODE |
723 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
724 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
725 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
726 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
728 mxs_dma_desc_append(channel, d);
731 mxs_nand_flush_data_buf(nand_info);
733 /* Execute the DMA chain. */
734 ret = mxs_dma_go(channel);
736 printf("MXS NAND: DMA write error\n");
740 ret = mxs_nand_wait_for_bch_complete();
742 printf("MXS NAND: BCH write timeout\n");
747 mxs_nand_return_dma_descs(nand_info);
752 * Read OOB from NAND.
754 * This function is a veneer that replaces the function originally installed by
755 * the NAND Flash MTD code.
757 static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
758 struct mtd_oob_ops *ops)
760 struct nand_chip *chip = mtd->priv;
761 struct mxs_nand_info *nand_info = chip->priv;
764 if (ops->mode == MTD_OPS_RAW)
765 nand_info->raw_oob_mode = 1;
767 nand_info->raw_oob_mode = 0;
769 ret = nand_info->hooked_read_oob(mtd, from, ops);
771 nand_info->raw_oob_mode = 0;
779 * This function is a veneer that replaces the function originally installed by
780 * the NAND Flash MTD code.
782 static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
783 struct mtd_oob_ops *ops)
785 struct nand_chip *chip = mtd->priv;
786 struct mxs_nand_info *nand_info = chip->priv;
789 if (ops->mode == MTD_OPS_RAW)
790 nand_info->raw_oob_mode = 1;
792 nand_info->raw_oob_mode = 0;
794 ret = nand_info->hooked_write_oob(mtd, to, ops);
796 nand_info->raw_oob_mode = 0;
802 * Mark a block bad in NAND.
804 * This function is a veneer that replaces the function originally installed by
805 * the NAND Flash MTD code.
807 static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
809 struct nand_chip *chip = mtd->priv;
810 struct mxs_nand_info *nand_info = chip->priv;
813 nand_info->marking_block_bad = 1;
815 ret = nand_info->hooked_block_markbad(mtd, ofs);
817 nand_info->marking_block_bad = 0;
823 * There are several places in this driver where we have to handle the OOB and
824 * block marks. This is the function where things are the most complicated, so
825 * this is where we try to explain it all. All the other places refer back to
828 * These are the rules, in order of decreasing importance:
830 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
831 * write operations take measures to protect it.
833 * 2) In read operations, the first byte of the OOB we return must reflect the
834 * true state of the block mark, no matter where that block mark appears in
837 * 3) ECC-based read operations return an OOB full of set bits (since we never
838 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
841 * 4) "Raw" read operations return a direct view of the physical bytes in the
842 * page, using the conventional definition of which bytes are data and which
843 * are OOB. This gives the caller a way to see the actual, physical bytes
844 * in the page, without the distortions applied by our ECC engine.
846 * What we do for this specific read operation depends on whether we're doing
847 * "raw" read, or an ECC-based read.
849 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
850 * easy. When reading a page, for example, the NAND Flash MTD code calls our
851 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
852 * ECC-based or raw view of the page is implicit in which function it calls
853 * (there is a similar pair of ECC-based/raw functions for writing).
855 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
856 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
857 * caller wants an ECC-based or raw view of the page is not propagated down to
860 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
861 * ecc.read_oob and ecc.write_oob function pointers in the owning
862 * struct mtd_info with our own functions. These hook functions set the
863 * raw_oob_mode field so that, when control finally arrives here, we'll know
866 static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
869 struct mxs_nand_info *nand_info = nand->priv;
872 * First, fill in the OOB buffer. If we're doing a raw read, we need to
873 * get the bytes from the physical page. If we're not doing a raw read,
874 * we need to fill the buffer with set bits.
876 if (nand_info->raw_oob_mode) {
878 * If control arrives here, we're doing a "raw" read. Send the
879 * command to read the conventional OOB and read it.
881 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
882 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
885 * If control arrives here, we're not doing a "raw" read. Fill
886 * the OOB buffer with set bits and correct the block mark.
888 memset(nand->oob_poi, 0xff, mtd->oobsize);
890 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
891 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
899 * Write OOB data to NAND.
901 static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
904 struct mxs_nand_info *nand_info = nand->priv;
905 uint8_t block_mark = 0;
908 * There are fundamental incompatibilities between the i.MX GPMI NFC and
909 * the NAND Flash MTD model that make it essentially impossible to write
910 * the out-of-band bytes.
912 * We permit *ONE* exception. If the *intent* of writing the OOB is to
913 * mark a block bad, we can do that.
916 if (!nand_info->marking_block_bad) {
917 printf("NXS NAND: Writing OOB isn't supported\n");
921 /* Write the block mark. */
922 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
923 nand->write_buf(mtd, &block_mark, 1);
924 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
926 /* Check if it worked. */
927 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
934 * Claims all blocks are good.
936 * In principle, this function is *only* called when the NAND Flash MTD system
937 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
938 * the driver for bad block information.
940 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
941 * this function is *only* called when we take it away.
943 * Thus, this function is only called when we want *all* blocks to look good,
944 * so it *always* return success.
946 static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
952 * Nominally, the purpose of this function is to look for or create the bad
953 * block table. In fact, since the we call this function at the very end of
954 * the initialization process started by nand_scan(), and we doesn't have a
955 * more formal mechanism, we "hook" this function to continue init process.
957 * At this point, the physical NAND Flash chips have been identified and
958 * counted, so we know the physical geometry. This enables us to make some
959 * important configuration decisions.
961 * The return value of this function propogates directly back to this driver's
962 * call to nand_scan(). Anything other than zero will cause this driver to
963 * tear everything down and declare failure.
965 static int mxs_nand_scan_bbt(struct mtd_info *mtd)
967 struct nand_chip *nand = mtd->priv;
968 struct mxs_nand_info *nand_info = nand->priv;
969 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
972 /* Configure BCH and set NFC geometry */
973 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
975 /* Configure layout 0 */
976 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
977 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
978 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
979 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
980 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
981 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
982 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
983 writel(tmp, &bch_regs->hw_bch_flash0layout0);
985 tmp = (mtd->writesize + mtd->oobsize)
986 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
987 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
988 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
989 tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
990 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
991 writel(tmp, &bch_regs->hw_bch_flash0layout1);
993 /* Set *all* chip selects to use layout 0 */
994 writel(0, &bch_regs->hw_bch_layoutselect);
996 /* Enable BCH complete interrupt */
997 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
999 /* Hook some operations at the MTD level. */
1000 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1001 nand_info->hooked_read_oob = mtd->_read_oob;
1002 mtd->_read_oob = mxs_nand_hook_read_oob;
1005 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1006 nand_info->hooked_write_oob = mtd->_write_oob;
1007 mtd->_write_oob = mxs_nand_hook_write_oob;
1010 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1011 nand_info->hooked_block_markbad = mtd->_block_markbad;
1012 mtd->_block_markbad = mxs_nand_hook_block_markbad;
1015 /* We use the reference implementation for bad block management. */
1016 return nand_default_bbt(mtd);
1020 * Allocate DMA buffers
1022 int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1025 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1027 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1030 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
1032 printf("MXS NAND: Error allocating DMA buffers\n");
1036 memset(buf, 0, nand_info->data_buf_size);
1038 nand_info->data_buf = buf;
1039 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
1040 /* Command buffers */
1041 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1042 MXS_NAND_COMMAND_BUFFER_SIZE);
1043 if (!nand_info->cmd_buf) {
1045 printf("MXS NAND: Error allocating command buffers\n");
1048 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1049 nand_info->cmd_queue_len = 0;
1055 * Initializes the NFC hardware.
1057 int mxs_nand_init(struct mxs_nand_info *info)
1059 struct mxs_gpmi_regs *gpmi_regs =
1060 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
1061 struct mxs_bch_regs *bch_regs =
1062 (struct mxs_bch_regs *)MXS_BCH_BASE;
1065 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1066 MXS_NAND_DMA_DESCRIPTOR_COUNT);
1070 /* Allocate the DMA descriptors. */
1071 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1072 info->desc[i] = mxs_dma_desc_alloc();
1077 /* Init the DMA controller. */
1078 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1079 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
1080 if (mxs_dma_init_channel(j))
1084 /* Reset the GPMI block. */
1085 mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
1086 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
1089 * Choose NAND mode, set IRQ polarity, disable write protection and
1092 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
1093 GPMI_CTRL1_GPMI_MODE,
1094 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1095 GPMI_CTRL1_BCH_MODE);
1100 for (--j; j >= 0; j--)
1105 for (--i; i >= 0; i--)
1106 mxs_dma_desc_free(info->desc[i]);
1107 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1112 * This function is called during the driver binding process.
1114 * @param pdev the device structure used to store device specific
1115 * information that is used by the suspend, resume and
1118 * @return The function always returns 0.
1120 int board_nand_init(struct nand_chip *nand)
1122 struct mxs_nand_info *nand_info;
1125 nand_info = malloc(sizeof(struct mxs_nand_info));
1127 printf("MXS NAND: Failed to allocate private data\n");
1130 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1132 err = mxs_nand_alloc_buffers(nand_info);
1136 err = mxs_nand_init(nand_info);
1140 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1142 nand->priv = nand_info;
1143 nand->options |= NAND_NO_SUBPAGE_WRITE;
1145 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1147 nand->dev_ready = mxs_nand_device_ready;
1148 nand->select_chip = mxs_nand_select_chip;
1149 nand->block_bad = mxs_nand_block_bad;
1150 nand->scan_bbt = mxs_nand_scan_bbt;
1152 nand->read_byte = mxs_nand_read_byte;
1154 nand->read_buf = mxs_nand_read_buf;
1155 nand->write_buf = mxs_nand_write_buf;
1157 nand->ecc.read_page = mxs_nand_ecc_read_page;
1158 nand->ecc.write_page = mxs_nand_ecc_write_page;
1159 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1160 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1162 nand->ecc.layout = &fake_ecc_layout;
1163 nand->ecc.mode = NAND_ECC_HW;
1164 nand->ecc.bytes = 9;
1165 nand->ecc.size = 512;
1166 nand->ecc.strength = 8;
1171 free(nand_info->data_buf);
1172 free(nand_info->cmd_buf);