2 * Copyright 2004-2007 Freescale Semiconductor, Inc.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
23 #include <linux/err.h>
25 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35)
26 #include <asm/arch/imx-regs.h>
30 #define DRIVER_NAME "mxc_nand"
32 struct mxc_nand_host {
34 struct nand_chip *nand;
36 struct fsl_nfc_regs __iomem *regs;
42 unsigned int page_addr;
45 static struct mxc_nand_host mxc_host;
46 static struct mxc_nand_host *host = &mxc_host;
48 /* Define delays in microsec for NAND device operations */
49 #define TROP_US_DELAY 2000
50 /* Macros to get byte and bit positions of ECC */
51 #define COLPOS(x) ((x) >> 3)
52 #define BITPOS(x) ((x) & 0xf)
54 /* Define single bit Error positions in Main & Spare area */
55 #define MAIN_SINGLEBIT_ERROR 0x4
56 #define SPARE_SINGLEBIT_ERROR 0x1
58 /* OOB placement block for use with hardware ecc generation */
59 #if defined(MXC_NFC_V1)
60 #ifndef CONFIG_SYS_NAND_LARGEPAGE
61 static struct nand_ecclayout nand_hw_eccoob = {
63 .eccpos = {6, 7, 8, 9, 10},
64 .oobfree = { {0, 5}, {11, 5}, }
67 static struct nand_ecclayout nand_hw_eccoob2k = {
75 .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
78 #elif defined(MXC_NFC_V2_1)
79 #ifndef CONFIG_SYS_NAND_LARGEPAGE
80 static struct nand_ecclayout nand_hw_eccoob = {
82 .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
86 static struct nand_ecclayout nand_hw_eccoob2k = {
89 7, 8, 9, 10, 11, 12, 13, 14, 15,
90 23, 24, 25, 26, 27, 28, 29, 30, 31,
91 39, 40, 41, 42, 43, 44, 45, 46, 47,
92 55, 56, 57, 58, 59, 60, 61, 62, 63,
94 .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
100 static int is_16bit_nand(void)
102 struct system_control_regs *sc_regs =
103 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
105 if (readl(&sc_regs->fmcr) & NF_16BIT_SEL)
110 #elif defined(CONFIG_MX31)
111 static int is_16bit_nand(void)
113 struct clock_control_regs *sc_regs =
114 (struct clock_control_regs *)CCM_BASE;
116 if (readl(&sc_regs->rcsr) & CCM_RCSR_NF16B)
121 #elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
122 static int is_16bit_nand(void)
124 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
126 if (readl(&ccm->rcsr) & CCM_RCSR_NF_16BIT_SEL)
132 #warning "8/16 bit NAND autodetection not supported"
133 static int is_16bit_nand(void)
139 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
145 __raw_writel(__raw_readl(source++), d++);
150 * This function polls the NANDFC to wait for the basic operation to
151 * complete by checking the INT bit of config2 register.
153 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
158 while (max_retries-- > 0) {
159 if (readw(&host->regs->config2) & NFC_INT) {
160 tmp = readw(&host->regs->config2);
162 writew(tmp, &host->regs->config2);
167 if (max_retries < 0) {
168 MTDDEBUG(MTD_DEBUG_LEVEL0, "%s(%d): INT not set\n",
174 * This function issues the specified command to the NAND device and
175 * waits for completion.
177 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
179 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x)\n", cmd);
181 writew(cmd, &host->regs->flash_cmd);
182 writew(NFC_CMD, &host->regs->config2);
184 /* Wait for operation to complete */
185 wait_op_done(host, TROP_US_DELAY, cmd);
189 * This function sends an address (or partial address) to the
190 * NAND device. The address is used to select the source/destination for
193 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
195 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x)\n", addr);
197 writew(addr, &host->regs->flash_addr);
198 writew(NFC_ADDR, &host->regs->config2);
200 /* Wait for operation to complete */
201 wait_op_done(host, TROP_US_DELAY, addr);
205 * This function requests the NANDFC to initiate the transfer
206 * of data currently in the NANDFC RAM buffer to the NAND device.
208 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
212 MTDDEBUG(MTD_DEBUG_LEVEL1, "send_prog_page (%d)\n", spare_only);
214 if (is_mxc_nfc_21()) {
217 * The controller copies the 64 bytes of spare data from
218 * the first 16 bytes of each of the 4 64 byte spare buffers.
219 * Copy the contiguous data starting in spare_area[0] to
220 * the four spare area buffers.
222 for (i = 1; i < 4; i++) {
223 void __iomem *src = &host->regs->spare_area[0][i * 16];
224 void __iomem *dst = &host->regs->spare_area[i][0];
226 mxc_nand_memcpy32(dst, src, 16);
230 writew(buf_id, &host->regs->buf_addr);
232 /* Configure spare or page+spare access */
233 if (!host->pagesize_2k) {
234 uint16_t config1 = readw(&host->regs->config1);
236 config1 |= NFC_SP_EN;
238 config1 &= ~NFC_SP_EN;
239 writew(config1, &host->regs->config1);
242 writew(NFC_INPUT, &host->regs->config2);
244 /* Wait for operation to complete */
245 wait_op_done(host, TROP_US_DELAY, spare_only);
249 * Requests NANDFC to initiate the transfer of data from the
250 * NAND device into in the NANDFC ram buffer.
252 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
255 MTDDEBUG(MTD_DEBUG_LEVEL3, "send_read_page (%d)\n", spare_only);
257 writew(buf_id, &host->regs->buf_addr);
259 /* Configure spare or page+spare access */
260 if (!host->pagesize_2k) {
261 uint32_t config1 = readw(&host->regs->config1);
263 config1 |= NFC_SP_EN;
265 config1 &= ~NFC_SP_EN;
266 writew(config1, &host->regs->config1);
269 writew(NFC_OUTPUT, &host->regs->config2);
271 /* Wait for operation to complete */
272 wait_op_done(host, TROP_US_DELAY, spare_only);
274 if (is_mxc_nfc_21()) {
278 * The controller copies the 64 bytes of spare data to
279 * the first 16 bytes of each of the 4 spare buffers.
280 * Make the data contiguous starting in spare_area[0].
282 for (i = 1; i < 4; i++) {
283 void __iomem *src = &host->regs->spare_area[i][0];
284 void __iomem *dst = &host->regs->spare_area[0][i * 16];
286 mxc_nand_memcpy32(dst, src, 16);
291 /* Request the NANDFC to perform a read of the NAND device ID. */
292 static void send_read_id(struct mxc_nand_host *host)
296 /* NANDFC buffer 0 is used for device ID output */
297 writew(0x0, &host->regs->buf_addr);
299 /* Read ID into main buffer */
300 tmp = readw(&host->regs->config1);
302 writew(tmp, &host->regs->config1);
304 writew(NFC_ID, &host->regs->config2);
306 /* Wait for operation to complete */
307 wait_op_done(host, TROP_US_DELAY, 0);
311 * This function requests the NANDFC to perform a read of the
312 * NAND device status and returns the current status.
314 static uint16_t get_dev_status(struct mxc_nand_host *host)
316 void __iomem *main_buf = host->regs->main_area[1];
319 /* Issue status request to NAND device */
321 /* store the main area1 first word, later do recovery */
322 store = readl(main_buf);
323 /* NANDFC buffer 1 is used for device status */
324 writew(1, &host->regs->buf_addr);
326 /* Read status into main buffer */
327 tmp = readw(&host->regs->config1);
329 writew(tmp, &host->regs->config1);
331 writew(NFC_STATUS, &host->regs->config2);
333 /* Wait for operation to complete */
334 wait_op_done(host, TROP_US_DELAY, 0);
337 * Status is placed in first word of main buffer
338 * get status, then recovery area 1 data
340 ret = readw(main_buf);
341 writel(store, main_buf);
346 /* This function is used by upper layer to checks if device is ready */
347 static int mxc_nand_dev_ready(struct mtd_info *mtd)
350 * NFC handles R/B internally. Therefore, this function
351 * always returns status as ready.
356 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
358 struct nand_chip *nand_chip = mtd->priv;
359 struct mxc_nand_host *host = nand_chip->priv;
360 uint16_t tmp = readw(&host->regs->config1);
366 writew(tmp, &host->regs->config1);
369 #ifdef CONFIG_MXC_NAND_HWECC
370 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
373 * If HW ECC is enabled, we turn it on during init. There is
374 * no need to enable again here.
379 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
380 struct nand_chip *chip,
381 int page, int sndcmd)
383 struct mxc_nand_host *host = chip->priv;
384 uint8_t *buf = chip->oob_poi;
385 int length = mtd->oobsize;
386 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
387 uint8_t *bufpoi = buf;
390 MTDDEBUG(MTD_DEBUG_LEVEL0,
391 "%s: Reading OOB area of page %u to oob %p\n",
392 __FUNCTION__, host->page_addr, buf);
394 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
395 for (i = 0; i < chip->ecc.steps; i++) {
396 toread = min_t(int, length, chip->ecc.prepad);
398 chip->read_buf(mtd, bufpoi, toread);
402 bufpoi += chip->ecc.bytes;
403 host->col_addr += chip->ecc.bytes;
404 length -= chip->ecc.bytes;
406 toread = min_t(int, length, chip->ecc.postpad);
408 chip->read_buf(mtd, bufpoi, toread);
414 chip->read_buf(mtd, bufpoi, length);
416 _mxc_nand_enable_hwecc(mtd, 0);
417 chip->cmdfunc(mtd, NAND_CMD_READOOB,
418 mtd->writesize + chip->ecc.prepad, page);
419 bufpoi = buf + chip->ecc.prepad;
420 length = mtd->oobsize - chip->ecc.prepad;
421 for (i = 0; i < chip->ecc.steps; i++) {
422 toread = min_t(int, length, chip->ecc.bytes);
423 chip->read_buf(mtd, bufpoi, toread);
426 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
428 _mxc_nand_enable_hwecc(mtd, 1);
432 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
433 struct nand_chip *chip,
437 struct mxc_nand_host *host = chip->priv;
438 int eccsize = chip->ecc.size;
439 int eccbytes = chip->ecc.bytes;
440 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
441 uint8_t *oob = chip->oob_poi;
445 _mxc_nand_enable_hwecc(mtd, 0);
446 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, host->page_addr);
448 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
449 host->col_addr = n * eccsize;
450 chip->read_buf(mtd, buf, eccsize);
453 host->col_addr = mtd->writesize + n * eccpitch;
454 if (chip->ecc.prepad) {
455 chip->read_buf(mtd, oob, chip->ecc.prepad);
456 oob += chip->ecc.prepad;
459 chip->read_buf(mtd, oob, eccbytes);
462 if (chip->ecc.postpad) {
463 chip->read_buf(mtd, oob, chip->ecc.postpad);
464 oob += chip->ecc.postpad;
468 size = mtd->oobsize - (oob - chip->oob_poi);
470 chip->read_buf(mtd, oob, size);
471 _mxc_nand_enable_hwecc(mtd, 1);
476 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
477 struct nand_chip *chip,
481 struct mxc_nand_host *host = chip->priv;
482 int n, eccsize = chip->ecc.size;
483 int eccbytes = chip->ecc.bytes;
484 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
485 int eccsteps = chip->ecc.steps;
487 uint8_t *oob = chip->oob_poi;
489 MTDDEBUG(MTD_DEBUG_LEVEL1, "Reading page %u to buf %p oob %p\n",
490 host->page_addr, buf, oob);
492 /* first read the data area and the available portion of OOB */
493 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
496 host->col_addr = n * eccsize;
498 chip->read_buf(mtd, p, eccsize);
500 host->col_addr = mtd->writesize + n * eccpitch;
502 if (chip->ecc.prepad) {
503 chip->read_buf(mtd, oob, chip->ecc.prepad);
504 oob += chip->ecc.prepad;
507 stat = chip->ecc.correct(mtd, p, oob, NULL);
510 mtd->ecc_stats.failed++;
512 mtd->ecc_stats.corrected += stat;
515 if (chip->ecc.postpad) {
516 chip->read_buf(mtd, oob, chip->ecc.postpad);
517 oob += chip->ecc.postpad;
521 /* Calculate remaining oob bytes */
522 n = mtd->oobsize - (oob - chip->oob_poi);
524 chip->read_buf(mtd, oob, n);
526 /* Then switch ECC off and read the OOB area to get the ECC code */
527 _mxc_nand_enable_hwecc(mtd, 0);
528 chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, host->page_addr);
529 eccsteps = chip->ecc.steps;
530 oob = chip->oob_poi + chip->ecc.prepad;
531 for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
532 host->col_addr = mtd->writesize +
535 chip->read_buf(mtd, oob, eccbytes);
536 oob += eccbytes + chip->ecc.postpad;
538 _mxc_nand_enable_hwecc(mtd, 1);
542 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
543 struct nand_chip *chip, int page)
545 struct mxc_nand_host *host = chip->priv;
546 int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
547 int length = mtd->oobsize;
548 int i, len, status, steps = chip->ecc.steps;
549 const uint8_t *bufpoi = chip->oob_poi;
551 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
552 for (i = 0; i < steps; i++) {
553 len = min_t(int, length, eccpitch);
555 chip->write_buf(mtd, bufpoi, len);
558 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
561 chip->write_buf(mtd, bufpoi, length);
563 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
564 status = chip->waitfunc(mtd, chip);
565 return status & NAND_STATUS_FAIL ? -EIO : 0;
568 static void mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
569 struct nand_chip *chip,
572 struct mxc_nand_host *host = chip->priv;
573 int eccsize = chip->ecc.size;
574 int eccbytes = chip->ecc.bytes;
575 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
576 uint8_t *oob = chip->oob_poi;
580 for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
581 host->col_addr = n * eccsize;
582 chip->write_buf(mtd, buf, eccsize);
585 host->col_addr = mtd->writesize + n * eccpitch;
587 if (chip->ecc.prepad) {
588 chip->write_buf(mtd, oob, chip->ecc.prepad);
589 oob += chip->ecc.prepad;
592 host->col_addr += eccbytes;
595 if (chip->ecc.postpad) {
596 chip->write_buf(mtd, oob, chip->ecc.postpad);
597 oob += chip->ecc.postpad;
601 size = mtd->oobsize - (oob - chip->oob_poi);
603 chip->write_buf(mtd, oob, size);
606 static void mxc_nand_write_page_syndrome(struct mtd_info *mtd,
607 struct nand_chip *chip,
610 struct mxc_nand_host *host = chip->priv;
611 int i, n, eccsize = chip->ecc.size;
612 int eccbytes = chip->ecc.bytes;
613 int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
614 int eccsteps = chip->ecc.steps;
615 const uint8_t *p = buf;
616 uint8_t *oob = chip->oob_poi;
618 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
622 n++, eccsteps--, i += eccbytes, p += eccsize) {
623 host->col_addr = n * eccsize;
625 chip->write_buf(mtd, p, eccsize);
627 host->col_addr = mtd->writesize + n * eccpitch;
629 if (chip->ecc.prepad) {
630 chip->write_buf(mtd, oob, chip->ecc.prepad);
631 oob += chip->ecc.prepad;
634 chip->write_buf(mtd, oob, eccbytes);
637 if (chip->ecc.postpad) {
638 chip->write_buf(mtd, oob, chip->ecc.postpad);
639 oob += chip->ecc.postpad;
643 /* Calculate remaining oob bytes */
644 i = mtd->oobsize - (oob - chip->oob_poi);
646 chip->write_buf(mtd, oob, i);
649 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
650 u_char *read_ecc, u_char *calc_ecc)
652 struct nand_chip *nand_chip = mtd->priv;
653 struct mxc_nand_host *host = nand_chip->priv;
654 uint32_t ecc_status = readl(&host->regs->ecc_status_result);
655 int subpages = mtd->writesize / nand_chip->subpagesize;
656 int pg2blk_shift = nand_chip->phys_erase_shift -
657 nand_chip->page_shift;
660 if ((ecc_status & 0xf) > 4) {
661 static int last_bad = -1;
663 if (last_bad != host->page_addr >> pg2blk_shift) {
664 last_bad = host->page_addr >> pg2blk_shift;
666 "MXC_NAND: HWECC uncorrectable ECC error"
667 " in block %u page %u subpage %d\n",
668 last_bad, host->page_addr,
669 mtd->writesize / nand_chip->subpagesize
676 } while (subpages > 0);
681 #define mxc_nand_read_page_syndrome NULL
682 #define mxc_nand_read_page_raw_syndrome NULL
683 #define mxc_nand_read_oob_syndrome NULL
684 #define mxc_nand_write_page_syndrome NULL
685 #define mxc_nand_write_page_raw_syndrome NULL
686 #define mxc_nand_write_oob_syndrome NULL
688 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
689 u_char *read_ecc, u_char *calc_ecc)
691 struct nand_chip *nand_chip = mtd->priv;
692 struct mxc_nand_host *host = nand_chip->priv;
695 * 1-Bit errors are automatically corrected in HW. No need for
696 * additional correction. 2-Bit errors cannot be corrected by
697 * HW ECC, so we need to return failure
699 uint16_t ecc_status = readw(&host->regs->ecc_status_result);
701 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
702 MTDDEBUG(MTD_DEBUG_LEVEL0,
703 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
711 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
718 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
720 struct nand_chip *nand_chip = mtd->priv;
721 struct mxc_nand_host *host = nand_chip->priv;
724 uint16_t __iomem *main_buf =
725 (uint16_t __iomem *)host->regs->main_area[0];
726 uint16_t __iomem *spare_buf =
727 (uint16_t __iomem *)host->regs->spare_area[0];
733 /* Check for status request */
734 if (host->status_request)
735 return get_dev_status(host) & 0xFF;
737 /* Get column for 16-bit access */
738 col = host->col_addr >> 1;
740 /* If we are accessing the spare region */
741 if (host->spare_only)
742 nfc_word.word = readw(&spare_buf[col]);
744 nfc_word.word = readw(&main_buf[col]);
746 /* Pick upper/lower byte of word from RAM buffer */
747 ret = nfc_word.bytes[host->col_addr & 0x1];
749 /* Update saved column address */
750 if (nand_chip->options & NAND_BUSWIDTH_16)
758 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
760 struct nand_chip *nand_chip = mtd->priv;
761 struct mxc_nand_host *host = nand_chip->priv;
765 MTDDEBUG(MTD_DEBUG_LEVEL3,
766 "mxc_nand_read_word(col = %d)\n", host->col_addr);
768 col = host->col_addr;
769 /* Adjust saved column address */
770 if (col < mtd->writesize && host->spare_only)
771 col += mtd->writesize;
773 if (col < mtd->writesize) {
774 p = (uint16_t __iomem *)(host->regs->main_area[0] +
777 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
778 ((col - mtd->writesize) >> 1));
787 nfc_word[0].word = readw(p);
788 nfc_word[1].word = readw(p + 1);
790 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
791 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
793 ret = nfc_word[2].word;
798 /* Update saved column address */
799 host->col_addr = col + 2;
805 * Write data of length len to buffer buf. The data to be
806 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
807 * Operation by the NFC, the data is written to NAND Flash
809 static void mxc_nand_write_buf(struct mtd_info *mtd,
810 const u_char *buf, int len)
812 struct nand_chip *nand_chip = mtd->priv;
813 struct mxc_nand_host *host = nand_chip->priv;
816 MTDDEBUG(MTD_DEBUG_LEVEL3,
817 "mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
820 col = host->col_addr;
822 /* Adjust saved column address */
823 if (col < mtd->writesize && host->spare_only)
824 col += mtd->writesize;
826 n = mtd->writesize + mtd->oobsize - col;
829 MTDDEBUG(MTD_DEBUG_LEVEL3,
830 "%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
835 if (col < mtd->writesize) {
836 p = host->regs->main_area[0] + (col & ~3);
838 p = host->regs->spare_area[0] -
839 mtd->writesize + (col & ~3);
842 MTDDEBUG(MTD_DEBUG_LEVEL3, "%s:%d: p = %p\n", __func__,
845 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
851 nfc_word.word = readl(p);
852 nfc_word.bytes[col & 3] = buf[i++];
856 writel(nfc_word.word, p);
858 int m = mtd->writesize - col;
860 if (col >= mtd->writesize)
865 MTDDEBUG(MTD_DEBUG_LEVEL3,
866 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
867 __func__, __LINE__, n, m, i, col);
869 mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
875 /* Update saved column address */
876 host->col_addr = col;
880 * Read the data buffer from the NAND Flash. To read the data from NAND
881 * Flash first the data output cycle is initiated by the NFC, which copies
882 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
884 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
886 struct nand_chip *nand_chip = mtd->priv;
887 struct mxc_nand_host *host = nand_chip->priv;
890 MTDDEBUG(MTD_DEBUG_LEVEL3,
891 "mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr, len);
893 col = host->col_addr;
895 /* Adjust saved column address */
896 if (col < mtd->writesize && host->spare_only)
897 col += mtd->writesize;
899 n = mtd->writesize + mtd->oobsize - col;
905 if (col < mtd->writesize) {
906 p = host->regs->main_area[0] + (col & ~3);
908 p = host->regs->spare_area[0] -
909 mtd->writesize + (col & ~3);
912 if (((col | (int)&buf[i]) & 3) || n < 4) {
918 nfc_word.word = readl(p);
919 buf[i++] = nfc_word.bytes[col & 3];
923 int m = mtd->writesize - col;
925 if (col >= mtd->writesize)
929 mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
936 /* Update saved column address */
937 host->col_addr = col;
941 * Used by the upper layer to verify the data in NAND Flash
942 * with the data in the buf.
944 static int mxc_nand_verify_buf(struct mtd_info *mtd,
945 const u_char *buf, int len)
951 bsize = min(len, 256);
952 mxc_nand_read_buf(mtd, tmp, bsize);
954 if (memcmp(buf, tmp, bsize))
965 * This function is used by upper layer for select and
966 * deselect of the NAND chip
968 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
970 struct nand_chip *nand_chip = mtd->priv;
971 struct mxc_nand_host *host = nand_chip->priv;
975 /* TODO: Disable the NFC clock */
980 /* TODO: Enable the NFC clock */
991 * Used by the upper layer to write command to NAND Flash for
992 * different operations to be carried out on NAND Flash
994 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
995 int column, int page_addr)
997 struct nand_chip *nand_chip = mtd->priv;
998 struct mxc_nand_host *host = nand_chip->priv;
1000 MTDDEBUG(MTD_DEBUG_LEVEL3,
1001 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1002 command, column, page_addr);
1004 /* Reset command state information */
1005 host->status_request = false;
1007 /* Command pre-processing step */
1010 case NAND_CMD_STATUS:
1012 host->status_request = true;
1015 case NAND_CMD_READ0:
1016 host->page_addr = page_addr;
1017 host->col_addr = column;
1018 host->spare_only = false;
1021 case NAND_CMD_READOOB:
1022 host->col_addr = column;
1023 host->spare_only = true;
1024 if (host->pagesize_2k)
1025 command = NAND_CMD_READ0; /* only READ0 is valid */
1028 case NAND_CMD_SEQIN:
1029 if (column >= mtd->writesize) {
1031 * before sending SEQIN command for partial write,
1032 * we need read one page out. FSL NFC does not support
1033 * partial write. It always sends out 512+ecc+512+ecc
1034 * for large page nand flash. But for small page nand
1035 * flash, it does support SPARE ONLY operation.
1037 if (host->pagesize_2k) {
1038 /* call ourself to read a page */
1039 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1043 host->col_addr = column - mtd->writesize;
1044 host->spare_only = true;
1046 /* Set program pointer to spare region */
1047 if (!host->pagesize_2k)
1048 send_cmd(host, NAND_CMD_READOOB);
1050 host->spare_only = false;
1051 host->col_addr = column;
1053 /* Set program pointer to page start */
1054 if (!host->pagesize_2k)
1055 send_cmd(host, NAND_CMD_READ0);
1059 case NAND_CMD_PAGEPROG:
1060 send_prog_page(host, 0, host->spare_only);
1062 if (host->pagesize_2k && is_mxc_nfc_1()) {
1063 /* data in 4 areas */
1064 send_prog_page(host, 1, host->spare_only);
1065 send_prog_page(host, 2, host->spare_only);
1066 send_prog_page(host, 3, host->spare_only);
1072 /* Write out the command to the device. */
1073 send_cmd(host, command);
1075 /* Write out column address, if necessary */
1078 * MXC NANDFC can only perform full page+spare or
1079 * spare-only read/write. When the upper layers perform
1080 * a read/write buffer operation, we will use the saved
1081 * column address to index into the full page.
1084 if (host->pagesize_2k)
1085 /* another col addr cycle for 2k page */
1089 /* Write out page address, if necessary */
1090 if (page_addr != -1) {
1091 u32 page_mask = nand_chip->pagemask;
1093 send_addr(host, page_addr & 0xFF);
1096 } while (page_mask);
1099 /* Command post-processing step */
1102 case NAND_CMD_RESET:
1105 case NAND_CMD_READOOB:
1106 case NAND_CMD_READ0:
1107 if (host->pagesize_2k) {
1108 /* send read confirm command */
1109 send_cmd(host, NAND_CMD_READSTART);
1110 /* read for each AREA */
1111 send_read_page(host, 0, host->spare_only);
1112 if (is_mxc_nfc_1()) {
1113 send_read_page(host, 1, host->spare_only);
1114 send_read_page(host, 2, host->spare_only);
1115 send_read_page(host, 3, host->spare_only);
1118 send_read_page(host, 0, host->spare_only);
1122 case NAND_CMD_READID:
1127 case NAND_CMD_PAGEPROG:
1130 case NAND_CMD_STATUS:
1133 case NAND_CMD_ERASE2:
1138 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1140 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1141 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1143 static struct nand_bbt_descr bbt_main_descr = {
1144 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1145 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1150 .pattern = bbt_pattern,
1153 static struct nand_bbt_descr bbt_mirror_descr = {
1154 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1155 NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1160 .pattern = mirror_pattern,
1165 int board_nand_init(struct nand_chip *this)
1167 struct mtd_info *mtd;
1172 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1173 this->options |= NAND_USE_FLASH_BBT;
1174 this->bbt_td = &bbt_main_descr;
1175 this->bbt_md = &bbt_mirror_descr;
1178 /* structures must be linked */
1183 /* 5 us command delay time */
1184 this->chip_delay = 5;
1187 this->dev_ready = mxc_nand_dev_ready;
1188 this->cmdfunc = mxc_nand_command;
1189 this->select_chip = mxc_nand_select_chip;
1190 this->read_byte = mxc_nand_read_byte;
1191 this->read_word = mxc_nand_read_word;
1192 this->write_buf = mxc_nand_write_buf;
1193 this->read_buf = mxc_nand_read_buf;
1194 this->verify_buf = mxc_nand_verify_buf;
1196 host->regs = (struct fsl_nfc_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1199 #ifdef CONFIG_MXC_NAND_HWECC
1200 this->ecc.calculate = mxc_nand_calculate_ecc;
1201 this->ecc.hwctl = mxc_nand_enable_hwecc;
1202 this->ecc.correct = mxc_nand_correct_data;
1203 if (is_mxc_nfc_21()) {
1204 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1205 this->ecc.read_page = mxc_nand_read_page_syndrome;
1206 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1207 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1208 this->ecc.write_page = mxc_nand_write_page_syndrome;
1209 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1210 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1211 this->ecc.bytes = 9;
1212 this->ecc.prepad = 7;
1214 this->ecc.mode = NAND_ECC_HW;
1217 host->pagesize_2k = 0;
1219 this->ecc.size = 512;
1220 _mxc_nand_enable_hwecc(mtd, 1);
1222 this->ecc.layout = &nand_soft_eccoob;
1223 this->ecc.mode = NAND_ECC_SOFT;
1224 _mxc_nand_enable_hwecc(mtd, 0);
1227 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1229 /* NAND bus width determines access functions used by upper layer */
1230 if (is_16bit_nand())
1231 this->options |= NAND_BUSWIDTH_16;
1233 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1234 host->pagesize_2k = 1;
1235 this->ecc.layout = &nand_hw_eccoob2k;
1237 host->pagesize_2k = 0;
1238 this->ecc.layout = &nand_hw_eccoob;
1242 tmp = readw(&host->regs->config1);
1243 tmp |= NFC_ONE_CYCLE;
1244 tmp |= NFC_4_8N_ECC;
1245 writew(tmp, &host->regs->config1);
1246 if (host->pagesize_2k)
1247 writew(64/2, &host->regs->spare_area_size);
1249 writew(16/2, &host->regs->spare_area_size);
1254 * Unlock the internal RAM Buffer
1256 writew(0x2, &host->regs->config);
1258 /* Blocks to be unlocked */
1259 writew(0x0, &host->regs->unlockstart_blkaddr);
1260 /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1261 * unlockend_blkaddr, but the magic 0x4000 does not always work
1262 * when writing more than some 32 megabytes (on 2k page nands)
1263 * However 0xFFFF doesn't seem to have this kind
1264 * of limitation (tried it back and forth several times).
1265 * The linux kernel driver sets this to 0xFFFF for the v2 controller
1266 * only, but probably this was not tested there for v1.
1267 * The very same limitation seems to apply to this kernel driver.
1268 * This might be NAND chip specific and the i.MX31 datasheet is
1269 * extremely vague about the semantics of this register.
1271 writew(0xFFFF, &host->regs->unlockend_blkaddr);
1273 /* Unlock Block Command for given address range */
1274 writew(0x4, &host->regs->wrprot);