drivers/mtd/nand/mxc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2004-2007 Freescale Semiconductor, Inc.
   4  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   5  * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
   6  */
   7
   8 #include <common.h>
   9 #include <nand.h>
  10 #include <linux/err.h>
  11 #include <asm/io.h>
  12 #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
  13         defined(CONFIG_MX51) || defined(CONFIG_MX53)
  14 #include <asm/arch/imx-regs.h>
  15 #endif
  16 #include "mxc_nand.h"
  17
  18 #define DRIVER_NAME "mxc_nand"
  19
  20 struct mxc_nand_host {
  21         struct nand_chip                *nand;
  22
  23         struct mxc_nand_regs __iomem    *regs;
  24 #ifdef MXC_NFC_V3_2
  25         struct mxc_nand_ip_regs __iomem *ip_regs;
  26 #endif
  27         int                             spare_only;
  28         int                             status_request;
  29         int                             pagesize_2k;
  30         int                             clk_act;
  31         uint16_t                        col_addr;
  32         unsigned int                    page_addr;
  33 };
  34
  35 static struct mxc_nand_host mxc_host;
  36 static struct mxc_nand_host *host = &mxc_host;
  37
  38 /* Define delays in microsec for NAND device operations */
  39 #define TROP_US_DELAY   2000
  40 /* Macros to get byte and bit positions of ECC */
  41 #define COLPOS(x)  ((x) >> 3)
  42 #define BITPOS(x) ((x) & 0xf)
  43
  44 /* Define single bit Error positions in Main & Spare area */
  45 #define MAIN_SINGLEBIT_ERROR 0x4
  46 #define SPARE_SINGLEBIT_ERROR 0x1
  47
  48 /* OOB placement block for use with hardware ecc generation */
  49 #if defined(MXC_NFC_V1)
  50 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  51 static struct nand_ecclayout nand_hw_eccoob = {
  52         .eccbytes = 5,
  53         .eccpos = {6, 7, 8, 9, 10},
  54         .oobfree = { {0, 5}, {11, 5}, }
  55 };
  56 #else
  57 static struct nand_ecclayout nand_hw_eccoob2k = {
  58         .eccbytes = 20,
  59         .eccpos = {
  60                 6, 7, 8, 9, 10,
  61                 22, 23, 24, 25, 26,
  62                 38, 39, 40, 41, 42,
  63                 54, 55, 56, 57, 58,
  64         },
  65         .oobfree = { {2, 4}, {11, 11}, {27, 11}, {43, 11}, {59, 5} },
  66 };
  67 #endif
  68 #elif defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
  69 #ifndef CONFIG_SYS_NAND_LARGEPAGE
  70 static struct nand_ecclayout nand_hw_eccoob = {
  71         .eccbytes = 9,
  72         .eccpos = {7, 8, 9, 10, 11, 12, 13, 14, 15},
  73         .oobfree = { {2, 5} }
  74 };
  75 #else
  76 static struct nand_ecclayout nand_hw_eccoob2k = {
  77         .eccbytes = 36,
  78         .eccpos = {
  79                 7, 8, 9, 10, 11, 12, 13, 14, 15,
  80                 23, 24, 25, 26, 27, 28, 29, 30, 31,
  81                 39, 40, 41, 42, 43, 44, 45, 46, 47,
  82                 55, 56, 57, 58, 59, 60, 61, 62, 63,
  83         },
  84         .oobfree = { {2, 5}, {16, 7}, {32, 7}, {48, 7} },
  85 };
  86 #endif
  87 #endif
  88
  89 static int is_16bit_nand(void)
  90 {
  91 #if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  92         return 1;
  93 #else
  94         return 0;
  95 #endif
  96 }
  97
  98 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size)
  99 {
 100         uint32_t *d = dest;
 101
 102         size >>= 2;
 103         while (size--)
 104                 __raw_writel(__raw_readl(source++), d++);
 105         return dest;
 106 }
 107
 108 /*
 109  * This function polls the NANDFC to wait for the basic operation to
 110  * complete by checking the INT bit.
 111  */
 112 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
 113                                 uint16_t param)
 114 {
 115         uint32_t tmp;
 116
 117         while (max_retries-- > 0) {
 118 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 119                 tmp = readnfc(&host->regs->config2);
 120                 if (tmp & NFC_V1_V2_CONFIG2_INT) {
 121                         tmp &= ~NFC_V1_V2_CONFIG2_INT;
 122                         writenfc(tmp, &host->regs->config2);
 123 #elif defined(MXC_NFC_V3_2)
 124                 tmp = readnfc(&host->ip_regs->ipc);
 125                 if (tmp & NFC_V3_IPC_INT) {
 126                         tmp &= ~NFC_V3_IPC_INT;
 127                         writenfc(tmp, &host->ip_regs->ipc);
 128 #endif
 129                         break;
 130                 }
 131                 udelay(1);
 132         }
 133         if (max_retries < 0) {
 134                 pr_debug("%s(%d): INT not set\n",
 135                                 __func__, param);
 136         }
 137 }
 138
 139 /*
 140  * This function issues the specified command to the NAND device and
 141  * waits for completion.
 142  */
 143 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd)
 144 {
 145         pr_debug("send_cmd(host, 0x%x)\n", cmd);
 146
 147         writenfc(cmd, &host->regs->flash_cmd);
 148         writenfc(NFC_CMD, &host->regs->operation);
 149
 150         /* Wait for operation to complete */
 151         wait_op_done(host, TROP_US_DELAY, cmd);
 152 }
 153
 154 /*
 155  * This function sends an address (or partial address) to the
 156  * NAND device. The address is used to select the source/destination for
 157  * a NAND command.
 158  */
 159 static void send_addr(struct mxc_nand_host *host, uint16_t addr)
 160 {
 161         pr_debug("send_addr(host, 0x%x)\n", addr);
 162
 163         writenfc(addr, &host->regs->flash_addr);
 164         writenfc(NFC_ADDR, &host->regs->operation);
 165
 166         /* Wait for operation to complete */
 167         wait_op_done(host, TROP_US_DELAY, addr);
 168 }
 169
 170 /*
 171  * This function requests the NANDFC to initiate the transfer
 172  * of data currently in the NANDFC RAM buffer to the NAND device.
 173  */
 174 static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 175                         int spare_only)
 176 {
 177         if (spare_only)
 178                 pr_debug("send_prog_page (%d)\n", spare_only);
 179
 180         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 181                 int i;
 182                 /*
 183                  *  The controller copies the 64 bytes of spare data from
 184                  *  the first 16 bytes of each of the 4 64 byte spare buffers.
 185                  *  Copy the contiguous data starting in spare_area[0] to
 186                  *  the four spare area buffers.
 187                  */
 188                 for (i = 1; i < 4; i++) {
 189                         void __iomem *src = &host->regs->spare_area[0][i * 16];
 190                         void __iomem *dst = &host->regs->spare_area[i][0];
 191
 192                         mxc_nand_memcpy32(dst, src, 16);
 193                 }
 194         }
 195
 196 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 197         writenfc(buf_id, &host->regs->buf_addr);
 198 #elif defined(MXC_NFC_V3_2)
 199         uint32_t tmp = readnfc(&host->regs->config1);
 200         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 201         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 202         writenfc(tmp, &host->regs->config1);
 203 #endif
 204
 205         /* Configure spare or page+spare access */
 206         if (!host->pagesize_2k) {
 207                 uint32_t config1 = readnfc(&host->regs->config1);
 208                 if (spare_only)
 209                         config1 |= NFC_CONFIG1_SP_EN;
 210                 else
 211                         config1 &= ~NFC_CONFIG1_SP_EN;
 212                 writenfc(config1, &host->regs->config1);
 213         }
 214
 215         writenfc(NFC_INPUT, &host->regs->operation);
 216
 217         /* Wait for operation to complete */
 218         wait_op_done(host, TROP_US_DELAY, spare_only);
 219 }
 220
 221 /*
 222  * Requests NANDFC to initiate the transfer of data from the
 223  * NAND device into in the NANDFC ram buffer.
 224  */
 225 static void send_read_page(struct mxc_nand_host *host, uint8_t buf_id,
 226                 int spare_only)
 227 {
 228         pr_debug("send_read_page (%d)\n", spare_only);
 229
 230 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 231         writenfc(buf_id, &host->regs->buf_addr);
 232 #elif defined(MXC_NFC_V3_2)
 233         uint32_t tmp = readnfc(&host->regs->config1);
 234         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 235         tmp |= NFC_V3_CONFIG1_RBA(buf_id);
 236         writenfc(tmp, &host->regs->config1);
 237 #endif
 238
 239         /* Configure spare or page+spare access */
 240         if (!host->pagesize_2k) {
 241                 uint32_t config1 = readnfc(&host->regs->config1);
 242                 if (spare_only)
 243                         config1 |= NFC_CONFIG1_SP_EN;
 244                 else
 245                         config1 &= ~NFC_CONFIG1_SP_EN;
 246                 writenfc(config1, &host->regs->config1);
 247         }
 248
 249         writenfc(NFC_OUTPUT, &host->regs->operation);
 250
 251         /* Wait for operation to complete */
 252         wait_op_done(host, TROP_US_DELAY, spare_only);
 253
 254         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
 255                 int i;
 256
 257                 /*
 258                  *  The controller copies the 64 bytes of spare data to
 259                  *  the first 16 bytes of each of the 4 spare buffers.
 260                  *  Make the data contiguous starting in spare_area[0].
 261                  */
 262                 for (i = 1; i < 4; i++) {
 263                         void __iomem *src = &host->regs->spare_area[i][0];
 264                         void __iomem *dst = &host->regs->spare_area[0][i * 16];
 265
 266                         mxc_nand_memcpy32(dst, src, 16);
 267                 }
 268         }
 269 }
 270
 271 /* Request the NANDFC to perform a read of the NAND device ID. */
 272 static void send_read_id(struct mxc_nand_host *host)
 273 {
 274         uint32_t tmp;
 275
 276 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 277         /* NANDFC buffer 0 is used for device ID output */
 278         writenfc(0x0, &host->regs->buf_addr);
 279 #elif defined(MXC_NFC_V3_2)
 280         tmp = readnfc(&host->regs->config1);
 281         tmp &= ~NFC_V3_CONFIG1_RBA_MASK;
 282         writenfc(tmp, &host->regs->config1);
 283 #endif
 284
 285         /* Read ID into main buffer */
 286         tmp = readnfc(&host->regs->config1);
 287         tmp &= ~NFC_CONFIG1_SP_EN;
 288         writenfc(tmp, &host->regs->config1);
 289
 290         writenfc(NFC_ID, &host->regs->operation);
 291
 292         /* Wait for operation to complete */
 293         wait_op_done(host, TROP_US_DELAY, 0);
 294 }
 295
 296 /*
 297  * This function requests the NANDFC to perform a read of the
 298  * NAND device status and returns the current status.
 299  */
 300 static uint16_t get_dev_status(struct mxc_nand_host *host)
 301 {
 302 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 303         void __iomem *main_buf = host->regs->main_area[1];
 304         uint32_t store;
 305 #endif
 306         uint32_t ret, tmp;
 307         /* Issue status request to NAND device */
 308
 309 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 310         /* store the main area1 first word, later do recovery */
 311         store = readl(main_buf);
 312         /* NANDFC buffer 1 is used for device status */
 313         writenfc(1, &host->regs->buf_addr);
 314 #endif
 315
 316         /* Read status into main buffer */
 317         tmp = readnfc(&host->regs->config1);
 318         tmp &= ~NFC_CONFIG1_SP_EN;
 319         writenfc(tmp, &host->regs->config1);
 320
 321         writenfc(NFC_STATUS, &host->regs->operation);
 322
 323         /* Wait for operation to complete */
 324         wait_op_done(host, TROP_US_DELAY, 0);
 325
 326 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 327         /*
 328          *  Status is placed in first word of main buffer
 329          * get status, then recovery area 1 data
 330          */
 331         ret = readw(main_buf);
 332         writel(store, main_buf);
 333 #elif defined(MXC_NFC_V3_2)
 334         ret = readnfc(&host->regs->config1) >> 16;
 335 #endif
 336
 337         return ret;
 338 }
 339
 340 /* This function is used by upper layer to checks if device is ready */
 341 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 342 {
 343         /*
 344          * NFC handles R/B internally. Therefore, this function
 345          * always returns status as ready.
 346          */
 347         return 1;
 348 }
 349
 350 static void _mxc_nand_enable_hwecc(struct mtd_info *mtd, int on)
 351 {
 352         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 353         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 354 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
 355         uint16_t tmp = readnfc(&host->regs->config1);
 356
 357         if (on)
 358                 tmp |= NFC_V1_V2_CONFIG1_ECC_EN;
 359         else
 360                 tmp &= ~NFC_V1_V2_CONFIG1_ECC_EN;
 361         writenfc(tmp, &host->regs->config1);
 362 #elif defined(MXC_NFC_V3_2)
 363         uint32_t tmp = readnfc(&host->ip_regs->config2);
 364
 365         if (on)
 366                 tmp |= NFC_V3_CONFIG2_ECC_EN;
 367         else
 368                 tmp &= ~NFC_V3_CONFIG2_ECC_EN;
 369         writenfc(tmp, &host->ip_regs->config2);
 370 #endif
 371 }
 372
 373 #ifdef CONFIG_MXC_NAND_HWECC
 374 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 375 {
 376         /*
 377          * If HW ECC is enabled, we turn it on during init. There is
 378          * no need to enable again here.
 379          */
 380 }
 381
 382 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
 383 static int mxc_nand_read_oob_syndrome(struct mtd_info *mtd,
 384                                       struct nand_chip *chip,
 385                                       int page)
 386 {
 387         struct mxc_nand_host *host = nand_get_controller_data(chip);
 388         uint8_t *buf = chip->oob_poi;
 389         int length = mtd->oobsize;
 390         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 391         uint8_t *bufpoi = buf;
 392         int i, toread;
 393
 394         pr_debug("%s: Reading OOB area of page %u to oob %p\n",
 395                          __func__, page, buf);
 396
 397         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 398         for (i = 0; i < chip->ecc.steps; i++) {
 399                 toread = min_t(int, length, chip->ecc.prepad);
 400                 if (toread) {
 401                         chip->read_buf(mtd, bufpoi, toread);
 402                         bufpoi += toread;
 403                         length -= toread;
 404                 }
 405                 bufpoi += chip->ecc.bytes;
 406                 host->col_addr += chip->ecc.bytes;
 407                 length -= chip->ecc.bytes;
 408
 409                 toread = min_t(int, length, chip->ecc.postpad);
 410                 if (toread) {
 411                         chip->read_buf(mtd, bufpoi, toread);
 412                         bufpoi += toread;
 413                         length -= toread;
 414                 }
 415         }
 416         if (length > 0)
 417                 chip->read_buf(mtd, bufpoi, length);
 418
 419         _mxc_nand_enable_hwecc(mtd, 0);
 420         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 421                         mtd->writesize + chip->ecc.prepad, page);
 422         bufpoi = buf + chip->ecc.prepad;
 423         length = mtd->oobsize - chip->ecc.prepad;
 424         for (i = 0; i < chip->ecc.steps; i++) {
 425                 toread = min_t(int, length, chip->ecc.bytes);
 426                 chip->read_buf(mtd, bufpoi, toread);
 427                 bufpoi += eccpitch;
 428                 length -= eccpitch;
 429                 host->col_addr += chip->ecc.postpad + chip->ecc.prepad;
 430         }
 431         _mxc_nand_enable_hwecc(mtd, 1);
 432         return 1;
 433 }
 434
 435 static int mxc_nand_read_page_raw_syndrome(struct mtd_info *mtd,
 436                                            struct nand_chip *chip,
 437                                            uint8_t *buf,
 438                                            int oob_required,
 439                                            int page)
 440 {
 441         struct mxc_nand_host *host = nand_get_controller_data(chip);
 442         int eccsize = chip->ecc.size;
 443         int eccbytes = chip->ecc.bytes;
 444         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 445         uint8_t *oob = chip->oob_poi;
 446         int steps, size;
 447         int n;
 448
 449         _mxc_nand_enable_hwecc(mtd, 0);
 450         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 451
 452         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 453                 host->col_addr = n * eccsize;
 454                 chip->read_buf(mtd, buf, eccsize);
 455                 buf += eccsize;
 456
 457                 host->col_addr = mtd->writesize + n * eccpitch;
 458                 if (chip->ecc.prepad) {
 459                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 460                         oob += chip->ecc.prepad;
 461                 }
 462
 463                 chip->read_buf(mtd, oob, eccbytes);
 464                 oob += eccbytes;
 465
 466                 if (chip->ecc.postpad) {
 467                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 468                         oob += chip->ecc.postpad;
 469                 }
 470         }
 471
 472         size = mtd->oobsize - (oob - chip->oob_poi);
 473         if (size)
 474                 chip->read_buf(mtd, oob, size);
 475         _mxc_nand_enable_hwecc(mtd, 1);
 476
 477         return 0;
 478 }
 479
 480 static int mxc_nand_read_page_syndrome(struct mtd_info *mtd,
 481                                        struct nand_chip *chip,
 482                                        uint8_t *buf,
 483                                        int oob_required,
 484                                        int page)
 485 {
 486         struct mxc_nand_host *host = nand_get_controller_data(chip);
 487         int n, eccsize = chip->ecc.size;
 488         int eccbytes = chip->ecc.bytes;
 489         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 490         int eccsteps = chip->ecc.steps;
 491         uint8_t *p = buf;
 492         uint8_t *oob = chip->oob_poi;
 493
 494         pr_debug("Reading page %u to buf %p oob %p\n",
 495                  page, buf, oob);
 496
 497         /* first read the data area and the available portion of OOB */
 498         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 499                 int stat;
 500
 501                 host->col_addr = n * eccsize;
 502
 503                 chip->read_buf(mtd, p, eccsize);
 504
 505                 host->col_addr = mtd->writesize + n * eccpitch;
 506
 507                 if (chip->ecc.prepad) {
 508                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 509                         oob += chip->ecc.prepad;
 510                 }
 511
 512                 stat = chip->ecc.correct(mtd, p, oob, NULL);
 513
 514                 if (stat < 0)
 515                         mtd->ecc_stats.failed++;
 516                 else
 517                         mtd->ecc_stats.corrected += stat;
 518                 oob += eccbytes;
 519
 520                 if (chip->ecc.postpad) {
 521                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 522                         oob += chip->ecc.postpad;
 523                 }
 524         }
 525
 526         /* Calculate remaining oob bytes */
 527         n = mtd->oobsize - (oob - chip->oob_poi);
 528         if (n)
 529                 chip->read_buf(mtd, oob, n);
 530
 531         /* Then switch ECC off and read the OOB area to get the ECC code */
 532         _mxc_nand_enable_hwecc(mtd, 0);
 533         chip->cmdfunc(mtd, NAND_CMD_READOOB, mtd->writesize, page);
 534         eccsteps = chip->ecc.steps;
 535         oob = chip->oob_poi + chip->ecc.prepad;
 536         for (n = 0; eccsteps; n++, eccsteps--, p += eccsize) {
 537                 host->col_addr = mtd->writesize +
 538                                  n * eccpitch +
 539                                  chip->ecc.prepad;
 540                 chip->read_buf(mtd, oob, eccbytes);
 541                 oob += eccbytes + chip->ecc.postpad;
 542         }
 543         _mxc_nand_enable_hwecc(mtd, 1);
 544         return 0;
 545 }
 546
 547 static int mxc_nand_write_oob_syndrome(struct mtd_info *mtd,
 548                                        struct nand_chip *chip, int page)
 549 {
 550         struct mxc_nand_host *host = nand_get_controller_data(chip);
 551         int eccpitch = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
 552         int length = mtd->oobsize;
 553         int i, len, status, steps = chip->ecc.steps;
 554         const uint8_t *bufpoi = chip->oob_poi;
 555
 556         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
 557         for (i = 0; i < steps; i++) {
 558                 len = min_t(int, length, eccpitch);
 559
 560                 chip->write_buf(mtd, bufpoi, len);
 561                 bufpoi += len;
 562                 length -= len;
 563                 host->col_addr += chip->ecc.prepad + chip->ecc.postpad;
 564         }
 565         if (length > 0)
 566                 chip->write_buf(mtd, bufpoi, length);
 567
 568         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
 569         status = chip->waitfunc(mtd, chip);
 570         return status & NAND_STATUS_FAIL ? -EIO : 0;
 571 }
 572
 573 static int mxc_nand_write_page_raw_syndrome(struct mtd_info *mtd,
 574                                              struct nand_chip *chip,
 575                                              const uint8_t *buf,
 576                                              int oob_required, int page)
 577 {
 578         struct mxc_nand_host *host = nand_get_controller_data(chip);
 579         int eccsize = chip->ecc.size;
 580         int eccbytes = chip->ecc.bytes;
 581         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 582         uint8_t *oob = chip->oob_poi;
 583         int steps, size;
 584         int n;
 585
 586         for (n = 0, steps = chip->ecc.steps; steps > 0; n++, steps--) {
 587                 host->col_addr = n * eccsize;
 588                 chip->write_buf(mtd, buf, eccsize);
 589                 buf += eccsize;
 590
 591                 host->col_addr = mtd->writesize + n * eccpitch;
 592
 593                 if (chip->ecc.prepad) {
 594                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 595                         oob += chip->ecc.prepad;
 596                 }
 597
 598                 host->col_addr += eccbytes;
 599                 oob += eccbytes;
 600
 601                 if (chip->ecc.postpad) {
 602                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 603                         oob += chip->ecc.postpad;
 604                 }
 605         }
 606
 607         size = mtd->oobsize - (oob - chip->oob_poi);
 608         if (size)
 609                 chip->write_buf(mtd, oob, size);
 610         return 0;
 611 }
 612
 613 static int mxc_nand_write_page_syndrome(struct mtd_info *mtd,
 614                                          struct nand_chip *chip,
 615                                          const uint8_t *buf,
 616                                          int oob_required, int page)
 617 {
 618         struct mxc_nand_host *host = nand_get_controller_data(chip);
 619         int i, n, eccsize = chip->ecc.size;
 620         int eccbytes = chip->ecc.bytes;
 621         int eccpitch = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
 622         int eccsteps = chip->ecc.steps;
 623         const uint8_t *p = buf;
 624         uint8_t *oob = chip->oob_poi;
 625
 626         chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
 627
 628         for (i = n = 0;
 629              eccsteps;
 630              n++, eccsteps--, i += eccbytes, p += eccsize) {
 631                 host->col_addr = n * eccsize;
 632
 633                 chip->write_buf(mtd, p, eccsize);
 634
 635                 host->col_addr = mtd->writesize + n * eccpitch;
 636
 637                 if (chip->ecc.prepad) {
 638                         chip->write_buf(mtd, oob, chip->ecc.prepad);
 639                         oob += chip->ecc.prepad;
 640                 }
 641
 642                 chip->write_buf(mtd, oob, eccbytes);
 643                 oob += eccbytes;
 644
 645                 if (chip->ecc.postpad) {
 646                         chip->write_buf(mtd, oob, chip->ecc.postpad);
 647                         oob += chip->ecc.postpad;
 648                 }
 649         }
 650
 651         /* Calculate remaining oob bytes */
 652         i = mtd->oobsize - (oob - chip->oob_poi);
 653         if (i)
 654                 chip->write_buf(mtd, oob, i);
 655         return 0;
 656 }
 657
 658 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 659                                  u_char *read_ecc, u_char *calc_ecc)
 660 {
 661         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 662         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 663         uint32_t ecc_status = readl(&host->regs->ecc_status_result);
 664         int subpages = mtd->writesize / nand_chip->subpagesize;
 665         int pg2blk_shift = nand_chip->phys_erase_shift -
 666                            nand_chip->page_shift;
 667
 668         do {
 669                 if ((ecc_status & 0xf) > 4) {
 670                         static int last_bad = -1;
 671
 672                         if (last_bad != host->page_addr >> pg2blk_shift) {
 673                                 last_bad = host->page_addr >> pg2blk_shift;
 674                                 printk(KERN_DEBUG
 675                                        "MXC_NAND: HWECC uncorrectable ECC error"
 676                                        " in block %u page %u subpage %d\n",
 677                                        last_bad, host->page_addr,
 678                                        mtd->writesize / nand_chip->subpagesize
 679                                             - subpages);
 680                         }
 681                         return -EBADMSG;
 682                 }
 683                 ecc_status >>= 4;
 684                 subpages--;
 685         } while (subpages > 0);
 686
 687         return 0;
 688 }
 689 #else
 690 #define mxc_nand_read_page_syndrome NULL
 691 #define mxc_nand_read_page_raw_syndrome NULL
 692 #define mxc_nand_read_oob_syndrome NULL
 693 #define mxc_nand_write_page_syndrome NULL
 694 #define mxc_nand_write_page_raw_syndrome NULL
 695 #define mxc_nand_write_oob_syndrome NULL
 696
 697 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 698                                  u_char *read_ecc, u_char *calc_ecc)
 699 {
 700         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 701         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 702
 703         /*
 704          * 1-Bit errors are automatically corrected in HW.  No need for
 705          * additional correction.  2-Bit errors cannot be corrected by
 706          * HW ECC, so we need to return failure
 707          */
 708         uint16_t ecc_status = readnfc(&host->regs->ecc_status_result);
 709
 710         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 711                 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 712                 return -EBADMSG;
 713         }
 714
 715         return 0;
 716 }
 717 #endif
 718
 719 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 720                                   u_char *ecc_code)
 721 {
 722         return 0;
 723 }
 724 #endif
 725
 726 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 727 {
 728         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 729         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 730         uint8_t ret = 0;
 731         uint16_t col;
 732         uint16_t __iomem *main_buf =
 733                 (uint16_t __iomem *)host->regs->main_area[0];
 734         uint16_t __iomem *spare_buf =
 735                 (uint16_t __iomem *)host->regs->spare_area[0];
 736         union {
 737                 uint16_t word;
 738                 uint8_t bytes[2];
 739         } nfc_word;
 740
 741         /* Check for status request */
 742         if (host->status_request)
 743                 return get_dev_status(host) & 0xFF;
 744
 745         /* Get column for 16-bit access */
 746         col = host->col_addr >> 1;
 747
 748         /* If we are accessing the spare region */
 749         if (host->spare_only)
 750                 nfc_word.word = readw(&spare_buf[col]);
 751         else
 752                 nfc_word.word = readw(&main_buf[col]);
 753
 754         /* Pick upper/lower byte of word from RAM buffer */
 755         ret = nfc_word.bytes[host->col_addr & 0x1];
 756
 757         /* Update saved column address */
 758         if (nand_chip->options & NAND_BUSWIDTH_16)
 759                 host->col_addr += 2;
 760         else
 761                 host->col_addr++;
 762
 763         return ret;
 764 }
 765
 766 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 767 {
 768         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 769         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 770         uint16_t col, ret;
 771         uint16_t __iomem *p;
 772
 773         pr_debug("mxc_nand_read_word(col = %d)\n", host->col_addr);
 774
 775         col = host->col_addr;
 776         /* Adjust saved column address */
 777         if (col < mtd->writesize && host->spare_only)
 778                 col += mtd->writesize;
 779
 780         if (col < mtd->writesize) {
 781                 p = (uint16_t __iomem *)(host->regs->main_area[0] +
 782                                 (col >> 1));
 783         } else {
 784                 p = (uint16_t __iomem *)(host->regs->spare_area[0] +
 785                                 ((col - mtd->writesize) >> 1));
 786         }
 787
 788         if (col & 1) {
 789                 union {
 790                         uint16_t word;
 791                         uint8_t bytes[2];
 792                 } nfc_word[3];
 793
 794                 nfc_word[0].word = readw(p);
 795                 nfc_word[1].word = readw(p + 1);
 796
 797                 nfc_word[2].bytes[0] = nfc_word[0].bytes[1];
 798                 nfc_word[2].bytes[1] = nfc_word[1].bytes[0];
 799
 800                 ret = nfc_word[2].word;
 801         } else {
 802                 ret = readw(p);
 803         }
 804
 805         /* Update saved column address */
 806         host->col_addr = col + 2;
 807
 808         return ret;
 809 }
 810
 811 /*
 812  * Write data of length len to buffer buf. The data to be
 813  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 814  * Operation by the NFC, the data is written to NAND Flash
 815  */
 816 static void mxc_nand_write_buf(struct mtd_info *mtd,
 817                                 const u_char *buf, int len)
 818 {
 819         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 820         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 821         int n, col, i = 0;
 822
 823         pr_debug("mxc_nand_write_buf(col = %d, len = %d)\n", host->col_addr,
 824                  len);
 825
 826         col = host->col_addr;
 827
 828         /* Adjust saved column address */
 829         if (col < mtd->writesize && host->spare_only)
 830                 col += mtd->writesize;
 831
 832         n = mtd->writesize + mtd->oobsize - col;
 833         n = min(len, n);
 834
 835         pr_debug("%s:%d: col = %d, n = %d\n", __func__, __LINE__, col, n);
 836
 837         while (n > 0) {
 838                 void __iomem *p;
 839
 840                 if (col < mtd->writesize) {
 841                         p = host->regs->main_area[0] + (col & ~3);
 842                 } else {
 843                         p = host->regs->spare_area[0] -
 844                                                 mtd->writesize + (col & ~3);
 845                 }
 846
 847                 pr_debug("%s:%d: p = %p\n", __func__,
 848                          __LINE__, p);
 849
 850                 if (((col | (unsigned long)&buf[i]) & 3) || n < 4) {
 851                         union {
 852                                 uint32_t word;
 853                                 uint8_t bytes[4];
 854                         } nfc_word;
 855
 856                         nfc_word.word = readl(p);
 857                         nfc_word.bytes[col & 3] = buf[i++];
 858                         n--;
 859                         col++;
 860
 861                         writel(nfc_word.word, p);
 862                 } else {
 863                         int m = mtd->writesize - col;
 864
 865                         if (col >= mtd->writesize)
 866                                 m += mtd->oobsize;
 867
 868                         m = min(n, m) & ~3;
 869
 870                         pr_debug("%s:%d: n = %d, m = %d, i = %d, col = %d\n",
 871                                  __func__,  __LINE__, n, m, i, col);
 872
 873                         mxc_nand_memcpy32(p, (uint32_t *)&buf[i], m);
 874                         col += m;
 875                         i += m;
 876                         n -= m;
 877                 }
 878         }
 879         /* Update saved column address */
 880         host->col_addr = col;
 881 }
 882
 883 /*
 884  * Read the data buffer from the NAND Flash. To read the data from NAND
 885  * Flash first the data output cycle is initiated by the NFC, which copies
 886  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 887  */
 888 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 889 {
 890         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 891         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 892         int n, col, i = 0;
 893
 894         pr_debug("mxc_nand_read_buf(col = %d, len = %d)\n", host->col_addr,
 895                  len);
 896
 897         col = host->col_addr;
 898
 899         /* Adjust saved column address */
 900         if (col < mtd->writesize && host->spare_only)
 901                 col += mtd->writesize;
 902
 903         n = mtd->writesize + mtd->oobsize - col;
 904         n = min(len, n);
 905
 906         while (n > 0) {
 907                 void __iomem *p;
 908
 909                 if (col < mtd->writesize) {
 910                         p = host->regs->main_area[0] + (col & ~3);
 911                 } else {
 912                         p = host->regs->spare_area[0] -
 913                                         mtd->writesize + (col & ~3);
 914                 }
 915
 916                 if (((col | (int)&buf[i]) & 3) || n < 4) {
 917                         union {
 918                                 uint32_t word;
 919                                 uint8_t bytes[4];
 920                         } nfc_word;
 921
 922                         nfc_word.word = readl(p);
 923                         buf[i++] = nfc_word.bytes[col & 3];
 924                         n--;
 925                         col++;
 926                 } else {
 927                         int m = mtd->writesize - col;
 928
 929                         if (col >= mtd->writesize)
 930                                 m += mtd->oobsize;
 931
 932                         m = min(n, m) & ~3;
 933                         mxc_nand_memcpy32((uint32_t *)&buf[i], p, m);
 934
 935                         col += m;
 936                         i += m;
 937                         n -= m;
 938                 }
 939         }
 940         /* Update saved column address */
 941         host->col_addr = col;
 942 }
 943
 944 /*
 945  * This function is used by upper layer for select and
 946  * deselect of the NAND chip
 947  */
 948 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 949 {
 950         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 951         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 952
 953         switch (chip) {
 954         case -1:
 955                 /* TODO: Disable the NFC clock */
 956                 if (host->clk_act)
 957                         host->clk_act = 0;
 958                 break;
 959         case 0:
 960                 /* TODO: Enable the NFC clock */
 961                 if (!host->clk_act)
 962                         host->clk_act = 1;
 963                 break;
 964
 965         default:
 966                 break;
 967         }
 968 }
 969
 970 /*
 971  * Used by the upper layer to write command to NAND Flash for
 972  * different operations to be carried out on NAND Flash
 973  */
 974 void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 975                                 int column, int page_addr)
 976 {
 977         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 978         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 979
 980         pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 981                  command, column, page_addr);
 982
 983         /* Reset command state information */
 984         host->status_request = false;
 985
 986         /* Command pre-processing step */
 987         switch (command) {
 988
 989         case NAND_CMD_STATUS:
 990                 host->col_addr = 0;
 991                 host->status_request = true;
 992                 break;
 993
 994         case NAND_CMD_READ0:
 995                 host->page_addr = page_addr;
 996                 host->col_addr = column;
 997                 host->spare_only = false;
 998                 break;
 999
1000         case NAND_CMD_READOOB:
1001                 host->col_addr = column;
1002                 host->spare_only = true;
1003                 if (host->pagesize_2k)
1004                         command = NAND_CMD_READ0; /* only READ0 is valid */
1005                 break;
1006
1007         case NAND_CMD_SEQIN:
1008                 if (column >= mtd->writesize) {
1009                         /*
1010                          * before sending SEQIN command for partial write,
1011                          * we need read one page out. FSL NFC does not support
1012                          * partial write. It always sends out 512+ecc+512+ecc
1013                          * for large page nand flash. But for small page nand
1014                          * flash, it does support SPARE ONLY operation.
1015                          */
1016                         if (host->pagesize_2k) {
1017                                 /* call ourself to read a page */
1018                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
1019                                                 page_addr);
1020                         }
1021
1022                         host->col_addr = column - mtd->writesize;
1023                         host->spare_only = true;
1024
1025                         /* Set program pointer to spare region */
1026                         if (!host->pagesize_2k)
1027                                 send_cmd(host, NAND_CMD_READOOB);
1028                 } else {
1029                         host->spare_only = false;
1030                         host->col_addr = column;
1031
1032                         /* Set program pointer to page start */
1033                         if (!host->pagesize_2k)
1034                                 send_cmd(host, NAND_CMD_READ0);
1035                 }
1036                 break;
1037
1038         case NAND_CMD_PAGEPROG:
1039                 send_prog_page(host, 0, host->spare_only);
1040
1041                 if (host->pagesize_2k && is_mxc_nfc_1()) {
1042                         /* data in 4 areas */
1043                         send_prog_page(host, 1, host->spare_only);
1044                         send_prog_page(host, 2, host->spare_only);
1045                         send_prog_page(host, 3, host->spare_only);
1046                 }
1047
1048                 break;
1049         }
1050
1051         /* Write out the command to the device. */
1052         send_cmd(host, command);
1053
1054         /* Write out column address, if necessary */
1055         if (column != -1) {
1056                 /*
1057                  * MXC NANDFC can only perform full page+spare or
1058                  * spare-only read/write. When the upper layers perform
1059                  * a read/write buffer operation, we will use the saved
1060                  * column address to index into the full page.
1061                  */
1062                 send_addr(host, 0);
1063                 if (host->pagesize_2k)
1064                         /* another col addr cycle for 2k page */
1065                         send_addr(host, 0);
1066         }
1067
1068         /* Write out page address, if necessary */
1069         if (page_addr != -1) {
1070                 u32 page_mask = nand_chip->pagemask;
1071                 do {
1072                         send_addr(host, page_addr & 0xFF);
1073                         page_addr >>= 8;
1074                         page_mask >>= 8;
1075                 } while (page_mask);
1076         }
1077
1078         /* Command post-processing step */
1079         switch (command) {
1080
1081         case NAND_CMD_RESET:
1082                 break;
1083
1084         case NAND_CMD_READOOB:
1085         case NAND_CMD_READ0:
1086                 if (host->pagesize_2k) {
1087                         /* send read confirm command */
1088                         send_cmd(host, NAND_CMD_READSTART);
1089                         /* read for each AREA */
1090                         send_read_page(host, 0, host->spare_only);
1091                         if (is_mxc_nfc_1()) {
1092                                 send_read_page(host, 1, host->spare_only);
1093                                 send_read_page(host, 2, host->spare_only);
1094                                 send_read_page(host, 3, host->spare_only);
1095                         }
1096                 } else {
1097                         send_read_page(host, 0, host->spare_only);
1098                 }
1099                 break;
1100
1101         case NAND_CMD_READID:
1102                 host->col_addr = 0;
1103                 send_read_id(host);
1104                 break;
1105
1106         case NAND_CMD_PAGEPROG:
1107                 break;
1108
1109         case NAND_CMD_STATUS:
1110                 break;
1111
1112         case NAND_CMD_ERASE2:
1113                 break;
1114         }
1115 }
1116
1117 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1118
1119 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
1120 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
1121
1122 static struct nand_bbt_descr bbt_main_descr = {
1123         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1124                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1125         .offs = 0,
1126         .len = 4,
1127         .veroffs = 4,
1128         .maxblocks = 4,
1129         .pattern = bbt_pattern,
1130 };
1131
1132 static struct nand_bbt_descr bbt_mirror_descr = {
1133         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
1134                    NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1135         .offs = 0,
1136         .len = 4,
1137         .veroffs = 4,
1138         .maxblocks = 4,
1139         .pattern = mirror_pattern,
1140 };
1141
1142 #endif
1143
1144 int board_nand_init(struct nand_chip *this)
1145 {
1146         struct mtd_info *mtd;
1147 #if defined(MXC_NFC_V2_1) || defined(MXC_NFC_V3_2)
1148         uint32_t tmp;
1149 #endif
1150
1151 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
1152         this->bbt_options |= NAND_BBT_USE_FLASH;
1153         this->bbt_td = &bbt_main_descr;
1154         this->bbt_md = &bbt_mirror_descr;
1155 #endif
1156
1157         /* structures must be linked */
1158         mtd = &this->mtd;
1159         host->nand = this;
1160
1161         /* 5 us command delay time */
1162         this->chip_delay = 5;
1163
1164         nand_set_controller_data(this, host);
1165         this->dev_ready = mxc_nand_dev_ready;
1166         this->cmdfunc = mxc_nand_command;
1167         this->select_chip = mxc_nand_select_chip;
1168         this->read_byte = mxc_nand_read_byte;
1169         this->read_word = mxc_nand_read_word;
1170         this->write_buf = mxc_nand_write_buf;
1171         this->read_buf = mxc_nand_read_buf;
1172
1173         host->regs = (struct mxc_nand_regs __iomem *)CONFIG_MXC_NAND_REGS_BASE;
1174 #ifdef MXC_NFC_V3_2
1175         host->ip_regs =
1176                 (struct mxc_nand_ip_regs __iomem *)CONFIG_MXC_NAND_IP_REGS_BASE;
1177 #endif
1178         host->clk_act = 1;
1179
1180 #ifdef CONFIG_MXC_NAND_HWECC
1181         this->ecc.calculate = mxc_nand_calculate_ecc;
1182         this->ecc.hwctl = mxc_nand_enable_hwecc;
1183         this->ecc.correct = mxc_nand_correct_data;
1184         if (is_mxc_nfc_21() || is_mxc_nfc_32()) {
1185                 this->ecc.mode = NAND_ECC_HW_SYNDROME;
1186                 this->ecc.read_page = mxc_nand_read_page_syndrome;
1187                 this->ecc.read_page_raw = mxc_nand_read_page_raw_syndrome;
1188                 this->ecc.read_oob = mxc_nand_read_oob_syndrome;
1189                 this->ecc.write_page = mxc_nand_write_page_syndrome;
1190                 this->ecc.write_page_raw = mxc_nand_write_page_raw_syndrome;
1191                 this->ecc.write_oob = mxc_nand_write_oob_syndrome;
1192                 this->ecc.bytes = 9;
1193                 this->ecc.prepad = 7;
1194         } else {
1195                 this->ecc.mode = NAND_ECC_HW;
1196         }
1197
1198         if (is_mxc_nfc_1())
1199                 this->ecc.strength = 1;
1200         else
1201                 this->ecc.strength = 4;
1202
1203         host->pagesize_2k = 0;
1204
1205         this->ecc.size = 512;
1206         _mxc_nand_enable_hwecc(mtd, 1);
1207 #else
1208         this->ecc.layout = &nand_soft_eccoob;
1209         this->ecc.mode = NAND_ECC_SOFT;
1210         _mxc_nand_enable_hwecc(mtd, 0);
1211 #endif
1212         /* Reset NAND */
1213         this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
1214
1215         /* NAND bus width determines access functions used by upper layer */
1216         if (is_16bit_nand())
1217                 this->options |= NAND_BUSWIDTH_16;
1218
1219 #ifdef CONFIG_SYS_NAND_LARGEPAGE
1220         host->pagesize_2k = 1;
1221         this->ecc.layout = &nand_hw_eccoob2k;
1222 #else
1223         host->pagesize_2k = 0;
1224         this->ecc.layout = &nand_hw_eccoob;
1225 #endif
1226
1227 #if defined(MXC_NFC_V1) || defined(MXC_NFC_V2_1)
1228 #ifdef MXC_NFC_V2_1
1229         tmp = readnfc(&host->regs->config1);
1230         tmp |= NFC_V2_CONFIG1_ONE_CYCLE;
1231         tmp |= NFC_V2_CONFIG1_ECC_MODE_4;
1232         writenfc(tmp, &host->regs->config1);
1233         if (host->pagesize_2k)
1234                 writenfc(64/2, &host->regs->spare_area_size);
1235         else
1236                 writenfc(16/2, &host->regs->spare_area_size);
1237 #endif
1238
1239         /*
1240          * preset operation
1241          * Unlock the internal RAM Buffer
1242          */
1243         writenfc(0x2, &host->regs->config);
1244
1245         /* Blocks to be unlocked */
1246         writenfc(0x0, &host->regs->unlockstart_blkaddr);
1247         /* Originally (Freescale LTIB 2.6.21) 0x4000 was written to the
1248          * unlockend_blkaddr, but the magic 0x4000 does not always work
1249          * when writing more than some 32 megabytes (on 2k page nands)
1250          * However 0xFFFF doesn't seem to have this kind
1251          * of limitation (tried it back and forth several times).
1252          * The linux kernel driver sets this to 0xFFFF for the v2 controller
1253          * only, but probably this was not tested there for v1.
1254          * The very same limitation seems to apply to this kernel driver.
1255          * This might be NAND chip specific and the i.MX31 datasheet is
1256          * extremely vague about the semantics of this register.
1257          */
1258         writenfc(0xFFFF, &host->regs->unlockend_blkaddr);
1259
1260         /* Unlock Block Command for given address range */
1261         writenfc(0x4, &host->regs->wrprot);
1262 #elif defined(MXC_NFC_V3_2)
1263         writenfc(NFC_V3_CONFIG1_RBA(0), &host->regs->config1);
1264         writenfc(NFC_V3_IPC_CREQ, &host->ip_regs->ipc);
1265
1266         /* Unlock the internal RAM Buffer */
1267         writenfc(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1268                         &host->ip_regs->wrprot);
1269
1270         /* Blocks to be unlocked */
1271         for (tmp = 0; tmp < CONFIG_SYS_NAND_MAX_CHIPS; tmp++)
1272                 writenfc(0x0 | 0xFFFF << 16,
1273                                 &host->ip_regs->wrprot_unlock_blkaddr[tmp]);
1274
1275         writenfc(0, &host->ip_regs->ipc);
1276
1277         tmp = readnfc(&host->ip_regs->config2);
1278         tmp &= ~(NFC_V3_CONFIG2_SPAS_MASK | NFC_V3_CONFIG2_EDC_MASK |
1279                         NFC_V3_CONFIG2_ECC_MODE_8 | NFC_V3_CONFIG2_PS_MASK);
1280         tmp |= NFC_V3_CONFIG2_ONE_CYCLE;
1281
1282         if (host->pagesize_2k) {
1283                 tmp |= NFC_V3_CONFIG2_SPAS(64/2);
1284                 tmp |= NFC_V3_CONFIG2_PS_2048;
1285         } else {
1286                 tmp |= NFC_V3_CONFIG2_SPAS(16/2);
1287                 tmp |= NFC_V3_CONFIG2_PS_512;
1288         }
1289
1290         writenfc(tmp, &host->ip_regs->config2);
1291
1292         tmp = NFC_V3_CONFIG3_NUM_OF_DEVS(0) |
1293                         NFC_V3_CONFIG3_NO_SDMA |
1294                         NFC_V3_CONFIG3_RBB_MODE |
1295                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1296                         NFC_V3_CONFIG3_ADD_OP(0);
1297
1298         if (!(this->options & NAND_BUSWIDTH_16))
1299                 tmp |= NFC_V3_CONFIG3_FW8;
1300
1301         writenfc(tmp, &host->ip_regs->config3);
1302
1303         writenfc(0, &host->ip_regs->delay_line);
1304 #endif
1305
1306         return 0;
1307 }