2 * LPC32xx SLC NAND flash controller driver
4 * (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/errno.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/sys_proto.h>
16 struct lpc32xx_nand_slc_regs {
35 #define CFG_CE_LOW (1 << 5)
38 #define CTRL_SW_RESET (1 << 2)
41 #define STAT_NAND_READY (1 << 0)
43 /* INT_STAT register */
44 #define INT_STAT_TC (1 << 1)
45 #define INT_STAT_RDY (1 << 0)
47 /* TAC register bits, be aware of overflows */
48 #define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28)
49 #define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24)
50 #define TAC_W_HOLD(n) (max_t(uint32_t, (n), 0xF) << 20)
51 #define TAC_W_SETUP(n) (max_t(uint32_t, (n), 0xF) << 16)
52 #define TAC_R_RDY(n) (max_t(uint32_t, (n), 0xF) << 12)
53 #define TAC_R_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 8)
54 #define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4)
55 #define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0)
57 static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs
58 = (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE;
60 static void lpc32xx_nand_init(void)
62 uint32_t hclk = get_hclk_clk_rate();
64 /* Reset SLC NAND controller */
65 writel(CTRL_SW_RESET, &lpc32xx_nand_slc_regs->ctrl);
67 /* 8-bit bus, no DMA, no ECC, ordinary CE signal */
68 writel(0, &lpc32xx_nand_slc_regs->cfg);
70 /* Interrupts disabled and cleared */
71 writel(0, &lpc32xx_nand_slc_regs->ien);
72 writel(INT_STAT_TC | INT_STAT_RDY,
73 &lpc32xx_nand_slc_regs->icr);
75 /* Configure NAND flash timings */
76 writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
77 TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
78 TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
79 TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
80 TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
81 TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
82 TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
83 TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
84 &lpc32xx_nand_slc_regs->tac);
87 static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
88 int cmd, unsigned int ctrl)
90 debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
93 setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
95 clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
97 if (cmd == NAND_CMD_NONE)
101 writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->cmd);
102 else if (ctrl & NAND_ALE)
103 writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->addr);
106 static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
108 return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
111 static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
114 *buf++ = readl(&lpc32xx_nand_slc_regs->data);
117 static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
119 return readl(&lpc32xx_nand_slc_regs->data);
122 static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
125 writel(*buf++, &lpc32xx_nand_slc_regs->data);
128 static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
130 writel(byte, &lpc32xx_nand_slc_regs->data);
134 * LPC32xx has only one SLC NAND controller, don't utilize
135 * CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
136 * both in SPL NAND and U-boot images.
138 int board_nand_init(struct nand_chip *lpc32xx_chip)
140 lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
141 lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
144 * Hardware ECC calculation is not supported by the driver,
145 * because it requires DMA support, see LPC32x0 User Manual,
146 * note after SLC_ECC register description (UM10326, p.198)
148 lpc32xx_chip->ecc.mode = NAND_ECC_SOFT;
151 * The implementation of these functions is quite common, but
152 * they MUST be defined, because access to data register
153 * is strictly 32-bit aligned.
155 lpc32xx_chip->read_buf = lpc32xx_read_buf;
156 lpc32xx_chip->read_byte = lpc32xx_read_byte;
157 lpc32xx_chip->write_buf = lpc32xx_write_buf;
158 lpc32xx_chip->write_byte = lpc32xx_write_byte;
161 * Use default ECC layout, but these values are predefined
162 * for both small and large page NAND flash devices.
164 lpc32xx_chip->ecc.size = 256;
165 lpc32xx_chip->ecc.bytes = 3;
166 lpc32xx_chip->ecc.strength = 1;
168 #if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
169 lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
172 /* Initialize NAND interface */