2 * NAND boot for Freescale Integrated Flash Controller, NAND FCM
4 * Copyright 2011 Freescale Semiconductor, Inc.
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <linux/mtd/nand.h>
15 static inline int is_blank(uchar *addr, int page_size)
19 for (i = 0; i < page_size; i++) {
20 if (__raw_readb(&addr[i]) != 0xff)
25 * For the SPL, don't worry about uncorrectable errors
26 * where the main area is all FFs but shouldn't be.
31 /* returns nonzero if entire page is blank */
32 static inline int check_read_ecc(uchar *buf, u32 *eccstat,
33 unsigned int bufnum, int page_size)
35 u32 reg = eccstat[bufnum / 4];
36 int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
38 if (errors == 0xf) { /* uncorrectable */
39 /* Blank pages fail hw ECC checks */
40 if (is_blank(buf, page_size))
51 static inline void nand_wait(uchar *buf, int bufnum, int page_size)
53 struct fsl_ifc *ifc = IFC_BASE_ADDR;
56 int bufperpage = page_size / 512;
60 bufnum_end = bufnum + bufperpage - 1;
63 status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
64 } while (!(status & IFC_NAND_EVTER_STAT_OPC));
66 if (status & IFC_NAND_EVTER_STAT_FTOER) {
67 puts("flash time out error\n");
72 for (i = bufnum / 4; i <= bufnum_end / 4; i++)
73 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
75 for (i = bufnum; i <= bufnum_end; i++) {
76 if (check_read_ecc(buf, eccstat, i, page_size))
80 ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
83 static inline int bad_block(uchar *marker, int port_size)
86 return __raw_readb(marker) != 0xff;
88 return __raw_readw((u16 *)marker) != 0xffff;
91 int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
93 struct fsl_ifc *ifc = IFC_BASE_ADDR;
94 uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
100 int bufnum_mask, bufnum;
110 /* Get NAND Flash configuration */
111 csor = CONFIG_SYS_NAND_CSOR;
112 cspr = CONFIG_SYS_NAND_CSPR;
114 port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
116 if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
119 } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
122 } else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
134 32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
136 blk_size = pages_per_blk * page_size;
138 /* Open Full SRAM mapping for spare are access */
139 ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
141 /* Clear Boot events */
142 ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
144 /* Program FIR/FCR for Large/Small page */
145 if (page_size > 512) {
146 ifc_out32(&ifc->ifc_nand.nand_fir0,
147 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
148 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
149 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
150 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
151 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
152 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
154 ifc_out32(&ifc->ifc_nand.nand_fcr0,
155 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
156 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
158 ifc_out32(&ifc->ifc_nand.nand_fir0,
159 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
160 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
161 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
162 (IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
163 ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
165 ifc_out32(&ifc->ifc_nand.nand_fcr0,
166 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
169 /* Program FBCR = 0 for full page read */
170 ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
172 /* Read and copy u-boot on SDRAM from NAND device, In parallel
173 * check for Bad block if found skip it and read continue to
176 while (pos < uboot_size) {
179 pg_no = offs / page_size;
180 bufnum = pg_no & bufnum_mask;
181 sram_addr = bufnum * page_size * 2;
183 ifc_out32(&ifc->ifc_nand.row0, pg_no);
184 ifc_out32(&ifc->ifc_nand.col0, 0);
186 ifc_out32(&ifc->ifc_nand.nandseq_strt,
187 IFC_NAND_SEQ_STRT_FIR_STRT);
189 /* wait for read to complete */
190 nand_wait(&buf[sram_addr], bufnum, page_size);
193 * If either of the first two pages are marked bad,
194 * continue to the next block.
197 bad_block(&buf[sram_addr + page_size + bad_marker],
200 offs = (offs + blk_size) & ~(blk_size - 1);
201 pos &= ~(blk_size - 1);
205 for (j = 0; j < page_size; j++)
206 dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
210 } while ((offs & (blk_size - 1)) && (pos < uboot_size));
217 * Main entrypoint for NAND Boot. It's necessary that SDRAM is already
218 * configured and available since this code loads the main U-boot image
219 * from NAND into SDRAM and starts from there.
223 __attribute__((noreturn)) void (*uboot)(void);
225 * Load U-Boot image from NAND into RAM
227 nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
228 CONFIG_SYS_NAND_U_BOOT_SIZE,
229 (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
231 #ifdef CONFIG_NAND_ENV_DST
232 nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
233 (uchar *)CONFIG_NAND_ENV_DST);
235 #ifdef CONFIG_ENV_OFFSET_REDUND
236 nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
237 (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
241 * Jump to U-Boot image
243 #ifdef CONFIG_SPL_FLUSH_IMAGE
245 * Clean d-cache and invalidate i-cache, to
246 * make sure that no stale data is executed.
248 flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
250 uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;