1 /* Integrated Flash Controller NAND Machine Driver
3 * Copyright (c) 2012 Freescale Semiconductor, Inc
5 * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/mtd/mtd.h>
15 #include <linux/mtd/nand.h>
16 #include <linux/mtd/nand_ecc.h>
19 #include <asm/errno.h>
20 #include <asm/fsl_ifc.h>
22 #define FSL_IFC_V1_1_0 0x01010000
24 #define ERR_BYTE 0xFF /* Value returned for read bytes
26 #define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
31 /* mtd information per set */
33 struct nand_chip chip;
34 struct fsl_ifc_ctrl *ctrl;
37 int bank; /* Chip select bank number */
38 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
39 u8 __iomem *vbase; /* Chip select base virtual address */
42 /* overview of the fsl ifc controller */
44 struct nand_hw_control controller;
45 struct fsl_ifc_mtd *chips[MAX_BANKS];
49 uint8_t __iomem *addr; /* Address of assigned IFC buffer */
50 unsigned int cs_nand; /* On which chipsel NAND is connected */
51 unsigned int page; /* Last page written to / read from */
52 unsigned int read_bytes; /* Number of bytes read during command */
53 unsigned int column; /* Saved column from SEQIN */
54 unsigned int index; /* Pointer to next byte to 'read' */
55 unsigned int status; /* status read from NEESR after last op */
56 unsigned int oob; /* Non zero if operating on OOB data */
57 unsigned int eccread; /* Non zero for a full-page ECC read */
60 static struct fsl_ifc_ctrl *ifc_ctrl;
62 /* 512-byte page with 4-bit ECC, 8-bit */
63 static struct nand_ecclayout oob_512_8bit_ecc4 = {
65 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
66 .oobfree = { {0, 5}, {6, 2} },
69 /* 512-byte page with 4-bit ECC, 16-bit */
70 static struct nand_ecclayout oob_512_16bit_ecc4 = {
72 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
73 .oobfree = { {2, 6}, },
76 /* 2048-byte page size with 4-bit ECC */
77 static struct nand_ecclayout oob_2048_ecc4 = {
80 8, 9, 10, 11, 12, 13, 14, 15,
81 16, 17, 18, 19, 20, 21, 22, 23,
82 24, 25, 26, 27, 28, 29, 30, 31,
83 32, 33, 34, 35, 36, 37, 38, 39,
85 .oobfree = { {2, 6}, {40, 24} },
88 /* 4096-byte page size with 4-bit ECC */
89 static struct nand_ecclayout oob_4096_ecc4 = {
92 8, 9, 10, 11, 12, 13, 14, 15,
93 16, 17, 18, 19, 20, 21, 22, 23,
94 24, 25, 26, 27, 28, 29, 30, 31,
95 32, 33, 34, 35, 36, 37, 38, 39,
96 40, 41, 42, 43, 44, 45, 46, 47,
97 48, 49, 50, 51, 52, 53, 54, 55,
98 56, 57, 58, 59, 60, 61, 62, 63,
99 64, 65, 66, 67, 68, 69, 70, 71,
101 .oobfree = { {2, 6}, {72, 56} },
104 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
105 static struct nand_ecclayout oob_4096_ecc8 = {
108 8, 9, 10, 11, 12, 13, 14, 15,
109 16, 17, 18, 19, 20, 21, 22, 23,
110 24, 25, 26, 27, 28, 29, 30, 31,
111 32, 33, 34, 35, 36, 37, 38, 39,
112 40, 41, 42, 43, 44, 45, 46, 47,
113 48, 49, 50, 51, 52, 53, 54, 55,
114 56, 57, 58, 59, 60, 61, 62, 63,
115 64, 65, 66, 67, 68, 69, 70, 71,
116 72, 73, 74, 75, 76, 77, 78, 79,
117 80, 81, 82, 83, 84, 85, 86, 87,
118 88, 89, 90, 91, 92, 93, 94, 95,
119 96, 97, 98, 99, 100, 101, 102, 103,
120 104, 105, 106, 107, 108, 109, 110, 111,
121 112, 113, 114, 115, 116, 117, 118, 119,
122 120, 121, 122, 123, 124, 125, 126, 127,
123 128, 129, 130, 131, 132, 133, 134, 135,
125 .oobfree = { {2, 6}, {136, 82} },
130 * Generic flash bbt descriptors
132 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
133 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
135 static struct nand_bbt_descr bbt_main_descr = {
136 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
137 NAND_BBT_2BIT | NAND_BBT_VERSION,
138 .offs = 2, /* 0 on 8-bit small page */
142 .pattern = bbt_pattern,
145 static struct nand_bbt_descr bbt_mirror_descr = {
146 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
147 NAND_BBT_2BIT | NAND_BBT_VERSION,
148 .offs = 2, /* 0 on 8-bit small page */
152 .pattern = mirror_pattern,
156 * Set up the IFC hardware block and page address fields, and the ifc nand
157 * structure addr field to point to the correct IFC buffer in memory
159 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
161 struct nand_chip *chip = mtd->priv;
162 struct fsl_ifc_mtd *priv = chip->priv;
163 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
164 struct fsl_ifc *ifc = ctrl->regs;
167 ctrl->page = page_addr;
169 /* Program ROW0/COL0 */
170 out_be32(&ifc->ifc_nand.row0, page_addr);
171 out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
173 buf_num = page_addr & priv->bufnum_mask;
175 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
176 ctrl->index = column;
178 /* for OOB data point to the second half of the buffer */
180 ctrl->index += mtd->writesize;
183 static int is_blank(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
186 struct nand_chip *chip = mtd->priv;
187 struct fsl_ifc_mtd *priv = chip->priv;
188 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
189 u32 __iomem *main = (u32 *)addr;
190 u8 __iomem *oob = addr + mtd->writesize;
193 for (i = 0; i < mtd->writesize / 4; i++) {
194 if (__raw_readl(&main[i]) != 0xffffffff)
198 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
199 int pos = chip->ecc.layout->eccpos[i];
201 if (__raw_readb(&oob[pos]) != 0xff)
208 /* returns nonzero if entire page is blank */
209 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
210 u32 *eccstat, unsigned int bufnum)
212 u32 reg = eccstat[bufnum / 4];
215 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
221 * execute IFC NAND command and wait for it to complete
223 static int fsl_ifc_run_command(struct mtd_info *mtd)
225 struct nand_chip *chip = mtd->priv;
226 struct fsl_ifc_mtd *priv = chip->priv;
227 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
228 struct fsl_ifc *ifc = ctrl->regs;
233 /* set the chip select for NAND Transaction */
234 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
236 /* start read/write seq */
237 out_be32(&ifc->ifc_nand.nandseq_strt,
238 IFC_NAND_SEQ_STRT_FIR_STRT);
240 /* wait for NAND Machine complete flag or timeout */
241 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
243 while (end_tick > get_ticks()) {
244 ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
246 if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
250 out_be32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
252 if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
253 printf("%s: Flash Time Out Error\n", __func__);
254 if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
255 printf("%s: Write Protect Error\n", __func__);
259 int bufnum = ctrl->page & priv->bufnum_mask;
260 int sector = bufnum * chip->ecc.steps;
261 int sector_end = sector + chip->ecc.steps - 1;
263 for (i = sector / 4; i <= sector_end / 4; i++)
264 eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
266 for (i = sector; i <= sector_end; i++) {
267 errors = check_read_ecc(mtd, ctrl, eccstat, i);
271 * Uncorrectable error.
272 * OK only if the whole page is blank.
274 * We disable ECCER reporting due to erratum
275 * IFC-A002770 -- so report it now if we
276 * see an uncorrectable error in ECCSTAT.
278 if (!is_blank(mtd, ctrl, bufnum))
280 IFC_NAND_EVTER_STAT_ECCER;
284 mtd->ecc_stats.corrected += errors;
290 /* returns 0 on success otherwise non-zero) */
291 return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
294 static void fsl_ifc_do_read(struct nand_chip *chip,
296 struct mtd_info *mtd)
298 struct fsl_ifc_mtd *priv = chip->priv;
299 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
300 struct fsl_ifc *ifc = ctrl->regs;
302 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
303 if (mtd->writesize > 512) {
304 out_be32(&ifc->ifc_nand.nand_fir0,
305 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
306 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
307 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
308 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
309 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
310 out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
312 out_be32(&ifc->ifc_nand.nand_fcr0,
313 (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
314 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
316 out_be32(&ifc->ifc_nand.nand_fir0,
317 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
318 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
319 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
320 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
323 out_be32(&ifc->ifc_nand.nand_fcr0,
324 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
326 out_be32(&ifc->ifc_nand.nand_fcr0,
327 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
331 /* cmdfunc send commands to the IFC NAND Machine */
332 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
333 int column, int page_addr)
335 struct nand_chip *chip = mtd->priv;
336 struct fsl_ifc_mtd *priv = chip->priv;
337 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
338 struct fsl_ifc *ifc = ctrl->regs;
340 /* clear the read buffer */
341 ctrl->read_bytes = 0;
342 if (command != NAND_CMD_PAGEPROG)
346 /* READ0 read the entire buffer to use hardware ECC. */
347 case NAND_CMD_READ0: {
348 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
349 set_addr(mtd, 0, page_addr, 0);
351 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
352 ctrl->index += column;
354 if (chip->ecc.mode == NAND_ECC_HW)
357 fsl_ifc_do_read(chip, 0, mtd);
358 fsl_ifc_run_command(mtd);
362 /* READOOB reads only the OOB because no ECC is performed. */
363 case NAND_CMD_READOOB:
364 out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
365 set_addr(mtd, column, page_addr, 1);
367 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
369 fsl_ifc_do_read(chip, 1, mtd);
370 fsl_ifc_run_command(mtd);
374 /* READID must read all possible bytes while CEB is active */
375 case NAND_CMD_READID:
376 case NAND_CMD_PARAM: {
377 int timing = IFC_FIR_OP_RB;
378 if (command == NAND_CMD_PARAM)
379 timing = IFC_FIR_OP_RBCD;
381 out_be32(&ifc->ifc_nand.nand_fir0,
382 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
383 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
384 (timing << IFC_NAND_FIR0_OP2_SHIFT));
385 out_be32(&ifc->ifc_nand.nand_fcr0,
386 command << IFC_NAND_FCR0_CMD0_SHIFT);
387 out_be32(&ifc->ifc_nand.row3, column);
390 * although currently it's 8 bytes for READID, we always read
391 * the maximum 256 bytes(for PARAM)
393 out_be32(&ifc->ifc_nand.nand_fbcr, 256);
394 ctrl->read_bytes = 256;
396 set_addr(mtd, 0, 0, 0);
397 fsl_ifc_run_command(mtd);
401 /* ERASE1 stores the block and page address */
402 case NAND_CMD_ERASE1:
403 set_addr(mtd, 0, page_addr, 0);
406 /* ERASE2 uses the block and page address from ERASE1 */
407 case NAND_CMD_ERASE2:
408 out_be32(&ifc->ifc_nand.nand_fir0,
409 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
410 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
411 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
413 out_be32(&ifc->ifc_nand.nand_fcr0,
414 (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
415 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
417 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
418 ctrl->read_bytes = 0;
419 fsl_ifc_run_command(mtd);
422 /* SEQIN sets up the addr buffer and all registers except the length */
423 case NAND_CMD_SEQIN: {
425 ctrl->column = column;
428 if (mtd->writesize > 512) {
430 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
431 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
432 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
434 out_be32(&ifc->ifc_nand.nand_fir0,
435 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
436 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
437 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
438 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
439 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
440 out_be32(&ifc->ifc_nand.nand_fir1,
441 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
442 (IFC_FIR_OP_RDSTAT <<
443 IFC_NAND_FIR1_OP6_SHIFT) |
444 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
446 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
447 IFC_NAND_FCR0_CMD1_SHIFT) |
449 IFC_NAND_FCR0_CMD2_SHIFT) |
451 IFC_NAND_FCR0_CMD3_SHIFT));
453 out_be32(&ifc->ifc_nand.nand_fir0,
454 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
455 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
456 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
457 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
458 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
459 out_be32(&ifc->ifc_nand.nand_fir1,
460 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
461 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
462 (IFC_FIR_OP_RDSTAT <<
463 IFC_NAND_FIR1_OP7_SHIFT) |
464 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
466 if (column >= mtd->writesize)
468 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
471 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
474 if (column >= mtd->writesize) {
475 /* OOB area --> READOOB */
476 column -= mtd->writesize;
479 out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
480 set_addr(mtd, column, page_addr, ctrl->oob);
484 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
485 case NAND_CMD_PAGEPROG:
487 out_be32(&ifc->ifc_nand.nand_fbcr,
488 ctrl->index - ctrl->column);
490 out_be32(&ifc->ifc_nand.nand_fbcr, 0);
492 fsl_ifc_run_command(mtd);
495 case NAND_CMD_STATUS:
496 out_be32(&ifc->ifc_nand.nand_fir0,
497 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
498 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
499 out_be32(&ifc->ifc_nand.nand_fcr0,
500 NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
501 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
502 set_addr(mtd, 0, 0, 0);
503 ctrl->read_bytes = 1;
505 fsl_ifc_run_command(mtd);
507 /* Chip sometimes reporting write protect even when it's not */
508 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
512 out_be32(&ifc->ifc_nand.nand_fir0,
513 IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
514 out_be32(&ifc->ifc_nand.nand_fcr0,
515 NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
516 fsl_ifc_run_command(mtd);
520 printf("%s: error, unsupported command 0x%x.\n",
526 * Write buf to the IFC NAND Controller Data Buffer
528 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
530 struct nand_chip *chip = mtd->priv;
531 struct fsl_ifc_mtd *priv = chip->priv;
532 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
533 unsigned int bufsize = mtd->writesize + mtd->oobsize;
536 printf("%s of %d bytes", __func__, len);
541 if ((unsigned int)len > bufsize - ctrl->index) {
542 printf("%s beyond end of buffer "
543 "(%d requested, %u available)\n",
544 __func__, len, bufsize - ctrl->index);
545 len = bufsize - ctrl->index;
548 memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
553 * read a byte from either the IFC hardware buffer if it has any data left
554 * otherwise issue a command to read a single byte.
556 static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
558 struct nand_chip *chip = mtd->priv;
559 struct fsl_ifc_mtd *priv = chip->priv;
560 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
562 /* If there are still bytes in the IFC buffer, then use the
564 if (ctrl->index < ctrl->read_bytes)
565 return in_8(&ctrl->addr[ctrl->index++]);
567 printf("%s beyond end of buffer\n", __func__);
572 * Read two bytes from the IFC hardware buffer
573 * read function for 16-bit buswith
575 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
577 struct nand_chip *chip = mtd->priv;
578 struct fsl_ifc_mtd *priv = chip->priv;
579 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
583 * If there are still bytes in the IFC buffer, then use the
586 if (ctrl->index < ctrl->read_bytes) {
587 data = in_be16((uint16_t *)&ctrl->
590 return (uint8_t)data;
593 printf("%s beyond end of buffer\n", __func__);
598 * Read from the IFC Controller Data Buffer
600 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
602 struct nand_chip *chip = mtd->priv;
603 struct fsl_ifc_mtd *priv = chip->priv;
604 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
610 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
611 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
612 ctrl->index += avail;
615 printf("%s beyond end of buffer "
616 "(%d requested, %d available)\n",
617 __func__, len, avail);
621 * Verify buffer against the IFC Controller Data Buffer
623 static int fsl_ifc_verify_buf(struct mtd_info *mtd,
624 const u_char *buf, int len)
626 struct nand_chip *chip = mtd->priv;
627 struct fsl_ifc_mtd *priv = chip->priv;
628 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
632 printf("%s of %d bytes", __func__, len);
636 if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
637 printf("%s beyond end of buffer "
638 "(%d requested, %u available)\n",
639 __func__, len, ctrl->read_bytes - ctrl->index);
641 ctrl->index = ctrl->read_bytes;
645 for (i = 0; i < len; i++)
646 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
650 return i == len && ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
653 /* This function is called after Program and Erase Operations to
654 * check for success or failure.
656 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
658 struct fsl_ifc_mtd *priv = chip->priv;
659 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
660 struct fsl_ifc *ifc = ctrl->regs;
663 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
664 return NAND_STATUS_FAIL;
666 /* Use READ_STATUS command, but wait for the device to be ready */
667 out_be32(&ifc->ifc_nand.nand_fir0,
668 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
669 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
670 out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
671 IFC_NAND_FCR0_CMD0_SHIFT);
672 out_be32(&ifc->ifc_nand.nand_fbcr, 1);
673 set_addr(mtd, 0, 0, 0);
674 ctrl->read_bytes = 1;
676 fsl_ifc_run_command(mtd);
678 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
679 return NAND_STATUS_FAIL;
681 nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
683 /* Chip sometimes reporting write protect even when it's not */
684 nand_fsr = nand_fsr | NAND_STATUS_WP;
688 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
689 uint8_t *buf, int oob_required, int page)
691 struct fsl_ifc_mtd *priv = chip->priv;
692 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
694 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
695 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
697 if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
698 mtd->ecc_stats.failed++;
703 /* ECC will be calculated automatically, and errors will be detected in
706 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
707 const uint8_t *buf, int oob_required)
709 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
710 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
715 static void fsl_ifc_ctrl_init(void)
717 ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
721 ifc_ctrl->regs = IFC_BASE_ADDR;
723 /* clear event registers */
724 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_stat, ~0U);
725 out_be32(&ifc_ctrl->regs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
727 /* Enable error and event for any detected errors */
728 out_be32(&ifc_ctrl->regs->ifc_nand.nand_evter_en,
729 IFC_NAND_EVTER_EN_OPC_EN |
730 IFC_NAND_EVTER_EN_PGRDCMPL_EN |
731 IFC_NAND_EVTER_EN_FTOER_EN |
732 IFC_NAND_EVTER_EN_WPER_EN);
734 out_be32(&ifc_ctrl->regs->ifc_nand.ncfgr, 0x0);
737 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
741 static void fsl_ifc_sram_init(void)
743 struct fsl_ifc *ifc = ifc_ctrl->regs;
744 uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
747 cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT;
749 /* Save CSOR and CSOR_ext */
750 csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor);
751 csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext);
753 /* chage PageSize 8K and SpareSize 1K*/
754 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
755 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k);
756 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400);
759 out_be32(&ifc->ifc_nand.nand_fir0,
760 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
761 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
762 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
763 out_be32(&ifc->ifc_nand.nand_fcr0,
764 NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
765 out_be32(&ifc->ifc_nand.row3, 0x0);
767 out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
769 /* Program ROW0/COL0 */
770 out_be32(&ifc->ifc_nand.row0, 0x0);
771 out_be32(&ifc->ifc_nand.col0, 0x0);
773 /* set the chip select for NAND Transaction */
774 out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand);
777 out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
779 /* wait for NAND Machine complete flag or timeout */
780 end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
782 while (end_tick > get_ticks()) {
783 ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat);
785 if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
789 out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
791 /* Restore CSOR and CSOR_ext */
792 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor);
793 out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext);
796 static int fsl_ifc_chip_init(int devnum, u8 *addr)
798 struct mtd_info *mtd = &nand_info[devnum];
799 struct nand_chip *nand;
800 struct fsl_ifc_mtd *priv;
801 struct nand_ecclayout *layout;
802 uint32_t cspr = 0, csor = 0, ver = 0;
811 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
815 priv->ctrl = ifc_ctrl;
818 /* Find which chip select it is connected to.
820 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
821 phys_addr_t phys_addr = virt_to_phys(addr);
823 cspr = in_be32(&ifc_ctrl->regs->cspr_cs[priv->bank].cspr);
824 csor = in_be32(&ifc_ctrl->regs->csor_cs[priv->bank].csor);
826 if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
827 (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr)) {
828 ifc_ctrl->cs_nand = priv->bank << IFC_NAND_CSEL_SHIFT;
833 if (priv->bank >= MAX_BANKS) {
834 printf("%s: address did not match any "
835 "chip selects\n", __func__);
843 ifc_ctrl->chips[priv->bank] = priv;
845 /* fill in nand_chip structure */
846 /* set up function call table */
848 nand->write_buf = fsl_ifc_write_buf;
849 nand->read_buf = fsl_ifc_read_buf;
850 nand->verify_buf = fsl_ifc_verify_buf;
851 nand->select_chip = fsl_ifc_select_chip;
852 nand->cmdfunc = fsl_ifc_cmdfunc;
853 nand->waitfunc = fsl_ifc_wait;
855 /* set up nand options */
856 nand->bbt_td = &bbt_main_descr;
857 nand->bbt_md = &bbt_mirror_descr;
859 /* set up nand options */
860 nand->options = NAND_NO_SUBPAGE_WRITE;
861 nand->bbt_options = NAND_BBT_USE_FLASH;
863 if (cspr & CSPR_PORT_SIZE_16) {
864 nand->read_byte = fsl_ifc_read_byte16;
865 nand->options |= NAND_BUSWIDTH_16;
867 nand->read_byte = fsl_ifc_read_byte;
870 nand->controller = &ifc_ctrl->controller;
873 nand->ecc.read_page = fsl_ifc_read_page;
874 nand->ecc.write_page = fsl_ifc_write_page;
876 /* Hardware generates ECC per 512 Bytes */
877 nand->ecc.size = 512;
880 switch (csor & CSOR_NAND_PGS_MASK) {
881 case CSOR_NAND_PGS_512:
882 if (nand->options & NAND_BUSWIDTH_16) {
883 layout = &oob_512_16bit_ecc4;
885 layout = &oob_512_8bit_ecc4;
887 /* Avoid conflict with bad block marker */
888 bbt_main_descr.offs = 0;
889 bbt_mirror_descr.offs = 0;
892 nand->ecc.strength = 4;
893 priv->bufnum_mask = 15;
896 case CSOR_NAND_PGS_2K:
897 layout = &oob_2048_ecc4;
898 nand->ecc.strength = 4;
899 priv->bufnum_mask = 3;
902 case CSOR_NAND_PGS_4K:
903 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
904 CSOR_NAND_ECC_MODE_4) {
905 layout = &oob_4096_ecc4;
906 nand->ecc.strength = 4;
908 layout = &oob_4096_ecc8;
909 nand->ecc.strength = 8;
910 nand->ecc.bytes = 16;
913 priv->bufnum_mask = 1;
917 printf("ifc nand: bad csor %#x: bad page size\n", csor);
921 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
922 if (csor & CSOR_NAND_ECC_DEC_EN) {
923 nand->ecc.mode = NAND_ECC_HW;
924 nand->ecc.layout = layout;
926 nand->ecc.mode = NAND_ECC_SOFT;
929 ver = in_be32(&ifc_ctrl->regs->ifc_rev);
930 if (ver == FSL_IFC_V1_1_0)
933 ret = nand_scan_ident(mtd, 1, NULL);
937 ret = nand_scan_tail(mtd);
941 ret = nand_register(devnum);
947 #ifndef CONFIG_SYS_NAND_BASE_LIST
948 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
951 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
952 CONFIG_SYS_NAND_BASE_LIST;
954 void board_nand_init(void)
958 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
959 fsl_ifc_chip_init(i, (u8 *)base_address[i]);