drivers/mtd/nand/fsl_elbc_nand.c

   1 /* Freescale Enhanced Local Bus Controller FCM NAND driver
   2  *
   3  * Copyright (c) 2006-2008 Freescale Semiconductor
   4  *
   5  * Authors: Nick Spence <nick.spence@freescale.com>,
   6  *          Scott Wood <scottwood@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22
  23 #include <common.h>
  24 #include <malloc.h>
  25
  26 #include <linux/mtd/mtd.h>
  27 #include <linux/mtd/nand.h>
  28 #include <linux/mtd/nand_ecc.h>
  29
  30 #include <asm/io.h>
  31 #include <asm/errno.h>
  32
  33 #ifdef VERBOSE_DEBUG
  34 #define DEBUG_ELBC
  35 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
  36 #else
  37 #define vdbg(format, arg...) do {} while (0)
  38 #endif
  39
  40 /* Can't use plain old DEBUG because the linux mtd
  41  * headers define it as a macro.
  42  */
  43 #ifdef DEBUG_ELBC
  44 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
  45 #else
  46 #define dbg(format, arg...) do {} while (0)
  47 #endif
  48
  49 #define MAX_BANKS 8
  50 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  51 #define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
  52
  53 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
  54
  55 struct fsl_elbc_ctrl;
  56
  57 /* mtd information per set */
  58
  59 struct fsl_elbc_mtd {
  60         struct mtd_info mtd;
  61         struct nand_chip chip;
  62         struct fsl_elbc_ctrl *ctrl;
  63
  64         struct device *dev;
  65         int bank;               /* Chip select bank number           */
  66         u8 __iomem *vbase;      /* Chip select base virtual address  */
  67         int page_size;          /* NAND page size (0=512, 1=2048)    */
  68         unsigned int fmr;       /* FCM Flash Mode Register value     */
  69 };
  70
  71 /* overview of the fsl elbc controller */
  72
  73 struct fsl_elbc_ctrl {
  74         struct nand_hw_control controller;
  75         struct fsl_elbc_mtd *chips[MAX_BANKS];
  76
  77         /* device info */
  78         lbus83xx_t *regs;
  79         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  80         unsigned int page;       /* Last page written to / read from      */
  81         unsigned int read_bytes; /* Number of bytes read during command   */
  82         unsigned int column;     /* Saved column from SEQIN               */
  83         unsigned int index;      /* Pointer to next byte to 'read'        */
  84         unsigned int status;     /* status read from LTESR after last op  */
  85         unsigned int mdr;        /* UPM/FCM Data Register value           */
  86         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  87         unsigned int oob;        /* Non zero if operating on OOB data     */
  88         uint8_t *oob_poi;        /* Place to write ECC after read back    */
  89 };
  90
  91 /* These map to the positions used by the FCM hardware ECC generator */
  92
  93 /* Small Page FLASH with FMR[ECCM] = 0 */
  94 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  95         .eccbytes = 3,
  96         .eccpos = {6, 7, 8},
  97         .oobfree = { {0, 5}, {9, 7} },
  98         .oobavail = 12,
  99 };
 100
 101 /* Small Page FLASH with FMR[ECCM] = 1 */
 102 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
 103         .eccbytes = 3,
 104         .eccpos = {8, 9, 10},
 105         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
 106         .oobavail = 12,
 107 };
 108
 109 /* Large Page FLASH with FMR[ECCM] = 0 */
 110 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
 111         .eccbytes = 12,
 112         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
 113         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
 114         .oobavail = 48,
 115 };
 116
 117 /* Large Page FLASH with FMR[ECCM] = 1 */
 118 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 119         .eccbytes = 12,
 120         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 121         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 122         .oobavail = 48,
 123 };
 124
 125 /*
 126  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 127  * 1, so we have to adjust bad block pattern. This pattern should be used for
 128  * x8 chips only. So far hardware does not support x16 chips anyway.
 129  */
 130 static u8 scan_ff_pattern[] = { 0xff, };
 131
 132 static struct nand_bbt_descr largepage_memorybased = {
 133         .options = 0,
 134         .offs = 0,
 135         .len = 1,
 136         .pattern = scan_ff_pattern,
 137 };
 138
 139 /*
 140  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 141  * interfere with ECC positions, that's why we implement our own descriptors.
 142  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 143  */
 144 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 145 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 146
 147 static struct nand_bbt_descr bbt_main_descr = {
 148         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 149                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 150         .offs = 11,
 151         .len = 4,
 152         .veroffs = 15,
 153         .maxblocks = 4,
 154         .pattern = bbt_pattern,
 155 };
 156
 157 static struct nand_bbt_descr bbt_mirror_descr = {
 158         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 159                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 160         .offs = 11,
 161         .len = 4,
 162         .veroffs = 15,
 163         .maxblocks = 4,
 164         .pattern = mirror_pattern,
 165 };
 166
 167 /*=================================*/
 168
 169 /*
 170  * Set up the FCM hardware block and page address fields, and the fcm
 171  * structure addr field to point to the correct FCM buffer in memory
 172  */
 173 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 174 {
 175         struct nand_chip *chip = mtd->priv;
 176         struct fsl_elbc_mtd *priv = chip->priv;
 177         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 178         lbus83xx_t *lbc = ctrl->regs;
 179         int buf_num;
 180
 181         ctrl->page = page_addr;
 182
 183         if (priv->page_size) {
 184                 out_be32(&lbc->fbar, page_addr >> 6);
 185                 out_be32(&lbc->fpar,
 186                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 187                          (oob ? FPAR_LP_MS : 0) | column);
 188                 buf_num = (page_addr & 1) << 2;
 189         } else {
 190                 out_be32(&lbc->fbar, page_addr >> 5);
 191                 out_be32(&lbc->fpar,
 192                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 193                          (oob ? FPAR_SP_MS : 0) | column);
 194                 buf_num = page_addr & 7;
 195         }
 196
 197         ctrl->addr = priv->vbase + buf_num * 1024;
 198         ctrl->index = column;
 199
 200         /* for OOB data point to the second half of the buffer */
 201         if (oob)
 202                 ctrl->index += priv->page_size ? 2048 : 512;
 203
 204         vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 205              "index %x, pes %d ps %d\n",
 206              buf_num, ctrl->addr, priv->vbase, ctrl->index,
 207              chip->phys_erase_shift, chip->page_shift);
 208 }
 209
 210 /*
 211  * execute FCM command and wait for it to complete
 212  */
 213 static int fsl_elbc_run_command(struct mtd_info *mtd)
 214 {
 215         struct nand_chip *chip = mtd->priv;
 216         struct fsl_elbc_mtd *priv = chip->priv;
 217         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 218         lbus83xx_t *lbc = ctrl->regs;
 219         long long end_tick;
 220         u32 ltesr;
 221
 222         /* Setup the FMR[OP] to execute without write protection */
 223         out_be32(&lbc->fmr, priv->fmr | 3);
 224         if (ctrl->use_mdr)
 225                 out_be32(&lbc->mdr, ctrl->mdr);
 226
 227         vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 228              in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 229         vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
 230              "fbcr=%08x bank=%d\n",
 231              in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 232              in_be32(&lbc->fbcr), priv->bank);
 233
 234         /* execute special operation */
 235         out_be32(&lbc->lsor, priv->bank);
 236
 237         /* wait for FCM complete flag or timeout */
 238         end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
 239
 240         ltesr = 0;
 241         while (end_tick > get_ticks()) {
 242                 ltesr = in_be32(&lbc->ltesr);
 243                 if (ltesr & LTESR_CC)
 244                         break;
 245         }
 246
 247         ctrl->status = ltesr & LTESR_NAND_MASK;
 248         out_be32(&lbc->ltesr, ctrl->status);
 249         out_be32(&lbc->lteatr, 0);
 250
 251         /* store mdr value in case it was needed */
 252         if (ctrl->use_mdr)
 253                 ctrl->mdr = in_be32(&lbc->mdr);
 254
 255         ctrl->use_mdr = 0;
 256
 257         vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 258              ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 259
 260         /* returns 0 on success otherwise non-zero) */
 261         return ctrl->status == LTESR_CC ? 0 : -EIO;
 262 }
 263
 264 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 265 {
 266         struct fsl_elbc_mtd *priv = chip->priv;
 267         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 268         lbus83xx_t *lbc = ctrl->regs;
 269
 270         if (priv->page_size) {
 271                 out_be32(&lbc->fir,
 272                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 273                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 274                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 275                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 276                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 277
 278                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 279                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 280         } else {
 281                 out_be32(&lbc->fir,
 282                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 283                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 284                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 285                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 286
 287                 if (oob)
 288                         out_be32(&lbc->fcr,
 289                                  NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 290                 else
 291                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 292         }
 293 }
 294
 295 /* cmdfunc send commands to the FCM */
 296 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 297                              int column, int page_addr)
 298 {
 299         struct nand_chip *chip = mtd->priv;
 300         struct fsl_elbc_mtd *priv = chip->priv;
 301         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 302         lbus83xx_t *lbc = ctrl->regs;
 303
 304         ctrl->use_mdr = 0;
 305
 306         /* clear the read buffer */
 307         ctrl->read_bytes = 0;
 308         if (command != NAND_CMD_PAGEPROG)
 309                 ctrl->index = 0;
 310
 311         switch (command) {
 312         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 313         case NAND_CMD_READ1:
 314                 column += 256;
 315
 316         /* fall-through */
 317         case NAND_CMD_READ0:
 318                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 319                      " 0x%x, column: 0x%x.\n", page_addr, column);
 320
 321                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 322                 set_addr(mtd, 0, page_addr, 0);
 323
 324                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 325                 ctrl->index += column;
 326
 327                 fsl_elbc_do_read(chip, 0);
 328                 fsl_elbc_run_command(mtd);
 329                 return;
 330
 331         /* READOOB reads only the OOB because no ECC is performed. */
 332         case NAND_CMD_READOOB:
 333                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 334                      " 0x%x, column: 0x%x.\n", page_addr, column);
 335
 336                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 337                 set_addr(mtd, column, page_addr, 1);
 338
 339                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 340
 341                 fsl_elbc_do_read(chip, 1);
 342                 fsl_elbc_run_command(mtd);
 343
 344                 return;
 345
 346         /* READID must read all 5 possible bytes while CEB is active */
 347         case NAND_CMD_READID:
 348                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n");
 349
 350                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 351                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 352                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 353                 out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT);
 354                 /* 5 bytes for manuf, device and exts */
 355                 out_be32(&lbc->fbcr, 5);
 356                 ctrl->read_bytes = 5;
 357                 ctrl->use_mdr = 1;
 358                 ctrl->mdr = 0;
 359
 360                 set_addr(mtd, 0, 0, 0);
 361                 fsl_elbc_run_command(mtd);
 362                 return;
 363
 364         /* ERASE1 stores the block and page address */
 365         case NAND_CMD_ERASE1:
 366                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 367                      "page_addr: 0x%x.\n", page_addr);
 368                 set_addr(mtd, 0, page_addr, 0);
 369                 return;
 370
 371         /* ERASE2 uses the block and page address from ERASE1 */
 372         case NAND_CMD_ERASE2:
 373                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 374
 375                 out_be32(&lbc->fir,
 376                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 377                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 378                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 379
 380                 out_be32(&lbc->fcr,
 381                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 382                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 383
 384                 out_be32(&lbc->fbcr, 0);
 385                 ctrl->read_bytes = 0;
 386
 387                 fsl_elbc_run_command(mtd);
 388                 return;
 389
 390         /* SEQIN sets up the addr buffer and all registers except the length */
 391         case NAND_CMD_SEQIN: {
 392                 u32 fcr;
 393                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 394                      "page_addr: 0x%x, column: 0x%x.\n",
 395                      page_addr, column);
 396
 397                 ctrl->column = column;
 398                 ctrl->oob = 0;
 399
 400                 if (priv->page_size) {
 401                         fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
 402                               (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
 403
 404                         out_be32(&lbc->fir,
 405                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 406                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 407                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 408                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 409                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 410                 } else {
 411                         fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 412                               (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 413
 414                         out_be32(&lbc->fir,
 415                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 416                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 417                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 418                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 419                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 420                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 421
 422                         if (column >= mtd->writesize) {
 423                                 /* OOB area --> READOOB */
 424                                 column -= mtd->writesize;
 425                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 426                                 ctrl->oob = 1;
 427                         } else if (column < 256) {
 428                                 /* First 256 bytes --> READ0 */
 429                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 430                         } else {
 431                                 /* Second 256 bytes --> READ1 */
 432                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 433                         }
 434                 }
 435
 436                 out_be32(&lbc->fcr, fcr);
 437                 set_addr(mtd, column, page_addr, ctrl->oob);
 438                 return;
 439         }
 440
 441         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 442         case NAND_CMD_PAGEPROG: {
 443                 int full_page;
 444                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 445                      "writing %d bytes.\n", ctrl->index);
 446
 447                 /* if the write did not start at 0 or is not a full page
 448                  * then set the exact length, otherwise use a full page
 449                  * write so the HW generates the ECC.
 450                  */
 451                 if (ctrl->oob || ctrl->column != 0 ||
 452                     ctrl->index != mtd->writesize + mtd->oobsize) {
 453                         out_be32(&lbc->fbcr, ctrl->index);
 454                         full_page = 0;
 455                 } else {
 456                         out_be32(&lbc->fbcr, 0);
 457                         full_page = 1;
 458                 }
 459
 460                 fsl_elbc_run_command(mtd);
 461
 462                 /* Read back the page in order to fill in the ECC for the
 463                  * caller.  Is this really needed?
 464                  */
 465                 if (full_page && ctrl->oob_poi) {
 466                         out_be32(&lbc->fbcr, 3);
 467                         set_addr(mtd, 6, page_addr, 1);
 468
 469                         ctrl->read_bytes = mtd->writesize + 9;
 470
 471                         fsl_elbc_do_read(chip, 1);
 472                         fsl_elbc_run_command(mtd);
 473
 474                         memcpy_fromio(ctrl->oob_poi + 6,
 475                                       &ctrl->addr[ctrl->index], 3);
 476                         ctrl->index += 3;
 477                 }
 478
 479                 ctrl->oob_poi = NULL;
 480                 return;
 481         }
 482
 483         /* CMD_STATUS must read the status byte while CEB is active */
 484         /* Note - it does not wait for the ready line */
 485         case NAND_CMD_STATUS:
 486                 out_be32(&lbc->fir,
 487                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 488                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 489                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 490                 out_be32(&lbc->fbcr, 1);
 491                 set_addr(mtd, 0, 0, 0);
 492                 ctrl->read_bytes = 1;
 493
 494                 fsl_elbc_run_command(mtd);
 495
 496                 /* The chip always seems to report that it is
 497                  * write-protected, even when it is not.
 498                  */
 499                 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 500                 return;
 501
 502         /* RESET without waiting for the ready line */
 503         case NAND_CMD_RESET:
 504                 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 505                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 506                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 507                 fsl_elbc_run_command(mtd);
 508                 return;
 509
 510         default:
 511                 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 512                         command);
 513         }
 514 }
 515
 516 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 517 {
 518         /* The hardware does not seem to support multiple
 519          * chips per bank.
 520          */
 521 }
 522
 523 /*
 524  * Write buf to the FCM Controller Data Buffer
 525  */
 526 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 527 {
 528         struct nand_chip *chip = mtd->priv;
 529         struct fsl_elbc_mtd *priv = chip->priv;
 530         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 531         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 532
 533         if (len <= 0) {
 534                 printf("write_buf of %d bytes", len);
 535                 ctrl->status = 0;
 536                 return;
 537         }
 538
 539         if ((unsigned int)len > bufsize - ctrl->index) {
 540                 printf("write_buf beyond end of buffer "
 541                        "(%d requested, %u available)\n",
 542                        len, bufsize - ctrl->index);
 543                 len = bufsize - ctrl->index;
 544         }
 545
 546         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 547         /*
 548          * This is workaround for the weird elbc hangs during nand write,
 549          * Scott Wood says: "...perhaps difference in how long it takes a
 550          * write to make it through the localbus compared to a write to IMMR
 551          * is causing problems, and sync isn't helping for some reason."
 552          * Reading back the last byte helps though.
 553          */
 554         in_8(&ctrl->addr[ctrl->index] + len - 1);
 555
 556         ctrl->index += len;
 557 }
 558
 559 /*
 560  * read a byte from either the FCM hardware buffer if it has any data left
 561  * otherwise issue a command to read a single byte.
 562  */
 563 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 564 {
 565         struct nand_chip *chip = mtd->priv;
 566         struct fsl_elbc_mtd *priv = chip->priv;
 567         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 568
 569         /* If there are still bytes in the FCM, then use the next byte. */
 570         if (ctrl->index < ctrl->read_bytes)
 571                 return in_8(&ctrl->addr[ctrl->index++]);
 572
 573         printf("read_byte beyond end of buffer\n");
 574         return ERR_BYTE;
 575 }
 576
 577 /*
 578  * Read from the FCM Controller Data Buffer
 579  */
 580 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 581 {
 582         struct nand_chip *chip = mtd->priv;
 583         struct fsl_elbc_mtd *priv = chip->priv;
 584         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 585         int avail;
 586
 587         if (len < 0)
 588                 return;
 589
 590         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 591         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 592         ctrl->index += avail;
 593
 594         if (len > avail)
 595                 printf("read_buf beyond end of buffer "
 596                        "(%d requested, %d available)\n",
 597                        len, avail);
 598 }
 599
 600 /*
 601  * Verify buffer against the FCM Controller Data Buffer
 602  */
 603 static int fsl_elbc_verify_buf(struct mtd_info *mtd,
 604                                const u_char *buf, int len)
 605 {
 606         struct nand_chip *chip = mtd->priv;
 607         struct fsl_elbc_mtd *priv = chip->priv;
 608         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 609         int i;
 610
 611         if (len < 0) {
 612                 printf("write_buf of %d bytes", len);
 613                 return -EINVAL;
 614         }
 615
 616         if ((unsigned int)len > ctrl->read_bytes - ctrl->index) {
 617                 printf("verify_buf beyond end of buffer "
 618                        "(%d requested, %u available)\n",
 619                        len, ctrl->read_bytes - ctrl->index);
 620
 621                 ctrl->index = ctrl->read_bytes;
 622                 return -EINVAL;
 623         }
 624
 625         for (i = 0; i < len; i++)
 626                 if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i])
 627                         break;
 628
 629         ctrl->index += len;
 630         return i == len && ctrl->status == LTESR_CC ? 0 : -EIO;
 631 }
 632
 633 /* This function is called after Program and Erase Operations to
 634  * check for success or failure.
 635  */
 636 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 637 {
 638         struct fsl_elbc_mtd *priv = chip->priv;
 639         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 640         lbus83xx_t *lbc = ctrl->regs;
 641
 642         if (ctrl->status != LTESR_CC)
 643                 return NAND_STATUS_FAIL;
 644
 645         /* Use READ_STATUS command, but wait for the device to be ready */
 646         ctrl->use_mdr = 0;
 647         out_be32(&lbc->fir,
 648                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 649                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 650         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 651         out_be32(&lbc->fbcr, 1);
 652         set_addr(mtd, 0, 0, 0);
 653         ctrl->read_bytes = 1;
 654
 655         fsl_elbc_run_command(mtd);
 656
 657         if (ctrl->status != LTESR_CC)
 658                 return NAND_STATUS_FAIL;
 659
 660         /* The chip always seems to report that it is
 661          * write-protected, even when it is not.
 662          */
 663         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 664         return fsl_elbc_read_byte(mtd);
 665 }
 666
 667 static int fsl_elbc_read_page(struct mtd_info *mtd,
 668                               struct nand_chip *chip,
 669                               uint8_t *buf)
 670 {
 671         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 672         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 673
 674         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 675                 mtd->ecc_stats.failed++;
 676
 677         return 0;
 678 }
 679
 680 /* ECC will be calculated automatically, and errors will be detected in
 681  * waitfunc.
 682  */
 683 static void fsl_elbc_write_page(struct mtd_info *mtd,
 684                                 struct nand_chip *chip,
 685                                 const uint8_t *buf)
 686 {
 687         struct fsl_elbc_mtd *priv = chip->priv;
 688         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 689
 690         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 691         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 692
 693         ctrl->oob_poi = chip->oob_poi;
 694 }
 695
 696 static struct fsl_elbc_ctrl *elbc_ctrl;
 697
 698 static void fsl_elbc_ctrl_init(void)
 699 {
 700         immap_t *im = (immap_t *)CFG_IMMR;
 701
 702         elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 703         if (!elbc_ctrl)
 704                 return;
 705
 706         elbc_ctrl->regs = &im->lbus;
 707
 708         /* clear event registers */
 709         out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
 710         out_be32(&elbc_ctrl->regs->lteatr, 0);
 711
 712         /* Enable interrupts for any detected events */
 713         out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
 714
 715         elbc_ctrl->read_bytes = 0;
 716         elbc_ctrl->index = 0;
 717         elbc_ctrl->addr = NULL;
 718 }
 719
 720 int board_nand_init(struct nand_chip *nand)
 721 {
 722         struct fsl_elbc_mtd *priv;
 723         uint32_t br, or;
 724
 725         if (!elbc_ctrl) {
 726                 fsl_elbc_ctrl_init();
 727                 if (!elbc_ctrl)
 728                         return -1;
 729         }
 730
 731         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 732         if (!priv)
 733                 return -ENOMEM;
 734
 735         priv->ctrl = elbc_ctrl;
 736         priv->vbase = nand->IO_ADDR_R;
 737
 738         /* Find which chip select it is connected to.  It'd be nice
 739          * if we could pass more than one datum to the NAND driver...
 740          */
 741         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 742                 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
 743                 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 744
 745                 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
 746                     (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R)
 747                         break;
 748         }
 749
 750         if (priv->bank >= MAX_BANKS) {
 751                 printf("fsl_elbc_nand: address did not match any "
 752                        "chip selects\n");
 753                 return -ENODEV;
 754         }
 755
 756         elbc_ctrl->chips[priv->bank] = priv;
 757
 758         /* fill in nand_chip structure */
 759         /* set up function call table */
 760         nand->read_byte = fsl_elbc_read_byte;
 761         nand->write_buf = fsl_elbc_write_buf;
 762         nand->read_buf = fsl_elbc_read_buf;
 763         nand->verify_buf = fsl_elbc_verify_buf;
 764         nand->select_chip = fsl_elbc_select_chip;
 765         nand->cmdfunc = fsl_elbc_cmdfunc;
 766         nand->waitfunc = fsl_elbc_wait;
 767
 768         /* set up nand options */
 769         nand->bbt_td = &bbt_main_descr;
 770         nand->bbt_md = &bbt_mirror_descr;
 771
 772         /* set up nand options */
 773         nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR |
 774                         NAND_USE_FLASH_BBT;
 775
 776         nand->controller = &elbc_ctrl->controller;
 777         nand->priv = priv;
 778
 779         nand->ecc.read_page = fsl_elbc_read_page;
 780         nand->ecc.write_page = fsl_elbc_write_page;
 781
 782         /* If CS Base Register selects full hardware ECC then use it */
 783         if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 784                 nand->ecc.mode = NAND_ECC_HW;
 785
 786                 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 787                                    &fsl_elbc_oob_sp_eccm1 :
 788                                    &fsl_elbc_oob_sp_eccm0;
 789
 790                 nand->ecc.size = 512;
 791                 nand->ecc.bytes = 3;
 792                 nand->ecc.steps = 1;
 793         } else {
 794                 /* otherwise fall back to default software ECC */
 795                 nand->ecc.mode = NAND_ECC_SOFT;
 796         }
 797
 798         priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
 799
 800         /* Large-page-specific setup */
 801         if (or & OR_FCM_PGS) {
 802                 priv->page_size = 1;
 803                 nand->badblock_pattern = &largepage_memorybased;
 804
 805                 /* adjust ecc setup if needed */
 806                 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 807                         nand->ecc.steps = 4;
 808                         nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 809                                            &fsl_elbc_oob_lp_eccm1 :
 810                                            &fsl_elbc_oob_lp_eccm0;
 811                 }
 812         }
 813
 814         return 0;
 815 }