drivers/mtd/nand/fsl_elbc_nand.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /* Freescale Enhanced Local Bus Controller FCM NAND driver
   3  *
   4  * Copyright (c) 2006-2008 Freescale Semiconductor
   5  *
   6  * Authors: Nick Spence <nick.spence@freescale.com>,
   7  *          Scott Wood <scottwood@freescale.com>
   8  */
   9
  10 #include <common.h>
  11 #include <malloc.h>
  12 #include <nand.h>
  13
  14 #include <linux/mtd/mtd.h>
  15 #include <linux/mtd/rawnand.h>
  16 #include <linux/mtd/nand_ecc.h>
  17
  18 #include <asm/io.h>
  19 #include <linux/errno.h>
  20
  21 #ifdef VERBOSE_DEBUG
  22 #define DEBUG_ELBC
  23 #define vdbg(format, arg...) printf("DEBUG: " format, ##arg)
  24 #else
  25 #define vdbg(format, arg...) do {} while (0)
  26 #endif
  27
  28 /* Can't use plain old DEBUG because the linux mtd
  29  * headers define it as a macro.
  30  */
  31 #ifdef DEBUG_ELBC
  32 #define dbg(format, arg...) printf("DEBUG: " format, ##arg)
  33 #else
  34 #define dbg(format, arg...) do {} while (0)
  35 #endif
  36
  37 #define MAX_BANKS 8
  38 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
  39
  40 #define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
  41
  42 struct fsl_elbc_ctrl;
  43
  44 /* mtd information per set */
  45
  46 struct fsl_elbc_mtd {
  47         struct nand_chip chip;
  48         struct fsl_elbc_ctrl *ctrl;
  49
  50         struct device *dev;
  51         int bank;               /* Chip select bank number           */
  52         u8 __iomem *vbase;      /* Chip select base virtual address  */
  53         int page_size;          /* NAND page size (0=512, 1=2048)    */
  54         unsigned int fmr;       /* FCM Flash Mode Register value     */
  55 };
  56
  57 /* overview of the fsl elbc controller */
  58
  59 struct fsl_elbc_ctrl {
  60         struct nand_hw_control controller;
  61         struct fsl_elbc_mtd *chips[MAX_BANKS];
  62
  63         /* device info */
  64         fsl_lbc_t *regs;
  65         u8 __iomem *addr;        /* Address of assigned FCM buffer        */
  66         unsigned int page;       /* Last page written to / read from      */
  67         unsigned int read_bytes; /* Number of bytes read during command   */
  68         unsigned int column;     /* Saved column from SEQIN               */
  69         unsigned int index;      /* Pointer to next byte to 'read'        */
  70         unsigned int status;     /* status read from LTESR after last op  */
  71         unsigned int mdr;        /* UPM/FCM Data Register value           */
  72         unsigned int use_mdr;    /* Non zero if the MDR is to be set      */
  73         unsigned int oob;        /* Non zero if operating on OOB data     */
  74 };
  75
  76 /* These map to the positions used by the FCM hardware ECC generator */
  77
  78 /* Small Page FLASH with FMR[ECCM] = 0 */
  79 static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = {
  80         .eccbytes = 3,
  81         .eccpos = {6, 7, 8},
  82         .oobfree = { {0, 5}, {9, 7} },
  83 };
  84
  85 /* Small Page FLASH with FMR[ECCM] = 1 */
  86 static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = {
  87         .eccbytes = 3,
  88         .eccpos = {8, 9, 10},
  89         .oobfree = { {0, 5}, {6, 2}, {11, 5} },
  90 };
  91
  92 /* Large Page FLASH with FMR[ECCM] = 0 */
  93 static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = {
  94         .eccbytes = 12,
  95         .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56},
  96         .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} },
  97 };
  98
  99 /* Large Page FLASH with FMR[ECCM] = 1 */
 100 static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = {
 101         .eccbytes = 12,
 102         .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
 103         .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} },
 104 };
 105
 106 /*
 107  * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset
 108  * 1, so we have to adjust bad block pattern. This pattern should be used for
 109  * x8 chips only. So far hardware does not support x16 chips anyway.
 110  */
 111 static u8 scan_ff_pattern[] = { 0xff, };
 112
 113 static struct nand_bbt_descr largepage_memorybased = {
 114         .options = 0,
 115         .offs = 0,
 116         .len = 1,
 117         .pattern = scan_ff_pattern,
 118 };
 119
 120 /*
 121  * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt,
 122  * interfere with ECC positions, that's why we implement our own descriptors.
 123  * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0.
 124  */
 125 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
 126 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
 127
 128 static struct nand_bbt_descr bbt_main_descr = {
 129         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 130                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 131         .offs = 11,
 132         .len = 4,
 133         .veroffs = 15,
 134         .maxblocks = 4,
 135         .pattern = bbt_pattern,
 136 };
 137
 138 static struct nand_bbt_descr bbt_mirror_descr = {
 139         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
 140                    NAND_BBT_2BIT | NAND_BBT_VERSION,
 141         .offs = 11,
 142         .len = 4,
 143         .veroffs = 15,
 144         .maxblocks = 4,
 145         .pattern = mirror_pattern,
 146 };
 147
 148 /*=================================*/
 149
 150 /*
 151  * Set up the FCM hardware block and page address fields, and the fcm
 152  * structure addr field to point to the correct FCM buffer in memory
 153  */
 154 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
 155 {
 156         struct nand_chip *chip = mtd_to_nand(mtd);
 157         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 158         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 159         fsl_lbc_t *lbc = ctrl->regs;
 160         int buf_num;
 161
 162         ctrl->page = page_addr;
 163
 164         if (priv->page_size) {
 165                 out_be32(&lbc->fbar, page_addr >> 6);
 166                 out_be32(&lbc->fpar,
 167                          ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) |
 168                          (oob ? FPAR_LP_MS : 0) | column);
 169                 buf_num = (page_addr & 1) << 2;
 170         } else {
 171                 out_be32(&lbc->fbar, page_addr >> 5);
 172                 out_be32(&lbc->fpar,
 173                          ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) |
 174                          (oob ? FPAR_SP_MS : 0) | column);
 175                 buf_num = page_addr & 7;
 176         }
 177
 178         ctrl->addr = priv->vbase + buf_num * 1024;
 179         ctrl->index = column;
 180
 181         /* for OOB data point to the second half of the buffer */
 182         if (oob)
 183                 ctrl->index += priv->page_size ? 2048 : 512;
 184
 185         vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
 186              "index %x, pes %d ps %d\n",
 187              buf_num, ctrl->addr, priv->vbase, ctrl->index,
 188              chip->phys_erase_shift, chip->page_shift);
 189 }
 190
 191 /*
 192  * execute FCM command and wait for it to complete
 193  */
 194 static int fsl_elbc_run_command(struct mtd_info *mtd)
 195 {
 196         struct nand_chip *chip = mtd_to_nand(mtd);
 197         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 198         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 199         fsl_lbc_t *lbc = ctrl->regs;
 200         u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
 201         u32 time_start;
 202         u32 ltesr;
 203
 204         /* Setup the FMR[OP] to execute without write protection */
 205         out_be32(&lbc->fmr, priv->fmr | 3);
 206         if (ctrl->use_mdr)
 207                 out_be32(&lbc->mdr, ctrl->mdr);
 208
 209         vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n",
 210              in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr));
 211         vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x "
 212              "fbcr=%08x bank=%d\n",
 213              in_be32(&lbc->fbar), in_be32(&lbc->fpar),
 214              in_be32(&lbc->fbcr), priv->bank);
 215
 216         /* execute special operation */
 217         out_be32(&lbc->lsor, priv->bank);
 218
 219         /* wait for FCM complete flag or timeout */
 220         time_start = get_timer(0);
 221
 222         ltesr = 0;
 223         while (get_timer(time_start) < timeo) {
 224                 ltesr = in_be32(&lbc->ltesr);
 225                 if (ltesr & LTESR_CC)
 226                         break;
 227         }
 228
 229         ctrl->status = ltesr & LTESR_NAND_MASK;
 230         out_be32(&lbc->ltesr, ctrl->status);
 231         out_be32(&lbc->lteatr, 0);
 232
 233         /* store mdr value in case it was needed */
 234         if (ctrl->use_mdr)
 235                 ctrl->mdr = in_be32(&lbc->mdr);
 236
 237         ctrl->use_mdr = 0;
 238
 239         vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n",
 240              ctrl->status, ctrl->mdr, in_be32(&lbc->fmr));
 241
 242         /* returns 0 on success otherwise non-zero) */
 243         return ctrl->status == LTESR_CC ? 0 : -EIO;
 244 }
 245
 246 static void fsl_elbc_do_read(struct nand_chip *chip, int oob)
 247 {
 248         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 249         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 250         fsl_lbc_t *lbc = ctrl->regs;
 251
 252         if (priv->page_size) {
 253                 out_be32(&lbc->fir,
 254                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 255                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 256                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 257                          (FIR_OP_CW1 << FIR_OP3_SHIFT) |
 258                          (FIR_OP_RBW << FIR_OP4_SHIFT));
 259
 260                 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
 261                                     (NAND_CMD_READSTART << FCR_CMD1_SHIFT));
 262         } else {
 263                 out_be32(&lbc->fir,
 264                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 265                          (FIR_OP_CA  << FIR_OP1_SHIFT) |
 266                          (FIR_OP_PA  << FIR_OP2_SHIFT) |
 267                          (FIR_OP_RBW << FIR_OP3_SHIFT));
 268
 269                 if (oob)
 270                         out_be32(&lbc->fcr,
 271                                  NAND_CMD_READOOB << FCR_CMD0_SHIFT);
 272                 else
 273                         out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT);
 274         }
 275 }
 276
 277 /* cmdfunc send commands to the FCM */
 278 static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command,
 279                              int column, int page_addr)
 280 {
 281         struct nand_chip *chip = mtd_to_nand(mtd);
 282         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 283         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 284         fsl_lbc_t *lbc = ctrl->regs;
 285
 286         ctrl->use_mdr = 0;
 287
 288         /* clear the read buffer */
 289         ctrl->read_bytes = 0;
 290         if (command != NAND_CMD_PAGEPROG)
 291                 ctrl->index = 0;
 292
 293         switch (command) {
 294         /* READ0 and READ1 read the entire buffer to use hardware ECC. */
 295         case NAND_CMD_READ1:
 296                 column += 256;
 297
 298         /* fall-through */
 299         case NAND_CMD_READ0:
 300                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:"
 301                      " 0x%x, column: 0x%x.\n", page_addr, column);
 302
 303                 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */
 304                 set_addr(mtd, 0, page_addr, 0);
 305
 306                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 307                 ctrl->index += column;
 308
 309                 fsl_elbc_do_read(chip, 0);
 310                 fsl_elbc_run_command(mtd);
 311                 return;
 312
 313         /* READOOB reads only the OOB because no ECC is performed. */
 314         case NAND_CMD_READOOB:
 315                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:"
 316                      " 0x%x, column: 0x%x.\n", page_addr, column);
 317
 318                 out_be32(&lbc->fbcr, mtd->oobsize - column);
 319                 set_addr(mtd, column, page_addr, 1);
 320
 321                 ctrl->read_bytes = mtd->writesize + mtd->oobsize;
 322
 323                 fsl_elbc_do_read(chip, 1);
 324                 fsl_elbc_run_command(mtd);
 325
 326                 return;
 327
 328         /* READID must read all 5 possible bytes while CEB is active */
 329         case NAND_CMD_READID:
 330         case NAND_CMD_PARAM:
 331                 vdbg("fsl_elbc_cmdfunc: NAND_CMD 0x%x.\n", command);
 332
 333                 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 334                                     (FIR_OP_UA  << FIR_OP1_SHIFT) |
 335                                     (FIR_OP_RBW << FIR_OP2_SHIFT));
 336                 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT);
 337                 /*
 338                  * although currently it's 8 bytes for READID, we always read
 339                  * the maximum 256 bytes(for PARAM)
 340                  */
 341                 out_be32(&lbc->fbcr, 256);
 342                 ctrl->read_bytes = 256;
 343                 ctrl->use_mdr = 1;
 344                 ctrl->mdr = column;
 345                 set_addr(mtd, 0, 0, 0);
 346                 fsl_elbc_run_command(mtd);
 347                 return;
 348
 349         /* ERASE1 stores the block and page address */
 350         case NAND_CMD_ERASE1:
 351                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, "
 352                      "page_addr: 0x%x.\n", page_addr);
 353                 set_addr(mtd, 0, page_addr, 0);
 354                 return;
 355
 356         /* ERASE2 uses the block and page address from ERASE1 */
 357         case NAND_CMD_ERASE2:
 358                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n");
 359
 360                 out_be32(&lbc->fir,
 361                          (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 362                          (FIR_OP_PA  << FIR_OP1_SHIFT) |
 363                          (FIR_OP_CM1 << FIR_OP2_SHIFT));
 364
 365                 out_be32(&lbc->fcr,
 366                          (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) |
 367                          (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT));
 368
 369                 out_be32(&lbc->fbcr, 0);
 370                 ctrl->read_bytes = 0;
 371
 372                 fsl_elbc_run_command(mtd);
 373                 return;
 374
 375         /* SEQIN sets up the addr buffer and all registers except the length */
 376         case NAND_CMD_SEQIN: {
 377                 u32 fcr;
 378                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, "
 379                      "page_addr: 0x%x, column: 0x%x.\n",
 380                      page_addr, column);
 381
 382                 ctrl->column = column;
 383                 ctrl->oob = 0;
 384
 385                 if (priv->page_size) {
 386                         fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) |
 387                               (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT);
 388
 389                         out_be32(&lbc->fir,
 390                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 391                                  (FIR_OP_CA  << FIR_OP1_SHIFT) |
 392                                  (FIR_OP_PA  << FIR_OP2_SHIFT) |
 393                                  (FIR_OP_WB  << FIR_OP3_SHIFT) |
 394                                  (FIR_OP_CW1 << FIR_OP4_SHIFT));
 395                 } else {
 396                         fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) |
 397                               (NAND_CMD_SEQIN << FCR_CMD2_SHIFT);
 398
 399                         out_be32(&lbc->fir,
 400                                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 401                                  (FIR_OP_CM2 << FIR_OP1_SHIFT) |
 402                                  (FIR_OP_CA  << FIR_OP2_SHIFT) |
 403                                  (FIR_OP_PA  << FIR_OP3_SHIFT) |
 404                                  (FIR_OP_WB  << FIR_OP4_SHIFT) |
 405                                  (FIR_OP_CW1 << FIR_OP5_SHIFT));
 406
 407                         if (column >= mtd->writesize) {
 408                                 /* OOB area --> READOOB */
 409                                 column -= mtd->writesize;
 410                                 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT;
 411                                 ctrl->oob = 1;
 412                         } else if (column < 256) {
 413                                 /* First 256 bytes --> READ0 */
 414                                 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT;
 415                         } else {
 416                                 /* Second 256 bytes --> READ1 */
 417                                 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT;
 418                         }
 419                 }
 420
 421                 out_be32(&lbc->fcr, fcr);
 422                 set_addr(mtd, column, page_addr, ctrl->oob);
 423                 return;
 424         }
 425
 426         /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
 427         case NAND_CMD_PAGEPROG: {
 428                 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG "
 429                      "writing %d bytes.\n", ctrl->index);
 430
 431                 /* if the write did not start at 0 or is not a full page
 432                  * then set the exact length, otherwise use a full page
 433                  * write so the HW generates the ECC.
 434                  */
 435                 if (ctrl->oob || ctrl->column != 0 ||
 436                     ctrl->index != mtd->writesize + mtd->oobsize)
 437                         out_be32(&lbc->fbcr, ctrl->index);
 438                 else
 439                         out_be32(&lbc->fbcr, 0);
 440
 441                 fsl_elbc_run_command(mtd);
 442
 443                 return;
 444         }
 445
 446         /* CMD_STATUS must read the status byte while CEB is active */
 447         /* Note - it does not wait for the ready line */
 448         case NAND_CMD_STATUS:
 449                 out_be32(&lbc->fir,
 450                          (FIR_OP_CM0 << FIR_OP0_SHIFT) |
 451                          (FIR_OP_RBW << FIR_OP1_SHIFT));
 452                 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 453                 out_be32(&lbc->fbcr, 1);
 454                 set_addr(mtd, 0, 0, 0);
 455                 ctrl->read_bytes = 1;
 456
 457                 fsl_elbc_run_command(mtd);
 458
 459                 /* The chip always seems to report that it is
 460                  * write-protected, even when it is not.
 461                  */
 462                 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 463                 return;
 464
 465         /* RESET without waiting for the ready line */
 466         case NAND_CMD_RESET:
 467                 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n");
 468                 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT);
 469                 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT);
 470                 fsl_elbc_run_command(mtd);
 471                 return;
 472
 473         default:
 474                 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n",
 475                         command);
 476         }
 477 }
 478
 479 static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip)
 480 {
 481         /* The hardware does not seem to support multiple
 482          * chips per bank.
 483          */
 484 }
 485
 486 /*
 487  * Write buf to the FCM Controller Data Buffer
 488  */
 489 static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 490 {
 491         struct nand_chip *chip = mtd_to_nand(mtd);
 492         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 493         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 494         unsigned int bufsize = mtd->writesize + mtd->oobsize;
 495
 496         if (len <= 0) {
 497                 printf("write_buf of %d bytes", len);
 498                 ctrl->status = 0;
 499                 return;
 500         }
 501
 502         if ((unsigned int)len > bufsize - ctrl->index) {
 503                 printf("write_buf beyond end of buffer "
 504                        "(%d requested, %u available)\n",
 505                        len, bufsize - ctrl->index);
 506                 len = bufsize - ctrl->index;
 507         }
 508
 509         memcpy_toio(&ctrl->addr[ctrl->index], buf, len);
 510         /*
 511          * This is workaround for the weird elbc hangs during nand write,
 512          * Scott Wood says: "...perhaps difference in how long it takes a
 513          * write to make it through the localbus compared to a write to IMMR
 514          * is causing problems, and sync isn't helping for some reason."
 515          * Reading back the last byte helps though.
 516          */
 517         in_8(&ctrl->addr[ctrl->index] + len - 1);
 518
 519         ctrl->index += len;
 520 }
 521
 522 /*
 523  * read a byte from either the FCM hardware buffer if it has any data left
 524  * otherwise issue a command to read a single byte.
 525  */
 526 static u8 fsl_elbc_read_byte(struct mtd_info *mtd)
 527 {
 528         struct nand_chip *chip = mtd_to_nand(mtd);
 529         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 530         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 531
 532         /* If there are still bytes in the FCM, then use the next byte. */
 533         if (ctrl->index < ctrl->read_bytes)
 534                 return in_8(&ctrl->addr[ctrl->index++]);
 535
 536         printf("read_byte beyond end of buffer\n");
 537         return ERR_BYTE;
 538 }
 539
 540 /*
 541  * Read from the FCM Controller Data Buffer
 542  */
 543 static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 544 {
 545         struct nand_chip *chip = mtd_to_nand(mtd);
 546         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 547         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 548         int avail;
 549
 550         if (len < 0)
 551                 return;
 552
 553         avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
 554         memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail);
 555         ctrl->index += avail;
 556
 557         if (len > avail)
 558                 printf("read_buf beyond end of buffer "
 559                        "(%d requested, %d available)\n",
 560                        len, avail);
 561 }
 562
 563 /* This function is called after Program and Erase Operations to
 564  * check for success or failure.
 565  */
 566 static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip)
 567 {
 568         struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
 569         struct fsl_elbc_ctrl *ctrl = priv->ctrl;
 570         fsl_lbc_t *lbc = ctrl->regs;
 571
 572         if (ctrl->status != LTESR_CC)
 573                 return NAND_STATUS_FAIL;
 574
 575         /* Use READ_STATUS command, but wait for the device to be ready */
 576         ctrl->use_mdr = 0;
 577         out_be32(&lbc->fir,
 578                  (FIR_OP_CW0 << FIR_OP0_SHIFT) |
 579                  (FIR_OP_RBW << FIR_OP1_SHIFT));
 580         out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT);
 581         out_be32(&lbc->fbcr, 1);
 582         set_addr(mtd, 0, 0, 0);
 583         ctrl->read_bytes = 1;
 584
 585         fsl_elbc_run_command(mtd);
 586
 587         if (ctrl->status != LTESR_CC)
 588                 return NAND_STATUS_FAIL;
 589
 590         /* The chip always seems to report that it is
 591          * write-protected, even when it is not.
 592          */
 593         out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
 594         return fsl_elbc_read_byte(mtd);
 595 }
 596
 597 static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
 598                               uint8_t *buf, int oob_required, int page)
 599 {
 600         fsl_elbc_read_buf(mtd, buf, mtd->writesize);
 601         fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 602
 603         if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL)
 604                 mtd->ecc_stats.failed++;
 605
 606         return 0;
 607 }
 608
 609 /* ECC will be calculated automatically, and errors will be detected in
 610  * waitfunc.
 611  */
 612 static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
 613                                 const uint8_t *buf, int oob_required,
 614                                 int page)
 615 {
 616         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 617         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 618
 619         return 0;
 620 }
 621
 622 static struct fsl_elbc_ctrl *elbc_ctrl;
 623
 624 /* ECC will be calculated automatically, and errors will be detected in
 625  * waitfunc.
 626  */
 627 static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip,
 628                                 uint32_t offset, uint32_t data_len,
 629                                 const uint8_t *buf, int oob_required, int page)
 630 {
 631         fsl_elbc_write_buf(mtd, buf, mtd->writesize);
 632         fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 633
 634         return 0;
 635 }
 636
 637 static void fsl_elbc_ctrl_init(void)
 638 {
 639         elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL);
 640         if (!elbc_ctrl)
 641                 return;
 642
 643         elbc_ctrl->regs = LBC_BASE_ADDR;
 644
 645         /* clear event registers */
 646         out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
 647         out_be32(&elbc_ctrl->regs->lteatr, 0);
 648
 649         /* Enable interrupts for any detected events */
 650         out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK);
 651
 652         elbc_ctrl->read_bytes = 0;
 653         elbc_ctrl->index = 0;
 654         elbc_ctrl->addr = NULL;
 655 }
 656
 657 static int fsl_elbc_chip_init(int devnum, u8 *addr)
 658 {
 659         struct mtd_info *mtd;
 660         struct nand_chip *nand;
 661         struct fsl_elbc_mtd *priv;
 662         uint32_t br = 0, or = 0;
 663         int ret;
 664
 665         if (!elbc_ctrl) {
 666                 fsl_elbc_ctrl_init();
 667                 if (!elbc_ctrl)
 668                         return -1;
 669         }
 670
 671         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 672         if (!priv)
 673                 return -ENOMEM;
 674
 675         priv->ctrl = elbc_ctrl;
 676         priv->vbase = addr;
 677
 678         /* Find which chip select it is connected to.  It'd be nice
 679          * if we could pass more than one datum to the NAND driver...
 680          */
 681         for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
 682                 phys_addr_t phys_addr = virt_to_phys(addr);
 683
 684                 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br);
 685                 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 686
 687                 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM &&
 688                     (br & or & BR_BA) == BR_PHYS_ADDR(phys_addr))
 689                         break;
 690         }
 691
 692         if (priv->bank >= MAX_BANKS) {
 693                 printf("fsl_elbc_nand: address did not match any "
 694                        "chip selects\n");
 695                 kfree(priv);
 696                 return -ENODEV;
 697         }
 698
 699         nand = &priv->chip;
 700         mtd = nand_to_mtd(nand);
 701
 702         elbc_ctrl->chips[priv->bank] = priv;
 703
 704         /* fill in nand_chip structure */
 705         /* set up function call table */
 706         nand->read_byte = fsl_elbc_read_byte;
 707         nand->write_buf = fsl_elbc_write_buf;
 708         nand->read_buf = fsl_elbc_read_buf;
 709         nand->select_chip = fsl_elbc_select_chip;
 710         nand->cmdfunc = fsl_elbc_cmdfunc;
 711         nand->waitfunc = fsl_elbc_wait;
 712
 713         /* set up nand options */
 714         nand->bbt_td = &bbt_main_descr;
 715         nand->bbt_md = &bbt_mirror_descr;
 716
 717         /* set up nand options */
 718         nand->options = NAND_NO_SUBPAGE_WRITE;
 719         nand->bbt_options = NAND_BBT_USE_FLASH;
 720
 721         nand->controller = &elbc_ctrl->controller;
 722         nand_set_controller_data(nand, priv);
 723
 724         nand->ecc.read_page = fsl_elbc_read_page;
 725         nand->ecc.write_page = fsl_elbc_write_page;
 726         nand->ecc.write_subpage = fsl_elbc_write_subpage;
 727
 728         priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT);
 729
 730         /* If CS Base Register selects full hardware ECC then use it */
 731         if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 732                 nand->ecc.mode = NAND_ECC_HW;
 733
 734                 nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 735                                    &fsl_elbc_oob_sp_eccm1 :
 736                                    &fsl_elbc_oob_sp_eccm0;
 737
 738                 nand->ecc.size = 512;
 739                 nand->ecc.bytes = 3;
 740                 nand->ecc.steps = 1;
 741                 nand->ecc.strength = 1;
 742         } else {
 743                 /* otherwise fall back to software ECC */
 744 #if defined(CONFIG_NAND_ECC_BCH)
 745                 nand->ecc.mode = NAND_ECC_SOFT_BCH;
 746 #else
 747                 nand->ecc.mode = NAND_ECC_SOFT;
 748 #endif
 749         }
 750
 751         ret = nand_scan_ident(mtd, 1, NULL);
 752         if (ret)
 753                 return ret;
 754
 755         /* Large-page-specific setup */
 756         if (mtd->writesize == 2048) {
 757                 setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
 758                              OR_FCM_PGS);
 759                 in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 760
 761                 priv->page_size = 1;
 762                 nand->badblock_pattern = &largepage_memorybased;
 763
 764                 /*
 765                  * Hardware expects small page has ECCM0, large page has
 766                  * ECCM1 when booting from NAND, and we follow that even
 767                  * when not booting from NAND.
 768                  */
 769                 priv->fmr |= FMR_ECCM;
 770
 771                 /* adjust ecc setup if needed */
 772                 if ((br & BR_DECC) == BR_DECC_CHK_GEN) {
 773                         nand->ecc.steps = 4;
 774                         nand->ecc.layout = (priv->fmr & FMR_ECCM) ?
 775                                            &fsl_elbc_oob_lp_eccm1 :
 776                                            &fsl_elbc_oob_lp_eccm0;
 777                 }
 778         } else if (mtd->writesize == 512) {
 779                 clrbits_be32(&elbc_ctrl->regs->bank[priv->bank].or,
 780                              OR_FCM_PGS);
 781                 in_be32(&elbc_ctrl->regs->bank[priv->bank].or);
 782         } else {
 783                 return -ENODEV;
 784         }
 785
 786         ret = nand_scan_tail(mtd);
 787         if (ret)
 788                 return ret;
 789
 790         ret = nand_register(devnum, mtd);
 791         if (ret)
 792                 return ret;
 793
 794         return 0;
 795 }
 796
 797 #ifndef CONFIG_SYS_NAND_BASE_LIST
 798 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
 799 #endif
 800
 801 static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
 802         CONFIG_SYS_NAND_BASE_LIST;
 803
 804 void board_nand_init(void)
 805 {
 806         int i;
 807
 808         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 809                 fsl_elbc_chip_init(i, (u8 *)base_address[i]);
 810 }