2 * NAND driver for TI DaVinci based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
11 * linux/drivers/mtd/nand/nand_davinci.c
15 * Copyright (C) 2006 Texas Instruments.
17 * ----------------------------------------------------------------------------
19 * SPDX-License-Identifier: GPL-2.0+
21 * ----------------------------------------------------------------------------
24 * This is a device driver for the NAND flash device found on the
25 * DaVinci board which utilizes the Samsung k9k2g08 part.
28 ver. 1.0: Feb 2005, Vinod/Sudhakar
35 #include <asm/ti-common/davinci_nand.h>
37 /* Definitions for 4-bit hardware ECC */
38 #define NAND_TIMEOUT 10240
39 #define NAND_ECC_BUSY 0xC
40 #define NAND_4BITECC_MASK 0x03FF03FF
41 #define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00
42 #define ECC_STATE_NO_ERR 0x0
43 #define ECC_STATE_TOO_MANY_ERRS 0x1
44 #define ECC_STATE_ERR_CORR_COMP_P 0x2
45 #define ECC_STATE_ERR_CORR_COMP_N 0x3
48 * Exploit the little endianness of the ARM to do multi-byte transfers
49 * per device read. This can perform over twice as quickly as individual
50 * byte transfers when buffer alignment is conducive.
52 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
53 * the address bus. On Davinci EVM platforms this has always been true.
55 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
57 struct nand_chip *chip = mtd->priv;
58 const u32 *nand = chip->IO_ADDR_R;
60 /* Make sure that buf is 32 bit aligned */
61 if (((int)buf & 0x3) != 0) {
62 if (((int)buf & 0x1) != 0) {
70 if (((int)buf & 0x3) != 0) {
72 *(u16 *)buf = readw(nand);
79 /* copy aligned data */
81 *(u32 *)buf = __raw_readl(nand);
86 /* mop up any remaining bytes */
89 *(u16 *)buf = readw(nand);
99 static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
102 struct nand_chip *chip = mtd->priv;
103 const u32 *nand = chip->IO_ADDR_W;
105 /* Make sure that buf is 32 bit aligned */
106 if (((int)buf & 0x3) != 0) {
107 if (((int)buf & 0x1) != 0) {
115 if (((int)buf & 0x3) != 0) {
117 writew(*(u16 *)buf, nand);
124 /* copy aligned data */
126 __raw_writel(*(u32 *)buf, nand);
131 /* mop up any remaining bytes */
134 writew(*(u16 *)buf, nand);
144 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
147 struct nand_chip *this = mtd->priv;
148 u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
150 if (ctrl & NAND_CTRL_CHANGE) {
151 IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
154 IO_ADDR_W |= MASK_CLE;
156 IO_ADDR_W |= MASK_ALE;
157 this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
160 if (cmd != NAND_CMD_NONE)
161 writeb(cmd, IO_ADDR_W);
164 #ifdef CONFIG_SYS_NAND_HW_ECC
166 static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
170 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
171 CONFIG_SYS_NAND_CS - 2]));
176 static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
180 /* reading the ECC result register resets the ECC calculation */
181 nand_davinci_readecc(mtd);
183 val = __raw_readl(&davinci_emif_regs->nandfcr);
184 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
185 val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
186 __raw_writel(val, &davinci_emif_regs->nandfcr);
189 static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
194 tmp = nand_davinci_readecc(mtd);
196 /* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
197 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
198 tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);
200 /* Invert so that erased block ECC is correct */
204 *ecc_code++ = tmp >> 8;
205 *ecc_code++ = tmp >> 16;
207 /* NOTE: the above code matches mainline Linux:
208 * .PQR.stu ==> ~PQRstu
210 * MontaVista/TI kernels encode those bytes differently, use
211 * complicated (and allegedly sometimes-wrong) correction code,
212 * and usually shipped with U-Boot that uses software ECC:
213 * .PQR.stu ==> PsQRtu
215 * If you need MV/TI compatible NAND I/O in U-Boot, it should
216 * be possible to (a) change the mangling above, (b) reverse
217 * that mangling in nand_davinci_correct_data() below.
223 static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
224 u_char *read_ecc, u_char *calc_ecc)
226 struct nand_chip *this = mtd->priv;
227 u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
229 u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
231 u_int32_t diff = ecc_calc ^ ecc_nand;
234 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
235 /* Correctable error */
236 if ((diff >> (12 + 3)) < this->ecc.size) {
237 uint8_t find_bit = 1 << ((diff >> 12) & 7);
238 uint32_t find_byte = diff >> (12 + 3);
240 dat[find_byte] ^= find_bit;
241 MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
242 "bit ECC error at offset: %d, bit: "
243 "%d\n", find_byte, find_bit);
248 } else if (!(diff & (diff - 1))) {
249 /* Single bit ECC error in the ECC itself,
251 MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
255 /* Uncorrectable error */
256 MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
262 #endif /* CONFIG_SYS_NAND_HW_ECC */
264 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
265 static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
266 #if defined(CONFIG_SYS_NAND_PAGE_2K)
268 #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
270 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
271 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
272 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
273 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
276 {2, 4}, {16, 6}, {32, 6}, {48, 6},
281 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
282 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
283 49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
287 {.offset = 2, .length = 22, },
289 #endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
290 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
293 48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
294 58, 59, 60, 61, 62, 63, 64, 65, 66, 67,
295 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
296 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
297 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
298 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
299 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
300 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
303 {.offset = 2, .length = 46, },
308 #if defined CONFIG_KEYSTONE_RBL_NAND
309 #if defined(CONFIG_SYS_NAND_PAGE_2K)
310 static struct nand_ecclayout nand_keystone_rbl_4bit_layout_oobfirst = {
313 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
314 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
315 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
316 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
319 {.offset = 2, .length = 4, },
320 {.offset = 16, .length = 6, },
321 {.offset = 32, .length = 6, },
322 {.offset = 48, .length = 6, },
324 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
327 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
328 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
329 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
330 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
331 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
332 86, 87, 88, 89, 90, 91, 92, 93, 94, 95,
333 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
334 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
337 {.offset = 2, .length = 4, },
338 {.offset = 16, .length = 6, },
339 {.offset = 32, .length = 6, },
340 {.offset = 48, .length = 6, },
341 {.offset = 64, .length = 6, },
342 {.offset = 80, .length = 6, },
343 {.offset = 96, .length = 6, },
344 {.offset = 112, .length = 6, },
349 #ifdef CONFIG_SYS_NAND_PAGE_2K
350 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 11
351 #elif defined(CONFIG_SYS_NAND_PAGE_4K)
352 #define CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE >> 12
356 * nand_davinci_write_page - write one page
357 * @mtd: MTD device structure
358 * @chip: NAND chip descriptor
359 * @buf: the data to write
360 * @oob_required: must write chip->oob_poi to OOB
361 * @page: page number to write
362 * @cached: cached programming
363 * @raw: use _raw version of write_page
365 static int nand_davinci_write_page(struct mtd_info *mtd, struct nand_chip *chip,
366 const uint8_t *buf, int oob_required,
367 int page, int cached, int raw)
371 struct nand_ecclayout *saved_ecc_layout;
373 /* save current ECC layout and assign Keystone RBL ECC layout */
374 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
375 saved_ecc_layout = chip->ecc.layout;
376 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
377 mtd->oobavail = chip->ecc.layout->oobavail;
380 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
383 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
385 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
392 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
393 status = chip->waitfunc(mtd, chip);
396 * See if operation failed and additional status checks are
399 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
400 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
402 if (status & NAND_STATUS_FAIL) {
407 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
408 /* Send command to read back the data */
409 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
411 if (chip->verify_buf(mtd, buf, mtd->writesize)) {
416 /* Make sure the next page prog is preceded by a status read */
417 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
420 /* restore ECC layout */
421 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
422 chip->ecc.layout = saved_ecc_layout;
423 mtd->oobavail = saved_ecc_layout->oobavail;
430 * nand_davinci_read_page_hwecc - hardware ECC based page read function
431 * @mtd: mtd info structure
432 * @chip: nand chip info structure
433 * @buf: buffer to store read data
434 * @oob_required: caller requires OOB data read to chip->oob_poi
435 * @page: page number to read
437 * Not for syndrome calculating ECC controllers which need a special oob layout.
439 static int nand_davinci_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
440 uint8_t *buf, int oob_required, int page)
442 int i, eccsize = chip->ecc.size;
443 int eccbytes = chip->ecc.bytes;
444 int eccsteps = chip->ecc.steps;
447 uint8_t *ecc_code = chip->buffers->ecccode;
448 uint8_t *ecc_calc = chip->buffers->ecccalc;
449 struct nand_ecclayout *saved_ecc_layout = chip->ecc.layout;
451 /* save current ECC layout and assign Keystone RBL ECC layout */
452 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
453 chip->ecc.layout = &nand_keystone_rbl_4bit_layout_oobfirst;
454 mtd->oobavail = chip->ecc.layout->oobavail;
457 eccpos = chip->ecc.layout->eccpos;
459 /* Read the OOB area first */
460 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
461 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
462 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
464 for (i = 0; i < chip->ecc.total; i++)
465 ecc_code[i] = chip->oob_poi[eccpos[i]];
467 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
470 chip->ecc.hwctl(mtd, NAND_ECC_READ);
471 chip->read_buf(mtd, p, eccsize);
472 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
474 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
476 mtd->ecc_stats.failed++;
478 mtd->ecc_stats.corrected += stat;
481 /* restore ECC layout */
482 if (page < CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE) {
483 chip->ecc.layout = saved_ecc_layout;
484 mtd->oobavail = saved_ecc_layout->oobavail;
489 #endif /* CONFIG_KEYSTONE_RBL_NAND */
491 static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
499 * Start a new ECC calculation for reading or writing 512 bytes
502 val = __raw_readl(&davinci_emif_regs->nandfcr);
503 val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
504 val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
505 val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
506 val |= DAVINCI_NANDFCR_4BIT_ECC_START;
507 __raw_writel(val, &davinci_emif_regs->nandfcr);
509 case NAND_ECC_READSYN:
510 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
517 static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
521 for (i = 0; i < 4; i++) {
522 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
529 static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
533 unsigned int hw_4ecc[4];
536 nand_davinci_4bit_readecc(mtd, hw_4ecc);
538 /*Convert 10 bit ecc value to 8 bit */
539 for (i = 0; i < 2; i++) {
540 unsigned int hw_ecc_low = hw_4ecc[i * 2];
541 unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
543 /* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
544 *ecc_code++ = hw_ecc_low & 0xFF;
547 * Take 2 bits as LSB bits from val1 (count1=0) or val5
548 * (count1=1) and 6 bits from val2 (count1=0) or
552 ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
555 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
556 * 4 bits from val3 (count1=0) or val6 (count1=1)
559 ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
562 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
563 * 2 bits from val4 (count1=0) or val7 (count1=1)
566 ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
568 /* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
569 *ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
575 static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
576 uint8_t *read_ecc, uint8_t *calc_ecc)
579 unsigned int hw_4ecc[4];
580 unsigned int iserror;
581 unsigned short *ecc16;
582 unsigned int numerrors, erroraddress, errorvalue;
586 * Check for an ECC where all bytes are 0xFF. If this is the case, we
587 * will assume we are looking at an erased page and we should ignore
590 for (i = 0; i < 10; i++) {
591 if (read_ecc[i] != 0xFF)
597 /* Convert 8 bit in to 10 bit */
598 ecc16 = (unsigned short *)&read_ecc[0];
601 * Write the parity values in the NAND Flash 4-bit ECC Load register.
602 * Write each parity value one at a time starting from 4bit_ecc_val8
606 /*Take 2 bits from 8th byte and 8 bits from 9th byte */
607 __raw_writel(((ecc16[4]) >> 6) & 0x3FF,
608 &davinci_emif_regs->nand4biteccload);
610 /* Take 4 bits from 7th byte and 6 bits from 8th byte */
611 __raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
612 &davinci_emif_regs->nand4biteccload);
614 /* Take 6 bits from 6th byte and 4 bits from 7th byte */
615 __raw_writel((ecc16[3] >> 2) & 0x3FF,
616 &davinci_emif_regs->nand4biteccload);
618 /* Take 8 bits from 5th byte and 2 bits from 6th byte */
619 __raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
620 &davinci_emif_regs->nand4biteccload);
622 /*Take 2 bits from 3rd byte and 8 bits from 4th byte */
623 __raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
624 &davinci_emif_regs->nand4biteccload);
626 /* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
627 __raw_writel(((ecc16[1]) >> 4) & 0x3FF,
628 &davinci_emif_regs->nand4biteccload);
630 /* Take 6 bits from 1st byte and 4 bits from 2nd byte */
631 __raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
632 &davinci_emif_regs->nand4biteccload);
634 /* Take 10 bits from 0th and 1st bytes */
635 __raw_writel((ecc16[0]) & 0x3FF,
636 &davinci_emif_regs->nand4biteccload);
639 * Perform a dummy read to the EMIF Revision Code and Status register.
640 * This is required to ensure time for syndrome calculation after
641 * writing the ECC values in previous step.
644 val = __raw_readl(&davinci_emif_regs->nandfsr);
647 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
648 * A syndrome value of 0 means no bit errors. If the syndrome is
649 * non-zero then go further otherwise return.
651 nand_davinci_4bit_readecc(mtd, hw_4ecc);
653 if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
657 * Clear any previous address calculation by doing a dummy read of an
658 * error address register.
660 val = __raw_readl(&davinci_emif_regs->nanderradd1);
663 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
666 __raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
667 &davinci_emif_regs->nandfcr);
670 * Wait for the corr_state field (bits 8 to 11) in the
671 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
672 * Otherwise ECC calculation has not even begun and the next loop might
673 * fail because of a false positive!
677 val = __raw_readl(&davinci_emif_regs->nandfsr);
680 } while ((i > 0) && !val);
683 * Wait for the corr_state field (bits 8 to 11) in the
684 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
688 val = __raw_readl(&davinci_emif_regs->nandfsr);
691 } while ((i > 0) && val);
693 iserror = __raw_readl(&davinci_emif_regs->nandfsr);
694 iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
695 iserror = iserror >> 8;
698 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
699 * corrected (five or more errors). The number of errors
700 * calculated (err_num field) differs from the number of errors
701 * searched. ECC_STATE_ERR_CORR_COMP_P (0x2) means error
702 * correction complete (errors on bit 8 or 9).
703 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
704 * complete (error exists).
707 if (iserror == ECC_STATE_NO_ERR) {
708 val = __raw_readl(&davinci_emif_regs->nanderrval1);
710 } else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
711 val = __raw_readl(&davinci_emif_regs->nanderrval1);
715 numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
718 /* Read the error address, error value and correct */
719 for (i = 0; i < numerrors; i++) {
722 ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
723 (16 * (i & 1))) & 0x3FF);
724 erroraddress = ((512 + 7) - erroraddress);
726 ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
727 (16 * (i & 1))) & 0xFF);
730 ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
731 (16 * (i & 1))) & 0x3FF);
732 erroraddress = ((512 + 7) - erroraddress);
734 ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
735 (16 * (i & 1))) & 0xFF);
737 /* xor the corrupt data with error value */
738 if (erroraddress < 512)
739 dat[erroraddress] ^= errorvalue;
744 #endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */
746 static int nand_davinci_dev_ready(struct mtd_info *mtd)
748 return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
751 static void nand_flash_init(void)
753 /* This is for DM6446 EVM and *very* similar. DO NOT GROW THIS!
754 * Instead, have your board_init() set EMIF timings, based on its
755 * knowledge of the clocks and what devices are hooked up ... and
756 * don't even do that unless no UBL handled it.
758 #ifdef CONFIG_SOC_DM644X
759 u_int32_t acfg1 = 0x3ffffffc;
761 /*------------------------------------------------------------------*
762 * NAND FLASH CHIP TIMEOUT @ 459 MHz *
764 * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
765 * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
767 *------------------------------------------------------------------*/
769 | (0 << 31) /* selectStrobe */
770 | (0 << 30) /* extWait */
771 | (1 << 26) /* writeSetup 10 ns */
772 | (3 << 20) /* writeStrobe 40 ns */
773 | (1 << 17) /* writeHold 10 ns */
774 | (1 << 13) /* readSetup 10 ns */
775 | (5 << 7) /* readStrobe 60 ns */
776 | (1 << 4) /* readHold 10 ns */
777 | (3 << 2) /* turnAround ?? ns */
778 | (0 << 0) /* asyncSize 8-bit bus */
781 __raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */
783 /* NAND flash on CS2 */
784 __raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
788 void davinci_nand_init(struct nand_chip *nand)
790 #if defined CONFIG_KEYSTONE_RBL_NAND
792 struct nand_ecclayout *layout;
794 layout = &nand_keystone_rbl_4bit_layout_oobfirst;
795 layout->oobavail = 0;
796 for (i = 0; layout->oobfree[i].length &&
797 i < ARRAY_SIZE(layout->oobfree); i++)
798 layout->oobavail += layout->oobfree[i].length;
800 nand->write_page = nand_davinci_write_page;
801 nand->ecc.read_page = nand_davinci_read_page_hwecc;
803 nand->chip_delay = 0;
804 #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
805 nand->bbt_options |= NAND_BBT_USE_FLASH;
807 #ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
808 nand->options |= NAND_NO_SUBPAGE_WRITE;
810 #ifdef CONFIG_SYS_NAND_HW_ECC
811 nand->ecc.mode = NAND_ECC_HW;
812 nand->ecc.size = 512;
814 nand->ecc.strength = 1;
815 nand->ecc.calculate = nand_davinci_calculate_ecc;
816 nand->ecc.correct = nand_davinci_correct_data;
817 nand->ecc.hwctl = nand_davinci_enable_hwecc;
819 nand->ecc.mode = NAND_ECC_SOFT;
820 #endif /* CONFIG_SYS_NAND_HW_ECC */
821 #ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
822 nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
823 nand->ecc.size = 512;
824 nand->ecc.bytes = 10;
825 nand->ecc.strength = 4;
826 nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
827 nand->ecc.correct = nand_davinci_4bit_correct_data;
828 nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
829 nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
831 /* Set address of hardware control function */
832 nand->cmd_ctrl = nand_davinci_hwcontrol;
834 nand->read_buf = nand_davinci_read_buf;
835 nand->write_buf = nand_davinci_write_buf;
837 nand->dev_ready = nand_davinci_dev_ready;
842 int board_nand_init(struct nand_chip *chip) __attribute__((weak));
844 int board_nand_init(struct nand_chip *chip)
846 davinci_nand_init(chip);