2 * Error Corrected Code Controller (ECC) - System peripherals regsters.
3 * Based on AT91SAM9260 datasheet revision B.
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef ATMEL_NAND_ECC_H
9 #define ATMEL_NAND_ECC_H
11 #define ATMEL_ECC_CR 0x00 /* Control register */
12 #define ATMEL_ECC_RST (1 << 0) /* Reset parity */
14 #define ATMEL_ECC_MR 0x04 /* Mode register */
15 #define ATMEL_ECC_PAGESIZE (3 << 0) /* Page Size */
16 #define ATMEL_ECC_PAGESIZE_528 (0)
17 #define ATMEL_ECC_PAGESIZE_1056 (1)
18 #define ATMEL_ECC_PAGESIZE_2112 (2)
19 #define ATMEL_ECC_PAGESIZE_4224 (3)
21 #define ATMEL_ECC_SR 0x08 /* Status register */
22 #define ATMEL_ECC_RECERR (1 << 0) /* Recoverable Error */
23 #define ATMEL_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
24 #define ATMEL_ECC_MULERR (1 << 2) /* Multiple Errors */
26 #define ATMEL_ECC_PR 0x0c /* Parity register */
27 #define ATMEL_ECC_BITADDR (0xf << 0) /* Bit Error Address */
28 #define ATMEL_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
30 #define ATMEL_ECC_NPR 0x10 /* NParity register */
31 #define ATMEL_ECC_NPARITY (0xffff << 0) /* NParity */
33 /* Register access macros for PMECC */
34 #define pmecc_readl(addr, reg) \
37 #define pmecc_writel(addr, reg, value) \
38 writel((value), &addr->reg)
40 /* PMECC Register Definitions */
41 #define PMECC_MAX_SECTOR_NUM 8
43 u32 cfg; /* 0x00 PMECC Configuration Register */
44 u32 sarea; /* 0x04 PMECC Spare Area Size Register */
45 u32 saddr; /* 0x08 PMECC Start Address Register */
46 u32 eaddr; /* 0x0C PMECC End Address Register */
47 u32 clk; /* 0x10 PMECC Clock Control Register */
48 u32 ctrl; /* 0x14 PMECC Control Register */
49 u32 sr; /* 0x18 PMECC Status Register */
50 u32 ier; /* 0x1C PMECC Interrupt Enable Register */
51 u32 idr; /* 0x20 PMECC Interrupt Disable Register */
52 u32 imr; /* 0x24 PMECC Interrupt Mask Register */
53 u32 isr; /* 0x28 PMECC Interrupt Status Register */
54 u32 reserved0[5]; /* 0x2C-0x3C Reserved */
56 /* 0x40 + sector_num * (0x40), Redundancy Registers */
58 u8 ecc[44]; /* PMECC Generated Redundancy Byte Per Sector */
60 } ecc_port[PMECC_MAX_SECTOR_NUM];
62 /* 0x240 + sector_num * (0x40) Remainder Registers */
66 } rem_port[PMECC_MAX_SECTOR_NUM];
67 u32 reserved3[16]; /* 0x440-0x47C Reserved */
70 /* For PMECC Configuration Register */
71 #define PMECC_CFG_BCH_ERR2 (0 << 0)
72 #define PMECC_CFG_BCH_ERR4 (1 << 0)
73 #define PMECC_CFG_BCH_ERR8 (2 << 0)
74 #define PMECC_CFG_BCH_ERR12 (3 << 0)
75 #define PMECC_CFG_BCH_ERR24 (4 << 0)
77 #define PMECC_CFG_SECTOR512 (0 << 4)
78 #define PMECC_CFG_SECTOR1024 (1 << 4)
80 #define PMECC_CFG_PAGE_1SECTOR (0 << 8)
81 #define PMECC_CFG_PAGE_2SECTORS (1 << 8)
82 #define PMECC_CFG_PAGE_4SECTORS (2 << 8)
83 #define PMECC_CFG_PAGE_8SECTORS (3 << 8)
85 #define PMECC_CFG_READ_OP (0 << 12)
86 #define PMECC_CFG_WRITE_OP (1 << 12)
88 #define PMECC_CFG_SPARE_ENABLE (1 << 16)
89 #define PMECC_CFG_SPARE_DISABLE (0 << 16)
91 #define PMECC_CFG_AUTO_ENABLE (1 << 20)
92 #define PMECC_CFG_AUTO_DISABLE (0 << 20)
94 /* For PMECC Clock Control Register */
95 #define PMECC_CLK_133MHZ (2 << 0)
97 /* For PMECC Control Register */
98 #define PMECC_CTRL_RST (1 << 0)
99 #define PMECC_CTRL_DATA (1 << 1)
100 #define PMECC_CTRL_USER (1 << 2)
101 #define PMECC_CTRL_ENABLE (1 << 4)
102 #define PMECC_CTRL_DISABLE (1 << 5)
104 /* For PMECC Status Register */
105 #define PMECC_SR_BUSY (1 << 0)
106 #define PMECC_SR_ENABLE (1 << 4)
108 /* PMERRLOC Register Definitions */
109 struct pmecc_errloc_regs {
110 u32 elcfg; /* 0x00 Error Location Configuration Register */
111 u32 elprim; /* 0x04 Error Location Primitive Register */
112 u32 elen; /* 0x08 Error Location Enable Register */
113 u32 eldis; /* 0x0C Error Location Disable Register */
114 u32 elsr; /* 0x10 Error Location Status Register */
115 u32 elier; /* 0x14 Error Location Interrupt Enable Register */
116 u32 elidr; /* 0x08 Error Location Interrupt Disable Register */
117 u32 elimr; /* 0x0C Error Location Interrupt Mask Register */
118 u32 elisr; /* 0x20 Error Location Interrupt Status Register */
119 u32 reserved0; /* 0x24 Reserved */
120 u32 sigma[25]; /* 0x28-0x88 Error Location Sigma Registers */
121 u32 el[24]; /* 0x8C-0xE8 Error Location Registers */
122 u32 reserved1[5]; /* 0xEC-0xFC Reserved */
125 /* For Error Location Configuration Register */
126 #define PMERRLOC_ELCFG_SECTOR_512 (0 << 0)
127 #define PMERRLOC_ELCFG_SECTOR_1024 (1 << 0)
128 #define PMERRLOC_ELCFG_NUM_ERRORS(n) ((n) << 16)
130 /* For Error Location Disable Register */
131 #define PMERRLOC_DISABLE (1 << 0)
133 /* For Error Location Interrupt Status Register */
134 #define PMERRLOC_ERR_NUM_MASK (0x1f << 8)
135 #define PMERRLOC_CALC_DONE (1 << 0)
137 /* Galois field dimension */
138 #define PMECC_GF_DIMENSION_13 13
139 #define PMECC_GF_DIMENSION_14 14
141 #define PMECC_INDEX_TABLE_SIZE_512 0x2000
142 #define PMECC_INDEX_TABLE_SIZE_1024 0x4000
144 #define PMECC_MAX_TIMEOUT_US (100 * 1000)