2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 * Add Programmable Multibit ECC support for various AT91 SoC
9 * (C) Copyright 2012 ATMEL, Hong Xu
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/at91_pio.h>
22 #ifdef CONFIG_ATMEL_NAND_HWECC
24 /* Register access macros */
25 #define ecc_readl(add, reg) \
26 readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
27 #define ecc_writel(add, reg, value) \
28 writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
30 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
32 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
34 struct atmel_nand_host {
35 struct pmecc_regs __iomem *pmecc;
36 struct pmecc_errloc_regs __iomem *pmerrloc;
37 void __iomem *pmecc_rom_base;
40 u16 pmecc_sector_size;
41 u32 pmecc_index_table_offset;
43 int pmecc_bytes_per_sector;
44 int pmecc_sector_number;
45 int pmecc_degree; /* Degree of remainders */
46 int pmecc_cw_len; /* Length of codeword */
48 /* lookup table for alpha_to and index_of */
49 void __iomem *pmecc_alpha_to;
50 void __iomem *pmecc_index_of;
52 /* data for pmecc computation */
53 int16_t pmecc_smu[(CONFIG_PMECC_CAP + 2) * (2 * CONFIG_PMECC_CAP + 1)];
54 int16_t pmecc_partial_syn[2 * CONFIG_PMECC_CAP + 1];
55 int16_t pmecc_si[2 * CONFIG_PMECC_CAP + 1];
56 int16_t pmecc_lmu[CONFIG_PMECC_CAP + 1]; /* polynomal order */
57 int pmecc_mu[CONFIG_PMECC_CAP + 1];
58 int pmecc_dmu[CONFIG_PMECC_CAP + 1];
59 int pmecc_delta[CONFIG_PMECC_CAP + 1];
62 static struct atmel_nand_host pmecc_host;
63 static struct nand_ecclayout atmel_pmecc_oobinfo;
66 * Return number of ecc bytes per sector according to sector size and
67 * correction capability
69 * Following table shows what at91 PMECC supported:
70 * Correction Capability Sector_512_bytes Sector_1024_bytes
71 * ===================== ================ =================
72 * 2-bits 4-bytes 4-bytes
73 * 4-bits 7-bytes 7-bytes
74 * 8-bits 13-bytes 14-bytes
75 * 12-bits 20-bytes 21-bytes
76 * 24-bits 39-bytes 42-bytes
78 static int pmecc_get_ecc_bytes(int cap, int sector_size)
80 int m = 12 + sector_size / 512;
81 return (m * cap + 7) / 8;
84 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
85 int oobsize, int ecc_len)
89 layout->eccbytes = ecc_len;
91 /* ECC will occupy the last ecc_len bytes continuously */
92 for (i = 0; i < ecc_len; i++)
93 layout->eccpos[i] = oobsize - ecc_len + i;
95 layout->oobfree[0].offset = 2;
96 layout->oobfree[0].length =
97 oobsize - ecc_len - layout->oobfree[0].offset;
100 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
104 table_size = host->pmecc_sector_size == 512 ?
105 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
107 /* the ALPHA lookup table is right behind the INDEX lookup table. */
108 return host->pmecc_rom_base + host->pmecc_index_table_offset +
109 table_size * sizeof(int16_t);
112 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
114 struct nand_chip *nand_chip = mtd->priv;
115 struct atmel_nand_host *host = nand_chip->priv;
119 /* Fill odd syndromes */
120 for (i = 0; i < host->pmecc_corr_cap; i++) {
121 value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
125 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
129 static void pmecc_substitute(struct mtd_info *mtd)
131 struct nand_chip *nand_chip = mtd->priv;
132 struct atmel_nand_host *host = nand_chip->priv;
133 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
134 int16_t __iomem *index_of = host->pmecc_index_of;
135 int16_t *partial_syn = host->pmecc_partial_syn;
136 const int cap = host->pmecc_corr_cap;
140 /* si[] is a table that holds the current syndrome value,
141 * an element of that table belongs to the field
145 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
147 /* Computation 2t syndromes based on S(x) */
149 for (i = 1; i < 2 * cap; i += 2) {
150 for (j = 0; j < host->pmecc_degree; j++) {
151 if (partial_syn[i] & (0x1 << j))
152 si[i] = readw(alpha_to + i * j) ^ si[i];
155 /* Even syndrome = (Odd syndrome) ** 2 */
156 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
162 tmp = readw(index_of + si[j]);
163 tmp = (tmp * 2) % host->pmecc_cw_len;
164 si[i] = readw(alpha_to + tmp);
170 * This function defines a Berlekamp iterative procedure for
171 * finding the value of the error location polynomial.
172 * The input is si[], initialize by pmecc_substitute().
173 * The output is smu[][].
175 * This function is written according to chip datasheet Chapter:
176 * Find the Error Location Polynomial Sigma(x) of Section:
177 * Programmable Multibit ECC Control (PMECC).
179 static void pmecc_get_sigma(struct mtd_info *mtd)
181 struct nand_chip *nand_chip = mtd->priv;
182 struct atmel_nand_host *host = nand_chip->priv;
184 int16_t *lmu = host->pmecc_lmu;
185 int16_t *si = host->pmecc_si;
186 int *mu = host->pmecc_mu;
187 int *dmu = host->pmecc_dmu; /* Discrepancy */
188 int *delta = host->pmecc_delta; /* Delta order */
189 int cw_len = host->pmecc_cw_len;
190 const int16_t cap = host->pmecc_corr_cap;
191 const int num = 2 * cap + 1;
192 int16_t __iomem *index_of = host->pmecc_index_of;
193 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
195 uint32_t dmu_0_count, tmp;
196 int16_t *smu = host->pmecc_smu;
198 /* index of largest delta */
203 /* Init the Sigma(x) */
204 memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
215 /* discrepancy set to 1 */
217 /* polynom order set to 0 */
219 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
226 /* Sigma(x) set to 1 */
229 /* discrepancy set to S1 */
232 /* polynom order set to 0 */
235 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
238 for (i = 1; i <= cap; i++) {
240 /* Begin Computing Sigma (Mu+1) and L(mu) */
241 /* check if discrepancy is set to 0 */
245 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
246 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
251 if (dmu_0_count == tmp) {
252 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
253 smu[(cap + 1) * num + j] =
256 lmu[cap + 1] = lmu[i];
261 for (j = 0; j <= lmu[i] >> 1; j++)
262 smu[(i + 1) * num + j] = smu[i * num + j];
264 /* copy previous polynom order to the next */
269 /* find largest delta with dmu != 0 */
270 for (j = 0; j < i; j++) {
271 if ((dmu[j]) && (delta[j] > largest)) {
277 /* compute difference */
278 diff = (mu[i] - mu[ro]);
280 /* Compute degree of the new smu polynomial */
281 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
284 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
286 /* Init smu[i+1] with 0 */
287 for (k = 0; k < num; k++)
288 smu[(i + 1) * num + k] = 0;
290 /* Compute smu[i+1] */
291 for (k = 0; k <= lmu[ro] >> 1; k++) {
294 if (!(smu[ro * num + k] && dmu[i]))
296 a = readw(index_of + dmu[i]);
297 b = readw(index_of + dmu[ro]);
298 c = readw(index_of + smu[ro * num + k]);
299 tmp = a + (cw_len - b) + c;
300 a = readw(alpha_to + tmp % cw_len);
301 smu[(i + 1) * num + (k + diff)] = a;
304 for (k = 0; k <= lmu[i] >> 1; k++)
305 smu[(i + 1) * num + k] ^= smu[i * num + k];
308 /* End Computing Sigma (Mu+1) and L(mu) */
309 /* In either case compute delta */
310 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
312 /* Do not compute discrepancy for the last iteration */
316 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
319 dmu[i + 1] = si[tmp + 3];
320 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
323 smu[(i + 1) * num + k]);
324 b = si[2 * (i - 1) + 3 - k];
325 c = readw(index_of + b);
328 dmu[i + 1] = readw(alpha_to + tmp) ^
335 static int pmecc_err_location(struct mtd_info *mtd)
337 struct nand_chip *nand_chip = mtd->priv;
338 struct atmel_nand_host *host = nand_chip->priv;
339 const int cap = host->pmecc_corr_cap;
340 const int num = 2 * cap + 1;
341 int sector_size = host->pmecc_sector_size;
342 int err_nbr = 0; /* number of error */
343 int roots_nbr; /* number of roots */
346 int16_t *smu = host->pmecc_smu;
347 int timeout = PMECC_MAX_TIMEOUT_US;
349 writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
351 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
352 writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
356 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
357 if (sector_size == 1024)
358 val |= PMERRLOC_ELCFG_SECTOR_1024;
360 writel(val, &host->pmerrloc->elcfg);
361 writel(sector_size * 8 + host->pmecc_degree * cap,
362 &host->pmerrloc->elen);
365 if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
372 printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n");
376 roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
378 /* Number of roots == degree of smu hence <= cap */
379 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
382 /* Number of roots does not match the degree of smu
383 * unable to correct error */
387 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
388 int sector_num, int extra_bytes, int err_nbr)
390 struct nand_chip *nand_chip = mtd->priv;
391 struct atmel_nand_host *host = nand_chip->priv;
393 int byte_pos, bit_pos, sector_size, pos;
397 sector_size = host->pmecc_sector_size;
400 tmp = readl(&host->pmerrloc->el[i]) - 1;
404 if (byte_pos >= (sector_size + extra_bytes))
405 BUG(); /* should never happen */
407 if (byte_pos < sector_size) {
408 err_byte = *(buf + byte_pos);
409 *(buf + byte_pos) ^= (1 << bit_pos);
411 pos = sector_num * host->pmecc_sector_size + byte_pos;
412 printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
413 pos, bit_pos, err_byte, *(buf + byte_pos));
415 /* Bit flip in OOB area */
416 tmp = sector_num * host->pmecc_bytes_per_sector
417 + (byte_pos - sector_size);
419 ecc[tmp] ^= (1 << bit_pos);
421 pos = tmp + nand_chip->ecc.layout->eccpos[0];
422 printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
423 pos, bit_pos, err_byte, ecc[tmp]);
433 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
436 struct nand_chip *nand_chip = mtd->priv;
437 struct atmel_nand_host *host = nand_chip->priv;
438 int i, err_nbr, eccbytes;
441 eccbytes = nand_chip->ecc.bytes;
442 for (i = 0; i < eccbytes; i++)
445 /* Erased page, return OK */
449 for (i = 0; i < host->pmecc_sector_number; i++) {
451 if (pmecc_stat & 0x1) {
452 buf_pos = buf + i * host->pmecc_sector_size;
454 pmecc_gen_syndrome(mtd, i);
455 pmecc_substitute(mtd);
456 pmecc_get_sigma(mtd);
458 err_nbr = pmecc_err_location(mtd);
460 printk(KERN_ERR "PMECC: Too many errors\n");
461 mtd->ecc_stats.failed++;
464 pmecc_correct_data(mtd, buf_pos, ecc, i,
465 host->pmecc_bytes_per_sector, err_nbr);
466 mtd->ecc_stats.corrected += err_nbr;
475 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
476 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
478 struct atmel_nand_host *host = chip->priv;
479 int eccsize = chip->ecc.size;
480 uint8_t *oob = chip->oob_poi;
481 uint32_t *eccpos = chip->ecc.layout->eccpos;
483 int timeout = PMECC_MAX_TIMEOUT_US;
485 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
486 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
487 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
488 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
490 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
491 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
493 chip->read_buf(mtd, buf, eccsize);
494 chip->read_buf(mtd, oob, mtd->oobsize);
497 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
504 printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n");
508 stat = pmecc_readl(host->pmecc, isr);
510 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
516 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
517 struct nand_chip *chip, const uint8_t *buf,
520 struct atmel_nand_host *host = chip->priv;
521 uint32_t *eccpos = chip->ecc.layout->eccpos;
523 int timeout = PMECC_MAX_TIMEOUT_US;
525 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
526 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
528 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
529 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
531 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
532 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
534 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
537 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
544 printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
548 for (i = 0; i < host->pmecc_sector_number; i++) {
549 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
552 pos = i * host->pmecc_bytes_per_sector + j;
553 chip->oob_poi[eccpos[pos]] =
554 readb(&host->pmecc->ecc_port[i].ecc[j]);
557 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
562 static void atmel_pmecc_core_init(struct mtd_info *mtd)
564 struct nand_chip *nand_chip = mtd->priv;
565 struct atmel_nand_host *host = nand_chip->priv;
567 struct nand_ecclayout *ecc_layout;
569 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
570 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
572 switch (host->pmecc_corr_cap) {
574 val = PMECC_CFG_BCH_ERR2;
577 val = PMECC_CFG_BCH_ERR4;
580 val = PMECC_CFG_BCH_ERR8;
583 val = PMECC_CFG_BCH_ERR12;
586 val = PMECC_CFG_BCH_ERR24;
590 if (host->pmecc_sector_size == 512)
591 val |= PMECC_CFG_SECTOR512;
592 else if (host->pmecc_sector_size == 1024)
593 val |= PMECC_CFG_SECTOR1024;
595 switch (host->pmecc_sector_number) {
597 val |= PMECC_CFG_PAGE_1SECTOR;
600 val |= PMECC_CFG_PAGE_2SECTORS;
603 val |= PMECC_CFG_PAGE_4SECTORS;
606 val |= PMECC_CFG_PAGE_8SECTORS;
610 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
611 | PMECC_CFG_AUTO_DISABLE);
612 pmecc_writel(host->pmecc, cfg, val);
614 ecc_layout = nand_chip->ecc.layout;
615 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
616 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
617 pmecc_writel(host->pmecc, eaddr,
618 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
619 /* See datasheet about PMECC Clock Control Register */
620 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
621 pmecc_writel(host->pmecc, idr, 0xff);
622 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
625 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
626 struct mtd_info *mtd)
628 struct atmel_nand_host *host;
629 int cap, sector_size;
631 host = nand->priv = &pmecc_host;
633 nand->ecc.mode = NAND_ECC_HW;
634 nand->ecc.calculate = NULL;
635 nand->ecc.correct = NULL;
636 nand->ecc.hwctl = NULL;
638 cap = host->pmecc_corr_cap = CONFIG_PMECC_CAP;
639 sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
640 host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET;
642 MTDDEBUG(MTD_DEBUG_LEVEL1,
643 "Initialize PMECC params, cap: %d, sector: %d\n",
646 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
647 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
649 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
651 /* ECC is calculated for the whole page (1 step) */
652 nand->ecc.size = mtd->writesize;
654 /* set ECC page size and oob layout */
655 switch (mtd->writesize) {
658 host->pmecc_degree = PMECC_GF_DIMENSION_13;
659 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
660 host->pmecc_sector_number = mtd->writesize / sector_size;
661 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
663 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
664 host->pmecc_index_of = host->pmecc_rom_base +
665 host->pmecc_index_table_offset;
668 nand->ecc.bytes = host->pmecc_bytes_per_sector *
669 host->pmecc_sector_number;
670 if (nand->ecc.bytes > mtd->oobsize - 2) {
671 printk(KERN_ERR "No room for ECC bytes\n");
674 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
677 nand->ecc.layout = &atmel_pmecc_oobinfo;
682 printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n");
684 /* page size not handled by HW ECC */
685 /* switching back to soft ECC */
686 nand->ecc.mode = NAND_ECC_SOFT;
687 nand->ecc.read_page = NULL;
688 nand->ecc.postpad = 0;
689 nand->ecc.prepad = 0;
694 nand->ecc.read_page = atmel_nand_pmecc_read_page;
695 nand->ecc.write_page = atmel_nand_pmecc_write_page;
696 nand->ecc.strength = cap;
698 atmel_pmecc_core_init(mtd);
705 /* oob layout for large page size
706 * bad block info is on bytes 0 and 1
707 * the bytes have to be consecutives to avoid
708 * several NAND_CMD_RNDOUT during read
710 static struct nand_ecclayout atmel_oobinfo_large = {
712 .eccpos = {60, 61, 62, 63},
718 /* oob layout for small page size
719 * bad block info is on bytes 4 and 5
720 * the bytes have to be consecutives to avoid
721 * several NAND_CMD_RNDOUT during read
723 static struct nand_ecclayout atmel_oobinfo_small = {
725 .eccpos = {0, 1, 2, 3},
734 * function called after a write
736 * mtd: MTD block structure
737 * dat: raw data (unused)
738 * ecc_code: buffer for ECC
740 static int atmel_nand_calculate(struct mtd_info *mtd,
741 const u_char *dat, unsigned char *ecc_code)
743 unsigned int ecc_value;
745 /* get the first 2 ECC bytes */
746 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
748 ecc_code[0] = ecc_value & 0xFF;
749 ecc_code[1] = (ecc_value >> 8) & 0xFF;
751 /* get the last 2 ECC bytes */
752 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
754 ecc_code[2] = ecc_value & 0xFF;
755 ecc_code[3] = (ecc_value >> 8) & 0xFF;
761 * HW ECC read page function
763 * mtd: mtd info structure
764 * chip: nand chip info structure
765 * buf: buffer to store read data
766 * oob_required: caller expects OOB data read to chip->oob_poi
768 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
769 uint8_t *buf, int oob_required, int page)
771 int eccsize = chip->ecc.size;
772 int eccbytes = chip->ecc.bytes;
773 uint32_t *eccpos = chip->ecc.layout->eccpos;
775 uint8_t *oob = chip->oob_poi;
780 chip->read_buf(mtd, p, eccsize);
782 /* move to ECC position if needed */
783 if (eccpos[0] != 0) {
784 /* This only works on large pages
785 * because the ECC controller waits for
786 * NAND_CMD_RNDOUTSTART after the
788 * anyway, for small pages, the eccpos[0] == 0
790 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
791 mtd->writesize + eccpos[0], -1);
794 /* the ECC controller needs to read the ECC just after the data */
795 ecc_pos = oob + eccpos[0];
796 chip->read_buf(mtd, ecc_pos, eccbytes);
798 /* check if there's an error */
799 stat = chip->ecc.correct(mtd, p, oob, NULL);
802 mtd->ecc_stats.failed++;
804 mtd->ecc_stats.corrected += stat;
806 /* get back to oob start (end of page) */
807 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
810 chip->read_buf(mtd, oob, mtd->oobsize);
818 * function called after a read
820 * mtd: MTD block structure
821 * dat: raw data read from the chip
822 * read_ecc: ECC from the chip (unused)
825 * Detect and correct a 1 bit error for a page
827 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
828 u_char *read_ecc, u_char *isnull)
830 struct nand_chip *nand_chip = mtd->priv;
831 unsigned int ecc_status;
832 unsigned int ecc_word, ecc_bit;
834 /* get the status from the Status Register */
835 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
837 /* if there's no error */
838 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
841 /* get error bit offset (4 bits) */
842 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
843 /* get word address (12 bits) */
844 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
847 /* if there are multiple errors */
848 if (ecc_status & ATMEL_ECC_MULERR) {
849 /* check if it is a freshly erased block
850 * (filled with 0xff) */
851 if ((ecc_bit == ATMEL_ECC_BITADDR)
852 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
853 /* the block has just been erased, return OK */
856 /* it doesn't seems to be a freshly
858 * We can't correct so many errors */
859 printk(KERN_WARNING "atmel_nand : multiple errors detected."
860 " Unable to correct.\n");
864 /* if there's a single bit error : we can correct it */
865 if (ecc_status & ATMEL_ECC_ECCERR) {
866 /* there's nothing much to do here.
867 * the bit error is on the ECC itself.
869 printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
870 " Nothing to correct\n");
874 printk(KERN_WARNING "atmel_nand : one bit error on data."
875 " (word offset in the page :"
876 " 0x%x bit offset : 0x%x)\n",
878 /* correct the error */
879 if (nand_chip->options & NAND_BUSWIDTH_16) {
881 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
884 dat[ecc_word] ^= (1 << ecc_bit);
886 printk(KERN_WARNING "atmel_nand : error corrected\n");
891 * Enable HW ECC : unused on most chips
893 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
897 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
899 nand->ecc.mode = NAND_ECC_HW;
900 nand->ecc.calculate = atmel_nand_calculate;
901 nand->ecc.correct = atmel_nand_correct;
902 nand->ecc.hwctl = atmel_nand_hwctl;
903 nand->ecc.read_page = atmel_nand_read_page;
906 if (nand->ecc.mode == NAND_ECC_HW) {
907 /* ECC is calculated for the whole page (1 step) */
908 nand->ecc.size = mtd->writesize;
910 /* set ECC page size and oob layout */
911 switch (mtd->writesize) {
913 nand->ecc.layout = &atmel_oobinfo_small;
914 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
915 ATMEL_ECC_PAGESIZE_528);
918 nand->ecc.layout = &atmel_oobinfo_large;
919 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
920 ATMEL_ECC_PAGESIZE_1056);
923 nand->ecc.layout = &atmel_oobinfo_large;
924 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
925 ATMEL_ECC_PAGESIZE_2112);
928 nand->ecc.layout = &atmel_oobinfo_large;
929 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
930 ATMEL_ECC_PAGESIZE_4224);
933 /* page size not handled by HW ECC */
934 /* switching back to soft ECC */
935 nand->ecc.mode = NAND_ECC_SOFT;
936 nand->ecc.calculate = NULL;
937 nand->ecc.correct = NULL;
938 nand->ecc.hwctl = NULL;
939 nand->ecc.read_page = NULL;
940 nand->ecc.postpad = 0;
941 nand->ecc.prepad = 0;
950 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
952 #endif /* CONFIG_ATMEL_NAND_HWECC */
954 static void at91_nand_hwcontrol(struct mtd_info *mtd,
955 int cmd, unsigned int ctrl)
957 struct nand_chip *this = mtd->priv;
959 if (ctrl & NAND_CTRL_CHANGE) {
960 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
961 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
962 | CONFIG_SYS_NAND_MASK_CLE);
965 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
967 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
969 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
970 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
973 this->IO_ADDR_W = (void *) IO_ADDR_W;
976 if (cmd != NAND_CMD_NONE)
977 writeb(cmd, this->IO_ADDR_W);
980 #ifdef CONFIG_SYS_NAND_READY_PIN
981 static int at91_nand_ready(struct mtd_info *mtd)
983 return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
987 #ifndef CONFIG_SYS_NAND_BASE_LIST
988 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
990 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
991 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
993 int atmel_nand_chip_init(int devnum, ulong base_addr)
996 struct mtd_info *mtd = &nand_info[devnum];
997 struct nand_chip *nand = &nand_chip[devnum];
1000 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
1002 nand->ecc.mode = NAND_ECC_SOFT;
1003 #ifdef CONFIG_SYS_NAND_DBW_16
1004 nand->options = NAND_BUSWIDTH_16;
1006 nand->cmd_ctrl = at91_nand_hwcontrol;
1007 #ifdef CONFIG_SYS_NAND_READY_PIN
1008 nand->dev_ready = at91_nand_ready;
1010 nand->chip_delay = 20;
1012 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1016 #ifdef CONFIG_ATMEL_NAND_HWECC
1017 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1018 ret = atmel_pmecc_nand_init_params(nand, mtd);
1020 ret = atmel_hwecc_nand_init_param(nand, mtd);
1026 ret = nand_scan_tail(mtd);
1028 nand_register(devnum);
1033 void board_nand_init(void)
1036 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1037 if (atmel_nand_chip_init(i, base_addr[i]))
1038 printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",