2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 * Add Programmable Multibit ECC support for various AT91 SoC
9 * (C) Copyright 2012 ATMEL, Hong Xu
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/gpio.h>
22 #ifdef CONFIG_ATMEL_NAND_HWECC
24 /* Register access macros */
25 #define ecc_readl(add, reg) \
26 readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
27 #define ecc_writel(add, reg, value) \
28 writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
30 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
32 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
34 #ifdef CONFIG_SPL_BUILD
35 #undef CONFIG_SYS_NAND_ONFI_DETECTION
38 struct atmel_nand_host {
39 struct pmecc_regs __iomem *pmecc;
40 struct pmecc_errloc_regs __iomem *pmerrloc;
41 void __iomem *pmecc_rom_base;
44 u16 pmecc_sector_size;
45 u32 pmecc_index_table_offset;
47 int pmecc_bytes_per_sector;
48 int pmecc_sector_number;
49 int pmecc_degree; /* Degree of remainders */
50 int pmecc_cw_len; /* Length of codeword */
52 /* lookup table for alpha_to and index_of */
53 void __iomem *pmecc_alpha_to;
54 void __iomem *pmecc_index_of;
56 /* data for pmecc computation */
58 int16_t *pmecc_partial_syn;
60 int16_t *pmecc_lmu; /* polynomal order */
66 static struct atmel_nand_host pmecc_host;
67 static struct nand_ecclayout atmel_pmecc_oobinfo;
70 * Return number of ecc bytes per sector according to sector size and
71 * correction capability
73 * Following table shows what at91 PMECC supported:
74 * Correction Capability Sector_512_bytes Sector_1024_bytes
75 * ===================== ================ =================
76 * 2-bits 4-bytes 4-bytes
77 * 4-bits 7-bytes 7-bytes
78 * 8-bits 13-bytes 14-bytes
79 * 12-bits 20-bytes 21-bytes
80 * 24-bits 39-bytes 42-bytes
82 static int pmecc_get_ecc_bytes(int cap, int sector_size)
84 int m = 12 + sector_size / 512;
85 return (m * cap + 7) / 8;
88 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
89 int oobsize, int ecc_len)
93 layout->eccbytes = ecc_len;
95 /* ECC will occupy the last ecc_len bytes continuously */
96 for (i = 0; i < ecc_len; i++)
97 layout->eccpos[i] = oobsize - ecc_len + i;
99 layout->oobfree[0].offset = 2;
100 layout->oobfree[0].length =
101 oobsize - ecc_len - layout->oobfree[0].offset;
104 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
108 table_size = host->pmecc_sector_size == 512 ?
109 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
111 /* the ALPHA lookup table is right behind the INDEX lookup table. */
112 return host->pmecc_rom_base + host->pmecc_index_table_offset +
113 table_size * sizeof(int16_t);
116 static void pmecc_data_free(struct atmel_nand_host *host)
118 free(host->pmecc_partial_syn);
119 free(host->pmecc_si);
120 free(host->pmecc_lmu);
121 free(host->pmecc_smu);
122 free(host->pmecc_mu);
123 free(host->pmecc_dmu);
124 free(host->pmecc_delta);
127 static int pmecc_data_alloc(struct atmel_nand_host *host)
129 const int cap = host->pmecc_corr_cap;
132 size = (2 * cap + 1) * sizeof(int16_t);
133 host->pmecc_partial_syn = malloc(size);
134 host->pmecc_si = malloc(size);
135 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
136 host->pmecc_smu = malloc((cap + 2) * size);
138 size = (cap + 1) * sizeof(int);
139 host->pmecc_mu = malloc(size);
140 host->pmecc_dmu = malloc(size);
141 host->pmecc_delta = malloc(size);
143 if (host->pmecc_partial_syn &&
153 pmecc_data_free(host);
158 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
160 struct nand_chip *nand_chip = mtd->priv;
161 struct atmel_nand_host *host = nand_chip->priv;
165 /* Fill odd syndromes */
166 for (i = 0; i < host->pmecc_corr_cap; i++) {
167 value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
171 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
175 static void pmecc_substitute(struct mtd_info *mtd)
177 struct nand_chip *nand_chip = mtd->priv;
178 struct atmel_nand_host *host = nand_chip->priv;
179 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
180 int16_t __iomem *index_of = host->pmecc_index_of;
181 int16_t *partial_syn = host->pmecc_partial_syn;
182 const int cap = host->pmecc_corr_cap;
186 /* si[] is a table that holds the current syndrome value,
187 * an element of that table belongs to the field
191 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
193 /* Computation 2t syndromes based on S(x) */
195 for (i = 1; i < 2 * cap; i += 2) {
196 for (j = 0; j < host->pmecc_degree; j++) {
197 if (partial_syn[i] & (0x1 << j))
198 si[i] = readw(alpha_to + i * j) ^ si[i];
201 /* Even syndrome = (Odd syndrome) ** 2 */
202 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
208 tmp = readw(index_of + si[j]);
209 tmp = (tmp * 2) % host->pmecc_cw_len;
210 si[i] = readw(alpha_to + tmp);
216 * This function defines a Berlekamp iterative procedure for
217 * finding the value of the error location polynomial.
218 * The input is si[], initialize by pmecc_substitute().
219 * The output is smu[][].
221 * This function is written according to chip datasheet Chapter:
222 * Find the Error Location Polynomial Sigma(x) of Section:
223 * Programmable Multibit ECC Control (PMECC).
225 static void pmecc_get_sigma(struct mtd_info *mtd)
227 struct nand_chip *nand_chip = mtd->priv;
228 struct atmel_nand_host *host = nand_chip->priv;
230 int16_t *lmu = host->pmecc_lmu;
231 int16_t *si = host->pmecc_si;
232 int *mu = host->pmecc_mu;
233 int *dmu = host->pmecc_dmu; /* Discrepancy */
234 int *delta = host->pmecc_delta; /* Delta order */
235 int cw_len = host->pmecc_cw_len;
236 const int16_t cap = host->pmecc_corr_cap;
237 const int num = 2 * cap + 1;
238 int16_t __iomem *index_of = host->pmecc_index_of;
239 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
241 uint32_t dmu_0_count, tmp;
242 int16_t *smu = host->pmecc_smu;
244 /* index of largest delta */
249 /* Init the Sigma(x) */
250 memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
261 /* discrepancy set to 1 */
263 /* polynom order set to 0 */
265 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
272 /* Sigma(x) set to 1 */
275 /* discrepancy set to S1 */
278 /* polynom order set to 0 */
281 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
284 for (i = 1; i <= cap; i++) {
286 /* Begin Computing Sigma (Mu+1) and L(mu) */
287 /* check if discrepancy is set to 0 */
291 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
292 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
297 if (dmu_0_count == tmp) {
298 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
299 smu[(cap + 1) * num + j] =
302 lmu[cap + 1] = lmu[i];
307 for (j = 0; j <= lmu[i] >> 1; j++)
308 smu[(i + 1) * num + j] = smu[i * num + j];
310 /* copy previous polynom order to the next */
315 /* find largest delta with dmu != 0 */
316 for (j = 0; j < i; j++) {
317 if ((dmu[j]) && (delta[j] > largest)) {
323 /* compute difference */
324 diff = (mu[i] - mu[ro]);
326 /* Compute degree of the new smu polynomial */
327 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
330 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
332 /* Init smu[i+1] with 0 */
333 for (k = 0; k < num; k++)
334 smu[(i + 1) * num + k] = 0;
336 /* Compute smu[i+1] */
337 for (k = 0; k <= lmu[ro] >> 1; k++) {
340 if (!(smu[ro * num + k] && dmu[i]))
342 a = readw(index_of + dmu[i]);
343 b = readw(index_of + dmu[ro]);
344 c = readw(index_of + smu[ro * num + k]);
345 tmp = a + (cw_len - b) + c;
346 a = readw(alpha_to + tmp % cw_len);
347 smu[(i + 1) * num + (k + diff)] = a;
350 for (k = 0; k <= lmu[i] >> 1; k++)
351 smu[(i + 1) * num + k] ^= smu[i * num + k];
354 /* End Computing Sigma (Mu+1) and L(mu) */
355 /* In either case compute delta */
356 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
358 /* Do not compute discrepancy for the last iteration */
362 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
365 dmu[i + 1] = si[tmp + 3];
366 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
369 smu[(i + 1) * num + k]);
370 b = si[2 * (i - 1) + 3 - k];
371 c = readw(index_of + b);
374 dmu[i + 1] = readw(alpha_to + tmp) ^
381 static int pmecc_err_location(struct mtd_info *mtd)
383 struct nand_chip *nand_chip = mtd->priv;
384 struct atmel_nand_host *host = nand_chip->priv;
385 const int cap = host->pmecc_corr_cap;
386 const int num = 2 * cap + 1;
387 int sector_size = host->pmecc_sector_size;
388 int err_nbr = 0; /* number of error */
389 int roots_nbr; /* number of roots */
392 int16_t *smu = host->pmecc_smu;
393 int timeout = PMECC_MAX_TIMEOUT_US;
395 writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
397 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
398 writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
402 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
403 if (sector_size == 1024)
404 val |= PMERRLOC_ELCFG_SECTOR_1024;
406 writel(val, &host->pmerrloc->elcfg);
407 writel(sector_size * 8 + host->pmecc_degree * cap,
408 &host->pmerrloc->elen);
411 if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
418 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
422 roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
424 /* Number of roots == degree of smu hence <= cap */
425 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
428 /* Number of roots does not match the degree of smu
429 * unable to correct error */
433 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
434 int sector_num, int extra_bytes, int err_nbr)
436 struct nand_chip *nand_chip = mtd->priv;
437 struct atmel_nand_host *host = nand_chip->priv;
439 int byte_pos, bit_pos, sector_size, pos;
443 sector_size = host->pmecc_sector_size;
446 tmp = readl(&host->pmerrloc->el[i]) - 1;
450 if (byte_pos >= (sector_size + extra_bytes))
451 BUG(); /* should never happen */
453 if (byte_pos < sector_size) {
454 err_byte = *(buf + byte_pos);
455 *(buf + byte_pos) ^= (1 << bit_pos);
457 pos = sector_num * host->pmecc_sector_size + byte_pos;
458 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
459 pos, bit_pos, err_byte, *(buf + byte_pos));
461 /* Bit flip in OOB area */
462 tmp = sector_num * host->pmecc_bytes_per_sector
463 + (byte_pos - sector_size);
465 ecc[tmp] ^= (1 << bit_pos);
467 pos = tmp + nand_chip->ecc.layout->eccpos[0];
468 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
469 pos, bit_pos, err_byte, ecc[tmp]);
479 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
482 struct nand_chip *nand_chip = mtd->priv;
483 struct atmel_nand_host *host = nand_chip->priv;
484 int i, err_nbr, eccbytes;
487 eccbytes = nand_chip->ecc.bytes;
488 for (i = 0; i < eccbytes; i++)
491 /* Erased page, return OK */
495 for (i = 0; i < host->pmecc_sector_number; i++) {
497 if (pmecc_stat & 0x1) {
498 buf_pos = buf + i * host->pmecc_sector_size;
500 pmecc_gen_syndrome(mtd, i);
501 pmecc_substitute(mtd);
502 pmecc_get_sigma(mtd);
504 err_nbr = pmecc_err_location(mtd);
506 dev_err(host->dev, "PMECC: Too many errors\n");
507 mtd->ecc_stats.failed++;
510 pmecc_correct_data(mtd, buf_pos, ecc, i,
511 host->pmecc_bytes_per_sector, err_nbr);
512 mtd->ecc_stats.corrected += err_nbr;
521 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
522 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
524 struct atmel_nand_host *host = chip->priv;
525 int eccsize = chip->ecc.size;
526 uint8_t *oob = chip->oob_poi;
527 uint32_t *eccpos = chip->ecc.layout->eccpos;
529 int timeout = PMECC_MAX_TIMEOUT_US;
531 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
532 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
533 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
534 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
536 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
537 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
539 chip->read_buf(mtd, buf, eccsize);
540 chip->read_buf(mtd, oob, mtd->oobsize);
543 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
550 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
554 stat = pmecc_readl(host->pmecc, isr);
556 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
562 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
563 struct nand_chip *chip, const uint8_t *buf,
566 struct atmel_nand_host *host = chip->priv;
567 uint32_t *eccpos = chip->ecc.layout->eccpos;
569 int timeout = PMECC_MAX_TIMEOUT_US;
571 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
572 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
574 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
575 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
577 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
578 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
580 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
583 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
590 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
594 for (i = 0; i < host->pmecc_sector_number; i++) {
595 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
598 pos = i * host->pmecc_bytes_per_sector + j;
599 chip->oob_poi[eccpos[pos]] =
600 readb(&host->pmecc->ecc_port[i].ecc[j]);
603 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
608 static void atmel_pmecc_core_init(struct mtd_info *mtd)
610 struct nand_chip *nand_chip = mtd->priv;
611 struct atmel_nand_host *host = nand_chip->priv;
613 struct nand_ecclayout *ecc_layout;
615 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
616 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
618 switch (host->pmecc_corr_cap) {
620 val = PMECC_CFG_BCH_ERR2;
623 val = PMECC_CFG_BCH_ERR4;
626 val = PMECC_CFG_BCH_ERR8;
629 val = PMECC_CFG_BCH_ERR12;
632 val = PMECC_CFG_BCH_ERR24;
636 if (host->pmecc_sector_size == 512)
637 val |= PMECC_CFG_SECTOR512;
638 else if (host->pmecc_sector_size == 1024)
639 val |= PMECC_CFG_SECTOR1024;
641 switch (host->pmecc_sector_number) {
643 val |= PMECC_CFG_PAGE_1SECTOR;
646 val |= PMECC_CFG_PAGE_2SECTORS;
649 val |= PMECC_CFG_PAGE_4SECTORS;
652 val |= PMECC_CFG_PAGE_8SECTORS;
656 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
657 | PMECC_CFG_AUTO_DISABLE);
658 pmecc_writel(host->pmecc, cfg, val);
660 ecc_layout = nand_chip->ecc.layout;
661 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
662 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
663 pmecc_writel(host->pmecc, eaddr,
664 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
665 /* See datasheet about PMECC Clock Control Register */
666 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
667 pmecc_writel(host->pmecc, idr, 0xff);
668 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
671 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
673 * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
674 * @ecc_bits: store the ONFI ECC correct bits capbility
675 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
677 * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
678 * @sector_size are initialize to 0.
679 * Return 0 if success to get the ECC requirement.
681 static int get_onfi_ecc_param(struct nand_chip *chip,
682 int *ecc_bits, int *sector_size)
684 *ecc_bits = *sector_size = 0;
686 if (chip->onfi_params.ecc_bits == 0xff)
687 /* TODO: the sector_size and ecc_bits need to be find in
688 * extended ecc parameter, currently we don't support it.
692 *ecc_bits = chip->onfi_params.ecc_bits;
694 /* The default sector size (ecc codeword size) is 512 */
701 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
702 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
703 * ONFI ECC parameters.
704 * @host: point to an atmel_nand_host structure.
705 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
706 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
707 * @chip: point to an nand_chip structure.
708 * @cap: store the ONFI ECC correct bits capbility
709 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
711 * Return 0 if success. otherwise return the error code.
713 static int pmecc_choose_ecc(struct atmel_nand_host *host,
714 struct nand_chip *chip,
715 int *cap, int *sector_size)
717 /* Get ECC requirement from ONFI parameters */
718 *cap = *sector_size = 0;
719 if (chip->onfi_version) {
720 if (!get_onfi_ecc_param(chip, cap, sector_size)) {
721 MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
724 dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
727 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
729 if (*cap == 0 && *sector_size == 0) {
730 /* Non-ONFI compliant or use extended ONFI parameters */
735 /* If head file doesn't specify then use the one in ONFI parameters */
736 if (host->pmecc_corr_cap == 0) {
737 /* use the most fitable ecc bits (the near bigger one ) */
739 host->pmecc_corr_cap = 2;
741 host->pmecc_corr_cap = 4;
743 host->pmecc_corr_cap = 8;
745 host->pmecc_corr_cap = 12;
747 host->pmecc_corr_cap = 24;
751 if (host->pmecc_sector_size == 0) {
752 /* use the most fitable sector size (the near smaller one ) */
753 if (*sector_size >= 1024)
754 host->pmecc_sector_size = 1024;
755 else if (*sector_size >= 512)
756 host->pmecc_sector_size = 512;
764 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
765 struct mtd_info *mtd)
767 struct atmel_nand_host *host;
768 int cap, sector_size;
770 host = nand->priv = &pmecc_host;
772 nand->ecc.mode = NAND_ECC_HW;
773 nand->ecc.calculate = NULL;
774 nand->ecc.correct = NULL;
775 nand->ecc.hwctl = NULL;
777 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
778 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
780 #ifdef CONFIG_PMECC_CAP
781 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
783 #ifdef CONFIG_PMECC_SECTOR_SIZE
784 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
786 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
787 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
790 if (pmecc_choose_ecc(host, nand, &cap, §or_size)) {
791 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
796 if (cap > host->pmecc_corr_cap)
797 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
798 host->pmecc_corr_cap, cap);
799 if (sector_size < host->pmecc_sector_size)
800 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
801 host->pmecc_sector_size, sector_size);
802 #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
803 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
804 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
807 cap = host->pmecc_corr_cap;
808 sector_size = host->pmecc_sector_size;
810 /* TODO: need check whether cap & sector_size is validate */
812 if (host->pmecc_sector_size == 512)
813 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
815 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
817 MTDDEBUG(MTD_DEBUG_LEVEL1,
818 "Initialize PMECC params, cap: %d, sector: %d\n",
821 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
822 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
824 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
826 /* ECC is calculated for the whole page (1 step) */
827 nand->ecc.size = mtd->writesize;
829 /* set ECC page size and oob layout */
830 switch (mtd->writesize) {
834 host->pmecc_degree = (sector_size == 512) ?
835 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
836 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
837 host->pmecc_sector_number = mtd->writesize / sector_size;
838 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
840 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
841 host->pmecc_index_of = host->pmecc_rom_base +
842 host->pmecc_index_table_offset;
845 nand->ecc.bytes = host->pmecc_bytes_per_sector *
846 host->pmecc_sector_number;
848 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
849 dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
850 MTD_MAX_ECCPOS_ENTRIES_LARGE);
854 if (nand->ecc.bytes > mtd->oobsize - 2) {
855 dev_err(host->dev, "No room for ECC bytes\n");
858 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
861 nand->ecc.layout = &atmel_pmecc_oobinfo;
866 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
868 /* page size not handled by HW ECC */
869 /* switching back to soft ECC */
870 nand->ecc.mode = NAND_ECC_SOFT;
871 nand->ecc.read_page = NULL;
872 nand->ecc.postpad = 0;
873 nand->ecc.prepad = 0;
878 /* Allocate data for PMECC computation */
879 if (pmecc_data_alloc(host)) {
880 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
884 nand->ecc.read_page = atmel_nand_pmecc_read_page;
885 nand->ecc.write_page = atmel_nand_pmecc_write_page;
886 nand->ecc.strength = cap;
888 atmel_pmecc_core_init(mtd);
895 /* oob layout for large page size
896 * bad block info is on bytes 0 and 1
897 * the bytes have to be consecutives to avoid
898 * several NAND_CMD_RNDOUT during read
900 static struct nand_ecclayout atmel_oobinfo_large = {
902 .eccpos = {60, 61, 62, 63},
908 /* oob layout for small page size
909 * bad block info is on bytes 4 and 5
910 * the bytes have to be consecutives to avoid
911 * several NAND_CMD_RNDOUT during read
913 static struct nand_ecclayout atmel_oobinfo_small = {
915 .eccpos = {0, 1, 2, 3},
924 * function called after a write
926 * mtd: MTD block structure
927 * dat: raw data (unused)
928 * ecc_code: buffer for ECC
930 static int atmel_nand_calculate(struct mtd_info *mtd,
931 const u_char *dat, unsigned char *ecc_code)
933 unsigned int ecc_value;
935 /* get the first 2 ECC bytes */
936 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
938 ecc_code[0] = ecc_value & 0xFF;
939 ecc_code[1] = (ecc_value >> 8) & 0xFF;
941 /* get the last 2 ECC bytes */
942 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
944 ecc_code[2] = ecc_value & 0xFF;
945 ecc_code[3] = (ecc_value >> 8) & 0xFF;
951 * HW ECC read page function
953 * mtd: mtd info structure
954 * chip: nand chip info structure
955 * buf: buffer to store read data
956 * oob_required: caller expects OOB data read to chip->oob_poi
958 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
959 uint8_t *buf, int oob_required, int page)
961 int eccsize = chip->ecc.size;
962 int eccbytes = chip->ecc.bytes;
963 uint32_t *eccpos = chip->ecc.layout->eccpos;
965 uint8_t *oob = chip->oob_poi;
970 chip->read_buf(mtd, p, eccsize);
972 /* move to ECC position if needed */
973 if (eccpos[0] != 0) {
974 /* This only works on large pages
975 * because the ECC controller waits for
976 * NAND_CMD_RNDOUTSTART after the
978 * anyway, for small pages, the eccpos[0] == 0
980 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
981 mtd->writesize + eccpos[0], -1);
984 /* the ECC controller needs to read the ECC just after the data */
985 ecc_pos = oob + eccpos[0];
986 chip->read_buf(mtd, ecc_pos, eccbytes);
988 /* check if there's an error */
989 stat = chip->ecc.correct(mtd, p, oob, NULL);
992 mtd->ecc_stats.failed++;
994 mtd->ecc_stats.corrected += stat;
996 /* get back to oob start (end of page) */
997 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1000 chip->read_buf(mtd, oob, mtd->oobsize);
1008 * function called after a read
1010 * mtd: MTD block structure
1011 * dat: raw data read from the chip
1012 * read_ecc: ECC from the chip (unused)
1015 * Detect and correct a 1 bit error for a page
1017 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1018 u_char *read_ecc, u_char *isnull)
1020 struct nand_chip *nand_chip = mtd->priv;
1021 unsigned int ecc_status;
1022 unsigned int ecc_word, ecc_bit;
1024 /* get the status from the Status Register */
1025 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1027 /* if there's no error */
1028 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1031 /* get error bit offset (4 bits) */
1032 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1033 /* get word address (12 bits) */
1034 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1037 /* if there are multiple errors */
1038 if (ecc_status & ATMEL_ECC_MULERR) {
1039 /* check if it is a freshly erased block
1040 * (filled with 0xff) */
1041 if ((ecc_bit == ATMEL_ECC_BITADDR)
1042 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1043 /* the block has just been erased, return OK */
1046 /* it doesn't seems to be a freshly
1048 * We can't correct so many errors */
1049 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1050 " Unable to correct.\n");
1054 /* if there's a single bit error : we can correct it */
1055 if (ecc_status & ATMEL_ECC_ECCERR) {
1056 /* there's nothing much to do here.
1057 * the bit error is on the ECC itself.
1059 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1060 " Nothing to correct\n");
1064 dev_warn(host->dev, "atmel_nand : one bit error on data."
1065 " (word offset in the page :"
1066 " 0x%x bit offset : 0x%x)\n",
1068 /* correct the error */
1069 if (nand_chip->options & NAND_BUSWIDTH_16) {
1071 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1074 dat[ecc_word] ^= (1 << ecc_bit);
1076 dev_warn(host->dev, "atmel_nand : error corrected\n");
1081 * Enable HW ECC : unused on most chips
1083 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1087 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1089 nand->ecc.mode = NAND_ECC_HW;
1090 nand->ecc.calculate = atmel_nand_calculate;
1091 nand->ecc.correct = atmel_nand_correct;
1092 nand->ecc.hwctl = atmel_nand_hwctl;
1093 nand->ecc.read_page = atmel_nand_read_page;
1094 nand->ecc.bytes = 4;
1096 if (nand->ecc.mode == NAND_ECC_HW) {
1097 /* ECC is calculated for the whole page (1 step) */
1098 nand->ecc.size = mtd->writesize;
1100 /* set ECC page size and oob layout */
1101 switch (mtd->writesize) {
1103 nand->ecc.layout = &atmel_oobinfo_small;
1104 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1105 ATMEL_ECC_PAGESIZE_528);
1108 nand->ecc.layout = &atmel_oobinfo_large;
1109 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1110 ATMEL_ECC_PAGESIZE_1056);
1113 nand->ecc.layout = &atmel_oobinfo_large;
1114 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1115 ATMEL_ECC_PAGESIZE_2112);
1118 nand->ecc.layout = &atmel_oobinfo_large;
1119 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1120 ATMEL_ECC_PAGESIZE_4224);
1123 /* page size not handled by HW ECC */
1124 /* switching back to soft ECC */
1125 nand->ecc.mode = NAND_ECC_SOFT;
1126 nand->ecc.calculate = NULL;
1127 nand->ecc.correct = NULL;
1128 nand->ecc.hwctl = NULL;
1129 nand->ecc.read_page = NULL;
1130 nand->ecc.postpad = 0;
1131 nand->ecc.prepad = 0;
1132 nand->ecc.bytes = 0;
1140 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1142 #endif /* CONFIG_ATMEL_NAND_HWECC */
1144 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1145 int cmd, unsigned int ctrl)
1147 struct nand_chip *this = mtd->priv;
1149 if (ctrl & NAND_CTRL_CHANGE) {
1150 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1151 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1152 | CONFIG_SYS_NAND_MASK_CLE);
1154 if (ctrl & NAND_CLE)
1155 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1156 if (ctrl & NAND_ALE)
1157 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1159 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1160 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
1162 this->IO_ADDR_W = (void *) IO_ADDR_W;
1165 if (cmd != NAND_CMD_NONE)
1166 writeb(cmd, this->IO_ADDR_W);
1169 #ifdef CONFIG_SYS_NAND_READY_PIN
1170 static int at91_nand_ready(struct mtd_info *mtd)
1172 return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
1176 #ifdef CONFIG_SPL_BUILD
1177 /* The following code is for SPL */
1178 static nand_info_t mtd;
1179 static struct nand_chip nand_chip;
1181 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1183 struct nand_chip *this = mtd.priv;
1184 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1185 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1186 unsigned int ctrl) = this->cmd_ctrl;
1188 while (this->dev_ready(&mtd))
1191 if (cmd == NAND_CMD_READOOB) {
1192 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1193 cmd = NAND_CMD_READ0;
1196 hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1198 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1201 hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1202 hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1203 hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1204 hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1205 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1206 hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1208 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1210 hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1211 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1213 while (this->dev_ready(&mtd))
1219 static int nand_is_bad_block(int block)
1221 struct nand_chip *this = mtd.priv;
1223 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1225 if (this->options & NAND_BUSWIDTH_16) {
1226 if (readw(this->IO_ADDR_R) != 0xffff)
1229 if (readb(this->IO_ADDR_R) != 0xff)
1236 #ifdef CONFIG_SPL_NAND_ECC
1237 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1238 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1239 CONFIG_SYS_NAND_ECCSIZE)
1240 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1242 static int nand_read_page(int block, int page, void *dst)
1244 struct nand_chip *this = mtd.priv;
1245 u_char ecc_calc[ECCTOTAL];
1246 u_char ecc_code[ECCTOTAL];
1247 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1248 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1249 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1250 int eccsteps = ECCSTEPS;
1253 nand_command(block, page, 0, NAND_CMD_READ0);
1255 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1256 if (this->ecc.mode != NAND_ECC_SOFT)
1257 this->ecc.hwctl(&mtd, NAND_ECC_READ);
1258 this->read_buf(&mtd, p, eccsize);
1259 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
1261 this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1263 for (i = 0; i < ECCTOTAL; i++)
1264 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1266 eccsteps = ECCSTEPS;
1269 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1270 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
1275 static int nand_read_page(int block, int page, void *dst)
1277 struct nand_chip *this = mtd.priv;
1279 nand_command(block, page, 0, NAND_CMD_READ0);
1280 atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
1284 #endif /* CONFIG_SPL_NAND_ECC */
1286 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
1288 unsigned int block, lastblock;
1291 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
1292 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
1293 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
1295 while (block <= lastblock) {
1296 if (!nand_is_bad_block(block)) {
1297 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
1298 nand_read_page(block, page, dst);
1299 dst += CONFIG_SYS_NAND_PAGE_SIZE;
1314 int at91_nand_wait_ready(struct mtd_info *mtd)
1316 struct nand_chip *this = mtd->priv;
1318 udelay(this->chip_delay);
1323 int board_nand_init(struct nand_chip *nand)
1327 nand->ecc.mode = NAND_ECC_SOFT;
1328 #ifdef CONFIG_SYS_NAND_DBW_16
1329 nand->options = NAND_BUSWIDTH_16;
1330 nand->read_buf = nand_read_buf16;
1332 nand->read_buf = nand_read_buf;
1334 nand->cmd_ctrl = at91_nand_hwcontrol;
1335 #ifdef CONFIG_SYS_NAND_READY_PIN
1336 nand->dev_ready = at91_nand_ready;
1338 nand->dev_ready = at91_nand_wait_ready;
1340 nand->chip_delay = 20;
1342 #ifdef CONFIG_ATMEL_NAND_HWECC
1343 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1344 ret = atmel_pmecc_nand_init_params(nand, &mtd);
1351 void nand_init(void)
1353 mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1354 mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
1355 mtd.priv = &nand_chip;
1356 nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1357 nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1358 board_nand_init(&nand_chip);
1360 #ifdef CONFIG_SPL_NAND_ECC
1361 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1362 nand_chip.ecc.calculate = nand_calculate_ecc;
1363 nand_chip.ecc.correct = nand_correct_data;
1367 if (nand_chip.select_chip)
1368 nand_chip.select_chip(&mtd, 0);
1371 void nand_deselect(void)
1373 if (nand_chip.select_chip)
1374 nand_chip.select_chip(&mtd, -1);
1379 #ifndef CONFIG_SYS_NAND_BASE_LIST
1380 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1382 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1383 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1385 int atmel_nand_chip_init(int devnum, ulong base_addr)
1388 struct mtd_info *mtd = &nand_info[devnum];
1389 struct nand_chip *nand = &nand_chip[devnum];
1392 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
1394 #ifdef CONFIG_NAND_ECC_BCH
1395 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1397 nand->ecc.mode = NAND_ECC_SOFT;
1399 #ifdef CONFIG_SYS_NAND_DBW_16
1400 nand->options = NAND_BUSWIDTH_16;
1402 nand->cmd_ctrl = at91_nand_hwcontrol;
1403 #ifdef CONFIG_SYS_NAND_READY_PIN
1404 nand->dev_ready = at91_nand_ready;
1406 nand->chip_delay = 75;
1408 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1412 #ifdef CONFIG_ATMEL_NAND_HWECC
1413 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1414 ret = atmel_pmecc_nand_init_params(nand, mtd);
1416 ret = atmel_hwecc_nand_init_param(nand, mtd);
1422 ret = nand_scan_tail(mtd);
1424 nand_register(devnum);
1429 void board_nand_init(void)
1432 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1433 if (atmel_nand_chip_init(i, base_addr[i]))
1434 dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1437 #endif /* CONFIG_SPL_BUILD */