2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/arch/hardware.h>
29 #include <asm/arch/gpio.h>
30 #include <asm/arch/at91_pio.h>
34 #ifdef CONFIG_ATMEL_NAND_HWECC
36 /* Register access macros */
37 #define ecc_readl(add, reg) \
38 readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
39 #define ecc_writel(add, reg, value) \
40 writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
42 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
44 /* oob layout for large page size
45 * bad block info is on bytes 0 and 1
46 * the bytes have to be consecutives to avoid
47 * several NAND_CMD_RNDOUT during read
49 static struct nand_ecclayout atmel_oobinfo_large = {
51 .eccpos = {60, 61, 62, 63},
57 /* oob layout for small page size
58 * bad block info is on bytes 4 and 5
59 * the bytes have to be consecutives to avoid
60 * several NAND_CMD_RNDOUT during read
62 static struct nand_ecclayout atmel_oobinfo_small = {
64 .eccpos = {0, 1, 2, 3},
73 * function called after a write
75 * mtd: MTD block structure
76 * dat: raw data (unused)
77 * ecc_code: buffer for ECC
79 static int atmel_nand_calculate(struct mtd_info *mtd,
80 const u_char *dat, unsigned char *ecc_code)
82 unsigned int ecc_value;
84 /* get the first 2 ECC bytes */
85 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
87 ecc_code[0] = ecc_value & 0xFF;
88 ecc_code[1] = (ecc_value >> 8) & 0xFF;
90 /* get the last 2 ECC bytes */
91 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
93 ecc_code[2] = ecc_value & 0xFF;
94 ecc_code[3] = (ecc_value >> 8) & 0xFF;
100 * HW ECC read page function
102 * mtd: mtd info structure
103 * chip: nand chip info structure
104 * buf: buffer to store read data
106 static int atmel_nand_read_page(struct mtd_info *mtd,
107 struct nand_chip *chip, uint8_t *buf, int page)
109 int eccsize = chip->ecc.size;
110 int eccbytes = chip->ecc.bytes;
111 uint32_t *eccpos = chip->ecc.layout->eccpos;
113 uint8_t *oob = chip->oob_poi;
118 chip->read_buf(mtd, p, eccsize);
120 /* move to ECC position if needed */
121 if (eccpos[0] != 0) {
122 /* This only works on large pages
123 * because the ECC controller waits for
124 * NAND_CMD_RNDOUTSTART after the
126 * anyway, for small pages, the eccpos[0] == 0
128 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
129 mtd->writesize + eccpos[0], -1);
132 /* the ECC controller needs to read the ECC just after the data */
133 ecc_pos = oob + eccpos[0];
134 chip->read_buf(mtd, ecc_pos, eccbytes);
136 /* check if there's an error */
137 stat = chip->ecc.correct(mtd, p, oob, NULL);
140 mtd->ecc_stats.failed++;
142 mtd->ecc_stats.corrected += stat;
144 /* get back to oob start (end of page) */
145 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
148 chip->read_buf(mtd, oob, mtd->oobsize);
156 * function called after a read
158 * mtd: MTD block structure
159 * dat: raw data read from the chip
160 * read_ecc: ECC from the chip (unused)
163 * Detect and correct a 1 bit error for a page
165 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
166 u_char *read_ecc, u_char *isnull)
168 struct nand_chip *nand_chip = mtd->priv;
169 unsigned int ecc_status;
170 unsigned int ecc_word, ecc_bit;
172 /* get the status from the Status Register */
173 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
175 /* if there's no error */
176 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
179 /* get error bit offset (4 bits) */
180 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
181 /* get word address (12 bits) */
182 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
185 /* if there are multiple errors */
186 if (ecc_status & ATMEL_ECC_MULERR) {
187 /* check if it is a freshly erased block
188 * (filled with 0xff) */
189 if ((ecc_bit == ATMEL_ECC_BITADDR)
190 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
191 /* the block has just been erased, return OK */
194 /* it doesn't seems to be a freshly
196 * We can't correct so many errors */
197 printk(KERN_WARNING "atmel_nand : multiple errors detected."
198 " Unable to correct.\n");
202 /* if there's a single bit error : we can correct it */
203 if (ecc_status & ATMEL_ECC_ECCERR) {
204 /* there's nothing much to do here.
205 * the bit error is on the ECC itself.
207 printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
208 " Nothing to correct\n");
212 printk(KERN_WARNING "atmel_nand : one bit error on data."
213 " (word offset in the page :"
214 " 0x%x bit offset : 0x%x)\n",
216 /* correct the error */
217 if (nand_chip->options & NAND_BUSWIDTH_16) {
219 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
222 dat[ecc_word] ^= (1 << ecc_bit);
224 printk(KERN_WARNING "atmel_nand : error corrected\n");
229 * Enable HW ECC : unused on most chips
231 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
235 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
237 nand->ecc.mode = NAND_ECC_HW;
238 nand->ecc.calculate = atmel_nand_calculate;
239 nand->ecc.correct = atmel_nand_correct;
240 nand->ecc.hwctl = atmel_nand_hwctl;
241 nand->ecc.read_page = atmel_nand_read_page;
244 if (nand->ecc.mode == NAND_ECC_HW) {
245 /* ECC is calculated for the whole page (1 step) */
246 nand->ecc.size = mtd->writesize;
248 /* set ECC page size and oob layout */
249 switch (mtd->writesize) {
251 nand->ecc.layout = &atmel_oobinfo_small;
252 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
253 ATMEL_ECC_PAGESIZE_528);
256 nand->ecc.layout = &atmel_oobinfo_large;
257 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
258 ATMEL_ECC_PAGESIZE_1056);
261 nand->ecc.layout = &atmel_oobinfo_large;
262 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
263 ATMEL_ECC_PAGESIZE_2112);
266 nand->ecc.layout = &atmel_oobinfo_large;
267 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
268 ATMEL_ECC_PAGESIZE_4224);
271 /* page size not handled by HW ECC */
272 /* switching back to soft ECC */
273 nand->ecc.mode = NAND_ECC_SOFT;
274 nand->ecc.calculate = NULL;
275 nand->ecc.correct = NULL;
276 nand->ecc.hwctl = NULL;
277 nand->ecc.read_page = NULL;
278 nand->ecc.postpad = 0;
279 nand->ecc.prepad = 0;
290 static void at91_nand_hwcontrol(struct mtd_info *mtd,
291 int cmd, unsigned int ctrl)
293 struct nand_chip *this = mtd->priv;
295 if (ctrl & NAND_CTRL_CHANGE) {
296 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
297 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
298 | CONFIG_SYS_NAND_MASK_CLE);
301 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
303 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
305 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
306 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
309 this->IO_ADDR_W = (void *) IO_ADDR_W;
312 if (cmd != NAND_CMD_NONE)
313 writeb(cmd, this->IO_ADDR_W);
316 #ifdef CONFIG_SYS_NAND_READY_PIN
317 static int at91_nand_ready(struct mtd_info *mtd)
319 return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
323 #ifndef CONFIG_SYS_NAND_BASE_LIST
324 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
326 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
327 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
329 int atmel_nand_chip_init(int devnum, ulong base_addr)
332 struct mtd_info *mtd = &nand_info[devnum];
333 struct nand_chip *nand = &nand_chip[devnum];
336 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
338 nand->ecc.mode = NAND_ECC_SOFT;
339 #ifdef CONFIG_SYS_NAND_DBW_16
340 nand->options = NAND_BUSWIDTH_16;
342 nand->cmd_ctrl = at91_nand_hwcontrol;
343 #ifdef CONFIG_SYS_NAND_READY_PIN
344 nand->dev_ready = at91_nand_ready;
346 nand->chip_delay = 20;
348 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
352 #ifdef CONFIG_ATMEL_NAND_HWECC
353 ret = atmel_hwecc_nand_init_param(nand, mtd);
358 ret = nand_scan_tail(mtd);
360 nand_register(devnum);
365 void board_nand_init(void)
368 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
369 if (atmel_nand_chip_init(i, base_addr[i]))
370 printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",