2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 * Add Programmable Multibit ECC support for various AT91 SoC
9 * (C) Copyright 2012 ATMEL, Hong Xu
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/gpio.h>
21 #include <linux/mtd/nand_ecc.h>
23 #ifdef CONFIG_ATMEL_NAND_HWECC
25 /* Register access macros */
26 #define ecc_readl(add, reg) \
27 readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
28 #define ecc_writel(add, reg, value) \
29 writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
31 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
33 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
35 #ifdef CONFIG_SPL_BUILD
36 #undef CONFIG_SYS_NAND_ONFI_DETECTION
39 struct atmel_nand_host {
40 struct pmecc_regs __iomem *pmecc;
41 struct pmecc_errloc_regs __iomem *pmerrloc;
42 void __iomem *pmecc_rom_base;
45 u16 pmecc_sector_size;
46 u32 pmecc_index_table_offset;
49 int pmecc_bytes_per_sector;
50 int pmecc_sector_number;
51 int pmecc_degree; /* Degree of remainders */
52 int pmecc_cw_len; /* Length of codeword */
54 /* lookup table for alpha_to and index_of */
55 void __iomem *pmecc_alpha_to;
56 void __iomem *pmecc_index_of;
58 /* data for pmecc computation */
60 int16_t *pmecc_partial_syn;
62 int16_t *pmecc_lmu; /* polynomal order */
68 static struct atmel_nand_host pmecc_host;
69 static struct nand_ecclayout atmel_pmecc_oobinfo;
72 * Return number of ecc bytes per sector according to sector size and
73 * correction capability
75 * Following table shows what at91 PMECC supported:
76 * Correction Capability Sector_512_bytes Sector_1024_bytes
77 * ===================== ================ =================
78 * 2-bits 4-bytes 4-bytes
79 * 4-bits 7-bytes 7-bytes
80 * 8-bits 13-bytes 14-bytes
81 * 12-bits 20-bytes 21-bytes
82 * 24-bits 39-bytes 42-bytes
84 static int pmecc_get_ecc_bytes(int cap, int sector_size)
86 int m = 12 + sector_size / 512;
87 return (m * cap + 7) / 8;
90 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
91 int oobsize, int ecc_len)
95 layout->eccbytes = ecc_len;
97 /* ECC will occupy the last ecc_len bytes continuously */
98 for (i = 0; i < ecc_len; i++)
99 layout->eccpos[i] = oobsize - ecc_len + i;
101 layout->oobfree[0].offset = 2;
102 layout->oobfree[0].length =
103 oobsize - ecc_len - layout->oobfree[0].offset;
106 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
110 table_size = host->pmecc_sector_size == 512 ?
111 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
113 /* the ALPHA lookup table is right behind the INDEX lookup table. */
114 return host->pmecc_rom_base + host->pmecc_index_table_offset +
115 table_size * sizeof(int16_t);
118 static void pmecc_data_free(struct atmel_nand_host *host)
120 free(host->pmecc_partial_syn);
121 free(host->pmecc_si);
122 free(host->pmecc_lmu);
123 free(host->pmecc_smu);
124 free(host->pmecc_mu);
125 free(host->pmecc_dmu);
126 free(host->pmecc_delta);
129 static int pmecc_data_alloc(struct atmel_nand_host *host)
131 const int cap = host->pmecc_corr_cap;
134 size = (2 * cap + 1) * sizeof(int16_t);
135 host->pmecc_partial_syn = malloc(size);
136 host->pmecc_si = malloc(size);
137 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
138 host->pmecc_smu = malloc((cap + 2) * size);
140 size = (cap + 1) * sizeof(int);
141 host->pmecc_mu = malloc(size);
142 host->pmecc_dmu = malloc(size);
143 host->pmecc_delta = malloc(size);
145 if (host->pmecc_partial_syn &&
155 pmecc_data_free(host);
160 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
162 struct nand_chip *nand_chip = mtd->priv;
163 struct atmel_nand_host *host = nand_chip->priv;
167 /* Fill odd syndromes */
168 for (i = 0; i < host->pmecc_corr_cap; i++) {
169 value = pmecc_readl(host->pmecc, rem_port[sector].rem[i / 2]);
173 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
177 static void pmecc_substitute(struct mtd_info *mtd)
179 struct nand_chip *nand_chip = mtd->priv;
180 struct atmel_nand_host *host = nand_chip->priv;
181 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
182 int16_t __iomem *index_of = host->pmecc_index_of;
183 int16_t *partial_syn = host->pmecc_partial_syn;
184 const int cap = host->pmecc_corr_cap;
188 /* si[] is a table that holds the current syndrome value,
189 * an element of that table belongs to the field
193 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
195 /* Computation 2t syndromes based on S(x) */
197 for (i = 1; i < 2 * cap; i += 2) {
198 for (j = 0; j < host->pmecc_degree; j++) {
199 if (partial_syn[i] & (0x1 << j))
200 si[i] = readw(alpha_to + i * j) ^ si[i];
203 /* Even syndrome = (Odd syndrome) ** 2 */
204 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
210 tmp = readw(index_of + si[j]);
211 tmp = (tmp * 2) % host->pmecc_cw_len;
212 si[i] = readw(alpha_to + tmp);
218 * This function defines a Berlekamp iterative procedure for
219 * finding the value of the error location polynomial.
220 * The input is si[], initialize by pmecc_substitute().
221 * The output is smu[][].
223 * This function is written according to chip datasheet Chapter:
224 * Find the Error Location Polynomial Sigma(x) of Section:
225 * Programmable Multibit ECC Control (PMECC).
227 static void pmecc_get_sigma(struct mtd_info *mtd)
229 struct nand_chip *nand_chip = mtd->priv;
230 struct atmel_nand_host *host = nand_chip->priv;
232 int16_t *lmu = host->pmecc_lmu;
233 int16_t *si = host->pmecc_si;
234 int *mu = host->pmecc_mu;
235 int *dmu = host->pmecc_dmu; /* Discrepancy */
236 int *delta = host->pmecc_delta; /* Delta order */
237 int cw_len = host->pmecc_cw_len;
238 const int16_t cap = host->pmecc_corr_cap;
239 const int num = 2 * cap + 1;
240 int16_t __iomem *index_of = host->pmecc_index_of;
241 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
243 uint32_t dmu_0_count, tmp;
244 int16_t *smu = host->pmecc_smu;
246 /* index of largest delta */
251 /* Init the Sigma(x) */
252 memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
263 /* discrepancy set to 1 */
265 /* polynom order set to 0 */
267 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
274 /* Sigma(x) set to 1 */
277 /* discrepancy set to S1 */
280 /* polynom order set to 0 */
283 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
286 for (i = 1; i <= cap; i++) {
288 /* Begin Computing Sigma (Mu+1) and L(mu) */
289 /* check if discrepancy is set to 0 */
293 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
294 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
299 if (dmu_0_count == tmp) {
300 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
301 smu[(cap + 1) * num + j] =
304 lmu[cap + 1] = lmu[i];
309 for (j = 0; j <= lmu[i] >> 1; j++)
310 smu[(i + 1) * num + j] = smu[i * num + j];
312 /* copy previous polynom order to the next */
317 /* find largest delta with dmu != 0 */
318 for (j = 0; j < i; j++) {
319 if ((dmu[j]) && (delta[j] > largest)) {
325 /* compute difference */
326 diff = (mu[i] - mu[ro]);
328 /* Compute degree of the new smu polynomial */
329 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
332 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
334 /* Init smu[i+1] with 0 */
335 for (k = 0; k < num; k++)
336 smu[(i + 1) * num + k] = 0;
338 /* Compute smu[i+1] */
339 for (k = 0; k <= lmu[ro] >> 1; k++) {
342 if (!(smu[ro * num + k] && dmu[i]))
344 a = readw(index_of + dmu[i]);
345 b = readw(index_of + dmu[ro]);
346 c = readw(index_of + smu[ro * num + k]);
347 tmp = a + (cw_len - b) + c;
348 a = readw(alpha_to + tmp % cw_len);
349 smu[(i + 1) * num + (k + diff)] = a;
352 for (k = 0; k <= lmu[i] >> 1; k++)
353 smu[(i + 1) * num + k] ^= smu[i * num + k];
356 /* End Computing Sigma (Mu+1) and L(mu) */
357 /* In either case compute delta */
358 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
360 /* Do not compute discrepancy for the last iteration */
364 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
367 dmu[i + 1] = si[tmp + 3];
368 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
371 smu[(i + 1) * num + k]);
372 b = si[2 * (i - 1) + 3 - k];
373 c = readw(index_of + b);
376 dmu[i + 1] = readw(alpha_to + tmp) ^
383 static int pmecc_err_location(struct mtd_info *mtd)
385 struct nand_chip *nand_chip = mtd->priv;
386 struct atmel_nand_host *host = nand_chip->priv;
387 const int cap = host->pmecc_corr_cap;
388 const int num = 2 * cap + 1;
389 int sector_size = host->pmecc_sector_size;
390 int err_nbr = 0; /* number of error */
391 int roots_nbr; /* number of roots */
394 int16_t *smu = host->pmecc_smu;
395 int timeout = PMECC_MAX_TIMEOUT_US;
397 pmecc_writel(host->pmerrloc, eldis, PMERRLOC_DISABLE);
399 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
400 pmecc_writel(host->pmerrloc, sigma[i],
401 smu[(cap + 1) * num + i]);
405 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
406 if (sector_size == 1024)
407 val |= PMERRLOC_ELCFG_SECTOR_1024;
409 pmecc_writel(host->pmerrloc, elcfg, val);
410 pmecc_writel(host->pmerrloc, elen,
411 sector_size * 8 + host->pmecc_degree * cap);
414 if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
421 dev_err(host->dev, "atmel_nand : Timeout to calculate PMECC error location\n");
425 roots_nbr = (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_ERR_NUM_MASK)
427 /* Number of roots == degree of smu hence <= cap */
428 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
431 /* Number of roots does not match the degree of smu
432 * unable to correct error */
436 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
437 int sector_num, int extra_bytes, int err_nbr)
439 struct nand_chip *nand_chip = mtd->priv;
440 struct atmel_nand_host *host = nand_chip->priv;
442 int byte_pos, bit_pos, sector_size, pos;
446 sector_size = host->pmecc_sector_size;
449 tmp = pmecc_readl(host->pmerrloc, el[i]) - 1;
453 if (byte_pos >= (sector_size + extra_bytes))
454 BUG(); /* should never happen */
456 if (byte_pos < sector_size) {
457 err_byte = *(buf + byte_pos);
458 *(buf + byte_pos) ^= (1 << bit_pos);
460 pos = sector_num * host->pmecc_sector_size + byte_pos;
461 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
462 pos, bit_pos, err_byte, *(buf + byte_pos));
464 /* Bit flip in OOB area */
465 tmp = sector_num * host->pmecc_bytes_per_sector
466 + (byte_pos - sector_size);
468 ecc[tmp] ^= (1 << bit_pos);
470 pos = tmp + nand_chip->ecc.layout->eccpos[0];
471 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
472 pos, bit_pos, err_byte, ecc[tmp]);
482 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
485 struct nand_chip *nand_chip = mtd->priv;
486 struct atmel_nand_host *host = nand_chip->priv;
487 int i, err_nbr, eccbytes;
490 /* SAMA5D4 PMECC IP can correct errors for all 0xff page */
491 if (host->pmecc_version >= PMECC_VERSION_SAMA5D4)
494 eccbytes = nand_chip->ecc.bytes;
495 for (i = 0; i < eccbytes; i++)
498 /* Erased page, return OK */
502 for (i = 0; i < host->pmecc_sector_number; i++) {
504 if (pmecc_stat & 0x1) {
505 buf_pos = buf + i * host->pmecc_sector_size;
507 pmecc_gen_syndrome(mtd, i);
508 pmecc_substitute(mtd);
509 pmecc_get_sigma(mtd);
511 err_nbr = pmecc_err_location(mtd);
513 dev_err(host->dev, "PMECC: Too many errors\n");
514 mtd->ecc_stats.failed++;
517 pmecc_correct_data(mtd, buf_pos, ecc, i,
518 host->pmecc_bytes_per_sector, err_nbr);
519 mtd->ecc_stats.corrected += err_nbr;
528 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
529 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
531 struct atmel_nand_host *host = chip->priv;
532 int eccsize = chip->ecc.size;
533 uint8_t *oob = chip->oob_poi;
534 uint32_t *eccpos = chip->ecc.layout->eccpos;
536 int timeout = PMECC_MAX_TIMEOUT_US;
538 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
539 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
540 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
541 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
543 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
544 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
546 chip->read_buf(mtd, buf, eccsize);
547 chip->read_buf(mtd, oob, mtd->oobsize);
550 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
557 dev_err(host->dev, "atmel_nand : Timeout to read PMECC page\n");
561 stat = pmecc_readl(host->pmecc, isr);
563 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
569 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
570 struct nand_chip *chip, const uint8_t *buf,
573 struct atmel_nand_host *host = chip->priv;
574 uint32_t *eccpos = chip->ecc.layout->eccpos;
576 int timeout = PMECC_MAX_TIMEOUT_US;
578 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
579 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
581 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
582 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
584 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
585 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
587 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
590 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
597 dev_err(host->dev, "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
601 for (i = 0; i < host->pmecc_sector_number; i++) {
602 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
605 pos = i * host->pmecc_bytes_per_sector + j;
606 chip->oob_poi[eccpos[pos]] =
607 pmecc_readb(host->pmecc, ecc_port[i].ecc[j]);
610 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
615 static void atmel_pmecc_core_init(struct mtd_info *mtd)
617 struct nand_chip *nand_chip = mtd->priv;
618 struct atmel_nand_host *host = nand_chip->priv;
620 struct nand_ecclayout *ecc_layout;
622 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
623 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
625 switch (host->pmecc_corr_cap) {
627 val = PMECC_CFG_BCH_ERR2;
630 val = PMECC_CFG_BCH_ERR4;
633 val = PMECC_CFG_BCH_ERR8;
636 val = PMECC_CFG_BCH_ERR12;
639 val = PMECC_CFG_BCH_ERR24;
643 if (host->pmecc_sector_size == 512)
644 val |= PMECC_CFG_SECTOR512;
645 else if (host->pmecc_sector_size == 1024)
646 val |= PMECC_CFG_SECTOR1024;
648 switch (host->pmecc_sector_number) {
650 val |= PMECC_CFG_PAGE_1SECTOR;
653 val |= PMECC_CFG_PAGE_2SECTORS;
656 val |= PMECC_CFG_PAGE_4SECTORS;
659 val |= PMECC_CFG_PAGE_8SECTORS;
663 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
664 | PMECC_CFG_AUTO_DISABLE);
665 pmecc_writel(host->pmecc, cfg, val);
667 ecc_layout = nand_chip->ecc.layout;
668 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
669 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
670 pmecc_writel(host->pmecc, eaddr,
671 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
672 /* See datasheet about PMECC Clock Control Register */
673 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
674 pmecc_writel(host->pmecc, idr, 0xff);
675 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
678 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
680 * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
681 * @ecc_bits: store the ONFI ECC correct bits capbility
682 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
684 * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
685 * @sector_size are initialize to 0.
686 * Return 0 if success to get the ECC requirement.
688 static int get_onfi_ecc_param(struct nand_chip *chip,
689 int *ecc_bits, int *sector_size)
691 *ecc_bits = *sector_size = 0;
693 if (chip->onfi_params.ecc_bits == 0xff)
694 /* TODO: the sector_size and ecc_bits need to be find in
695 * extended ecc parameter, currently we don't support it.
699 *ecc_bits = chip->onfi_params.ecc_bits;
701 /* The default sector size (ecc codeword size) is 512 */
708 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
709 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
710 * ONFI ECC parameters.
711 * @host: point to an atmel_nand_host structure.
712 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
713 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
714 * @chip: point to an nand_chip structure.
715 * @cap: store the ONFI ECC correct bits capbility
716 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
718 * Return 0 if success. otherwise return the error code.
720 static int pmecc_choose_ecc(struct atmel_nand_host *host,
721 struct nand_chip *chip,
722 int *cap, int *sector_size)
724 /* Get ECC requirement from ONFI parameters */
725 *cap = *sector_size = 0;
726 if (chip->onfi_version) {
727 if (!get_onfi_ecc_param(chip, cap, sector_size)) {
728 MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
731 dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
734 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
736 if (*cap == 0 && *sector_size == 0) {
737 /* Non-ONFI compliant or use extended ONFI parameters */
742 /* If head file doesn't specify then use the one in ONFI parameters */
743 if (host->pmecc_corr_cap == 0) {
744 /* use the most fitable ecc bits (the near bigger one ) */
746 host->pmecc_corr_cap = 2;
748 host->pmecc_corr_cap = 4;
750 host->pmecc_corr_cap = 8;
752 host->pmecc_corr_cap = 12;
754 host->pmecc_corr_cap = 24;
758 if (host->pmecc_sector_size == 0) {
759 /* use the most fitable sector size (the near smaller one ) */
760 if (*sector_size >= 1024)
761 host->pmecc_sector_size = 1024;
762 else if (*sector_size >= 512)
763 host->pmecc_sector_size = 512;
771 #if defined(NO_GALOIS_TABLE_IN_ROM)
772 static uint16_t *pmecc_galois_table;
773 static inline int deg(unsigned int poly)
775 /* polynomial degree is the most-significant bit index */
776 return fls(poly) - 1;
779 static int build_gf_tables(int mm, unsigned int poly,
780 int16_t *index_of, int16_t *alpha_to)
782 unsigned int i, x = 1;
783 const unsigned int k = 1 << deg(poly);
784 unsigned int nn = (1 << mm) - 1;
786 /* primitive polynomial must be of degree m */
790 for (i = 0; i < nn; i++) {
794 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
807 static uint16_t *create_lookup_table(int sector_size)
809 int degree = (sector_size == 512) ?
810 PMECC_GF_DIMENSION_13 :
811 PMECC_GF_DIMENSION_14;
812 unsigned int poly = (sector_size == 512) ?
813 PMECC_GF_13_PRIMITIVE_POLY :
814 PMECC_GF_14_PRIMITIVE_POLY;
815 int table_size = (sector_size == 512) ?
816 PMECC_INDEX_TABLE_SIZE_512 :
817 PMECC_INDEX_TABLE_SIZE_1024;
819 int16_t *addr = kzalloc(2 * table_size * sizeof(uint16_t), GFP_KERNEL);
820 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
823 return (uint16_t *)addr;
827 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
828 struct mtd_info *mtd)
830 struct atmel_nand_host *host;
831 int cap, sector_size;
833 host = nand->priv = &pmecc_host;
835 nand->ecc.mode = NAND_ECC_HW;
836 nand->ecc.calculate = NULL;
837 nand->ecc.correct = NULL;
838 nand->ecc.hwctl = NULL;
840 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
841 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
843 #ifdef CONFIG_PMECC_CAP
844 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
846 #ifdef CONFIG_PMECC_SECTOR_SIZE
847 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
849 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
850 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
853 if (pmecc_choose_ecc(host, nand, &cap, §or_size)) {
854 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
859 if (cap > host->pmecc_corr_cap)
860 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
861 host->pmecc_corr_cap, cap);
862 if (sector_size < host->pmecc_sector_size)
863 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
864 host->pmecc_sector_size, sector_size);
865 #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
866 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
867 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
870 cap = host->pmecc_corr_cap;
871 sector_size = host->pmecc_sector_size;
873 /* TODO: need check whether cap & sector_size is validate */
874 #if defined(NO_GALOIS_TABLE_IN_ROM)
876 * As pmecc_rom_base is the begin of the gallois field table, So the
877 * index offset just set as 0.
879 host->pmecc_index_table_offset = 0;
881 if (host->pmecc_sector_size == 512)
882 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
884 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
887 MTDDEBUG(MTD_DEBUG_LEVEL1,
888 "Initialize PMECC params, cap: %d, sector: %d\n",
891 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
892 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
894 #if defined(NO_GALOIS_TABLE_IN_ROM)
895 pmecc_galois_table = create_lookup_table(host->pmecc_sector_size);
896 if (!pmecc_galois_table) {
897 dev_err(host->dev, "out of memory\n");
901 host->pmecc_rom_base = (void __iomem *)pmecc_galois_table;
903 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
906 /* ECC is calculated for the whole page (1 step) */
907 nand->ecc.size = mtd->writesize;
909 /* set ECC page size and oob layout */
910 switch (mtd->writesize) {
914 host->pmecc_degree = (sector_size == 512) ?
915 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
916 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
917 host->pmecc_sector_number = mtd->writesize / sector_size;
918 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
920 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
921 host->pmecc_index_of = host->pmecc_rom_base +
922 host->pmecc_index_table_offset;
925 nand->ecc.bytes = host->pmecc_bytes_per_sector *
926 host->pmecc_sector_number;
928 if (nand->ecc.bytes > MTD_MAX_ECCPOS_ENTRIES_LARGE) {
929 dev_err(host->dev, "too large eccpos entries. max support ecc.bytes is %d\n",
930 MTD_MAX_ECCPOS_ENTRIES_LARGE);
934 if (nand->ecc.bytes > mtd->oobsize - 2) {
935 dev_err(host->dev, "No room for ECC bytes\n");
938 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
941 nand->ecc.layout = &atmel_pmecc_oobinfo;
946 dev_err(host->dev, "Unsupported page size for PMECC, use Software ECC\n");
948 /* page size not handled by HW ECC */
949 /* switching back to soft ECC */
950 nand->ecc.mode = NAND_ECC_SOFT;
951 nand->ecc.read_page = NULL;
952 nand->ecc.postpad = 0;
953 nand->ecc.prepad = 0;
958 /* Allocate data for PMECC computation */
959 if (pmecc_data_alloc(host)) {
960 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
964 nand->options |= NAND_NO_SUBPAGE_WRITE;
965 nand->ecc.read_page = atmel_nand_pmecc_read_page;
966 nand->ecc.write_page = atmel_nand_pmecc_write_page;
967 nand->ecc.strength = cap;
969 /* Check the PMECC ip version */
970 host->pmecc_version = pmecc_readl(host->pmerrloc, version);
971 dev_dbg(host->dev, "PMECC IP version is: %x\n", host->pmecc_version);
973 atmel_pmecc_core_init(mtd);
980 /* oob layout for large page size
981 * bad block info is on bytes 0 and 1
982 * the bytes have to be consecutives to avoid
983 * several NAND_CMD_RNDOUT during read
985 static struct nand_ecclayout atmel_oobinfo_large = {
987 .eccpos = {60, 61, 62, 63},
993 /* oob layout for small page size
994 * bad block info is on bytes 4 and 5
995 * the bytes have to be consecutives to avoid
996 * several NAND_CMD_RNDOUT during read
998 static struct nand_ecclayout atmel_oobinfo_small = {
1000 .eccpos = {0, 1, 2, 3},
1009 * function called after a write
1011 * mtd: MTD block structure
1012 * dat: raw data (unused)
1013 * ecc_code: buffer for ECC
1015 static int atmel_nand_calculate(struct mtd_info *mtd,
1016 const u_char *dat, unsigned char *ecc_code)
1018 unsigned int ecc_value;
1020 /* get the first 2 ECC bytes */
1021 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
1023 ecc_code[0] = ecc_value & 0xFF;
1024 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1026 /* get the last 2 ECC bytes */
1027 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
1029 ecc_code[2] = ecc_value & 0xFF;
1030 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1036 * HW ECC read page function
1038 * mtd: mtd info structure
1039 * chip: nand chip info structure
1040 * buf: buffer to store read data
1041 * oob_required: caller expects OOB data read to chip->oob_poi
1043 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1044 uint8_t *buf, int oob_required, int page)
1046 int eccsize = chip->ecc.size;
1047 int eccbytes = chip->ecc.bytes;
1048 uint32_t *eccpos = chip->ecc.layout->eccpos;
1050 uint8_t *oob = chip->oob_poi;
1055 chip->read_buf(mtd, p, eccsize);
1057 /* move to ECC position if needed */
1058 if (eccpos[0] != 0) {
1059 /* This only works on large pages
1060 * because the ECC controller waits for
1061 * NAND_CMD_RNDOUTSTART after the
1063 * anyway, for small pages, the eccpos[0] == 0
1065 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1066 mtd->writesize + eccpos[0], -1);
1069 /* the ECC controller needs to read the ECC just after the data */
1070 ecc_pos = oob + eccpos[0];
1071 chip->read_buf(mtd, ecc_pos, eccbytes);
1073 /* check if there's an error */
1074 stat = chip->ecc.correct(mtd, p, oob, NULL);
1077 mtd->ecc_stats.failed++;
1079 mtd->ecc_stats.corrected += stat;
1081 /* get back to oob start (end of page) */
1082 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1085 chip->read_buf(mtd, oob, mtd->oobsize);
1093 * function called after a read
1095 * mtd: MTD block structure
1096 * dat: raw data read from the chip
1097 * read_ecc: ECC from the chip (unused)
1100 * Detect and correct a 1 bit error for a page
1102 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1103 u_char *read_ecc, u_char *isnull)
1105 struct nand_chip *nand_chip = mtd->priv;
1106 unsigned int ecc_status;
1107 unsigned int ecc_word, ecc_bit;
1109 /* get the status from the Status Register */
1110 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1112 /* if there's no error */
1113 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1116 /* get error bit offset (4 bits) */
1117 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1118 /* get word address (12 bits) */
1119 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1122 /* if there are multiple errors */
1123 if (ecc_status & ATMEL_ECC_MULERR) {
1124 /* check if it is a freshly erased block
1125 * (filled with 0xff) */
1126 if ((ecc_bit == ATMEL_ECC_BITADDR)
1127 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1128 /* the block has just been erased, return OK */
1131 /* it doesn't seems to be a freshly
1133 * We can't correct so many errors */
1134 dev_warn(host->dev, "atmel_nand : multiple errors detected."
1135 " Unable to correct.\n");
1139 /* if there's a single bit error : we can correct it */
1140 if (ecc_status & ATMEL_ECC_ECCERR) {
1141 /* there's nothing much to do here.
1142 * the bit error is on the ECC itself.
1144 dev_warn(host->dev, "atmel_nand : one bit error on ECC code."
1145 " Nothing to correct\n");
1149 dev_warn(host->dev, "atmel_nand : one bit error on data."
1150 " (word offset in the page :"
1151 " 0x%x bit offset : 0x%x)\n",
1153 /* correct the error */
1154 if (nand_chip->options & NAND_BUSWIDTH_16) {
1156 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1159 dat[ecc_word] ^= (1 << ecc_bit);
1161 dev_warn(host->dev, "atmel_nand : error corrected\n");
1166 * Enable HW ECC : unused on most chips
1168 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1172 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1174 nand->ecc.mode = NAND_ECC_HW;
1175 nand->ecc.calculate = atmel_nand_calculate;
1176 nand->ecc.correct = atmel_nand_correct;
1177 nand->ecc.hwctl = atmel_nand_hwctl;
1178 nand->ecc.read_page = atmel_nand_read_page;
1179 nand->ecc.bytes = 4;
1181 if (nand->ecc.mode == NAND_ECC_HW) {
1182 /* ECC is calculated for the whole page (1 step) */
1183 nand->ecc.size = mtd->writesize;
1185 /* set ECC page size and oob layout */
1186 switch (mtd->writesize) {
1188 nand->ecc.layout = &atmel_oobinfo_small;
1189 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1190 ATMEL_ECC_PAGESIZE_528);
1193 nand->ecc.layout = &atmel_oobinfo_large;
1194 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1195 ATMEL_ECC_PAGESIZE_1056);
1198 nand->ecc.layout = &atmel_oobinfo_large;
1199 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1200 ATMEL_ECC_PAGESIZE_2112);
1203 nand->ecc.layout = &atmel_oobinfo_large;
1204 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1205 ATMEL_ECC_PAGESIZE_4224);
1208 /* page size not handled by HW ECC */
1209 /* switching back to soft ECC */
1210 nand->ecc.mode = NAND_ECC_SOFT;
1211 nand->ecc.calculate = NULL;
1212 nand->ecc.correct = NULL;
1213 nand->ecc.hwctl = NULL;
1214 nand->ecc.read_page = NULL;
1215 nand->ecc.postpad = 0;
1216 nand->ecc.prepad = 0;
1217 nand->ecc.bytes = 0;
1225 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1227 #endif /* CONFIG_ATMEL_NAND_HWECC */
1229 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1230 int cmd, unsigned int ctrl)
1232 struct nand_chip *this = mtd->priv;
1234 if (ctrl & NAND_CTRL_CHANGE) {
1235 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1236 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1237 | CONFIG_SYS_NAND_MASK_CLE);
1239 if (ctrl & NAND_CLE)
1240 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1241 if (ctrl & NAND_ALE)
1242 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1244 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1245 gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
1247 this->IO_ADDR_W = (void *) IO_ADDR_W;
1250 if (cmd != NAND_CMD_NONE)
1251 writeb(cmd, this->IO_ADDR_W);
1254 #ifdef CONFIG_SYS_NAND_READY_PIN
1255 static int at91_nand_ready(struct mtd_info *mtd)
1257 return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
1261 #ifdef CONFIG_SPL_BUILD
1262 /* The following code is for SPL */
1263 static nand_info_t mtd;
1264 static struct nand_chip nand_chip;
1266 static int nand_command(int block, int page, uint32_t offs, u8 cmd)
1268 struct nand_chip *this = mtd.priv;
1269 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1270 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1271 unsigned int ctrl) = this->cmd_ctrl;
1273 while (!this->dev_ready(&mtd))
1276 if (cmd == NAND_CMD_READOOB) {
1277 offs += CONFIG_SYS_NAND_PAGE_SIZE;
1278 cmd = NAND_CMD_READ0;
1281 hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1283 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1286 hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1287 hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE);
1288 hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE);
1289 hwctrl(&mtd, ((page_addr >> 8) & 0xff), NAND_CTRL_ALE);
1290 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1291 hwctrl(&mtd, (page_addr >> 16) & 0x0f, NAND_CTRL_ALE);
1293 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1295 hwctrl(&mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1296 hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
1298 while (!this->dev_ready(&mtd))
1304 static int nand_is_bad_block(int block)
1306 struct nand_chip *this = mtd.priv;
1308 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
1310 if (this->options & NAND_BUSWIDTH_16) {
1311 if (readw(this->IO_ADDR_R) != 0xffff)
1314 if (readb(this->IO_ADDR_R) != 0xff)
1321 #ifdef CONFIG_SPL_NAND_ECC
1322 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
1323 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
1324 CONFIG_SYS_NAND_ECCSIZE)
1325 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
1327 static int nand_read_page(int block, int page, void *dst)
1329 struct nand_chip *this = mtd.priv;
1330 u_char ecc_calc[ECCTOTAL];
1331 u_char ecc_code[ECCTOTAL];
1332 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
1333 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
1334 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
1335 int eccsteps = ECCSTEPS;
1338 nand_command(block, page, 0, NAND_CMD_READ0);
1340 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1341 if (this->ecc.mode != NAND_ECC_SOFT)
1342 this->ecc.hwctl(&mtd, NAND_ECC_READ);
1343 this->read_buf(&mtd, p, eccsize);
1344 this->ecc.calculate(&mtd, p, &ecc_calc[i]);
1346 this->read_buf(&mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
1348 for (i = 0; i < ECCTOTAL; i++)
1349 ecc_code[i] = oob_data[nand_ecc_pos[i]];
1351 eccsteps = ECCSTEPS;
1354 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1355 this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]);
1360 int spl_nand_erase_one(int block, int page)
1362 struct nand_chip *this = mtd.priv;
1363 void (*hwctrl)(struct mtd_info *mtd, int cmd,
1364 unsigned int ctrl) = this->cmd_ctrl;
1367 if (nand_chip.select_chip)
1368 nand_chip.select_chip(&mtd, 0);
1370 page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
1371 hwctrl(&mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1373 hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1374 hwctrl(&mtd, ((page_addr >> 8) & 0xff),
1375 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1376 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
1377 /* One more address cycle for devices > 128MiB */
1378 hwctrl(&mtd, (page_addr >> 16) & 0x0f,
1379 NAND_CTRL_ALE | NAND_CTRL_CHANGE);
1382 hwctrl(&mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1385 while (!this->dev_ready(&mtd))
1393 static int nand_read_page(int block, int page, void *dst)
1395 struct nand_chip *this = mtd.priv;
1397 nand_command(block, page, 0, NAND_CMD_READ0);
1398 atmel_nand_pmecc_read_page(&mtd, this, dst, 0, page);
1402 #endif /* CONFIG_SPL_NAND_ECC */
1404 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
1406 unsigned int block, lastblock;
1409 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
1410 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
1411 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
1413 while (block <= lastblock) {
1414 if (!nand_is_bad_block(block)) {
1415 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
1416 nand_read_page(block, page, dst);
1417 dst += CONFIG_SYS_NAND_PAGE_SIZE;
1432 int at91_nand_wait_ready(struct mtd_info *mtd)
1434 struct nand_chip *this = mtd->priv;
1436 udelay(this->chip_delay);
1441 int board_nand_init(struct nand_chip *nand)
1445 nand->ecc.mode = NAND_ECC_SOFT;
1446 #ifdef CONFIG_SYS_NAND_DBW_16
1447 nand->options = NAND_BUSWIDTH_16;
1448 nand->read_buf = nand_read_buf16;
1450 nand->read_buf = nand_read_buf;
1452 nand->cmd_ctrl = at91_nand_hwcontrol;
1453 #ifdef CONFIG_SYS_NAND_READY_PIN
1454 nand->dev_ready = at91_nand_ready;
1456 nand->dev_ready = at91_nand_wait_ready;
1458 nand->chip_delay = 20;
1460 #ifdef CONFIG_ATMEL_NAND_HWECC
1461 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1462 ret = atmel_pmecc_nand_init_params(nand, &mtd);
1469 void nand_init(void)
1471 mtd.writesize = CONFIG_SYS_NAND_PAGE_SIZE;
1472 mtd.oobsize = CONFIG_SYS_NAND_OOBSIZE;
1473 mtd.priv = &nand_chip;
1474 nand_chip.IO_ADDR_R = (void __iomem *)CONFIG_SYS_NAND_BASE;
1475 nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
1476 board_nand_init(&nand_chip);
1478 #ifdef CONFIG_SPL_NAND_ECC
1479 if (nand_chip.ecc.mode == NAND_ECC_SOFT) {
1480 nand_chip.ecc.calculate = nand_calculate_ecc;
1481 nand_chip.ecc.correct = nand_correct_data;
1485 if (nand_chip.select_chip)
1486 nand_chip.select_chip(&mtd, 0);
1489 void nand_deselect(void)
1491 if (nand_chip.select_chip)
1492 nand_chip.select_chip(&mtd, -1);
1497 #ifndef CONFIG_SYS_NAND_BASE_LIST
1498 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1500 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1501 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1503 int atmel_nand_chip_init(int devnum, ulong base_addr)
1506 struct mtd_info *mtd = &nand_info[devnum];
1507 struct nand_chip *nand = &nand_chip[devnum];
1510 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
1512 #ifdef CONFIG_NAND_ECC_BCH
1513 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1515 nand->ecc.mode = NAND_ECC_SOFT;
1517 #ifdef CONFIG_SYS_NAND_DBW_16
1518 nand->options = NAND_BUSWIDTH_16;
1520 nand->cmd_ctrl = at91_nand_hwcontrol;
1521 #ifdef CONFIG_SYS_NAND_READY_PIN
1522 nand->dev_ready = at91_nand_ready;
1524 nand->chip_delay = 75;
1526 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1530 #ifdef CONFIG_ATMEL_NAND_HWECC
1531 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1532 ret = atmel_pmecc_nand_init_params(nand, mtd);
1534 ret = atmel_hwecc_nand_init_param(nand, mtd);
1540 ret = nand_scan_tail(mtd);
1542 nand_register(devnum);
1547 void board_nand_init(void)
1550 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1551 if (atmel_nand_chip_init(i, base_addr[i]))
1552 dev_err(host->dev, "atmel_nand: Fail to initialize #%d chip",
1555 #endif /* CONFIG_SPL_BUILD */