2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian@popies.net>
4 * Lead Tech Design <www.leadtechdesign.com>
6 * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
8 * Add Programmable Multibit ECC support for various AT91 SoC
9 * (C) Copyright 2012 ATMEL, Hong Xu
11 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/at91_pio.h>
23 #ifdef CONFIG_ATMEL_NAND_HWECC
25 /* Register access macros */
26 #define ecc_readl(add, reg) \
27 readl(AT91_BASE_SYS + add + ATMEL_ECC_##reg)
28 #define ecc_writel(add, reg, value) \
29 writel((value), AT91_BASE_SYS + add + ATMEL_ECC_##reg)
31 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
33 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
35 struct atmel_nand_host {
36 struct pmecc_regs __iomem *pmecc;
37 struct pmecc_errloc_regs __iomem *pmerrloc;
38 void __iomem *pmecc_rom_base;
41 u16 pmecc_sector_size;
42 u32 pmecc_index_table_offset;
44 int pmecc_bytes_per_sector;
45 int pmecc_sector_number;
46 int pmecc_degree; /* Degree of remainders */
47 int pmecc_cw_len; /* Length of codeword */
49 /* lookup table for alpha_to and index_of */
50 void __iomem *pmecc_alpha_to;
51 void __iomem *pmecc_index_of;
53 /* data for pmecc computation */
55 int16_t *pmecc_partial_syn;
57 int16_t *pmecc_lmu; /* polynomal order */
63 static struct atmel_nand_host pmecc_host;
64 static struct nand_ecclayout atmel_pmecc_oobinfo;
67 * Return number of ecc bytes per sector according to sector size and
68 * correction capability
70 * Following table shows what at91 PMECC supported:
71 * Correction Capability Sector_512_bytes Sector_1024_bytes
72 * ===================== ================ =================
73 * 2-bits 4-bytes 4-bytes
74 * 4-bits 7-bytes 7-bytes
75 * 8-bits 13-bytes 14-bytes
76 * 12-bits 20-bytes 21-bytes
77 * 24-bits 39-bytes 42-bytes
79 static int pmecc_get_ecc_bytes(int cap, int sector_size)
81 int m = 12 + sector_size / 512;
82 return (m * cap + 7) / 8;
85 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
86 int oobsize, int ecc_len)
90 layout->eccbytes = ecc_len;
92 /* ECC will occupy the last ecc_len bytes continuously */
93 for (i = 0; i < ecc_len; i++)
94 layout->eccpos[i] = oobsize - ecc_len + i;
96 layout->oobfree[0].offset = 2;
97 layout->oobfree[0].length =
98 oobsize - ecc_len - layout->oobfree[0].offset;
101 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
105 table_size = host->pmecc_sector_size == 512 ?
106 PMECC_INDEX_TABLE_SIZE_512 : PMECC_INDEX_TABLE_SIZE_1024;
108 /* the ALPHA lookup table is right behind the INDEX lookup table. */
109 return host->pmecc_rom_base + host->pmecc_index_table_offset +
110 table_size * sizeof(int16_t);
113 static void pmecc_data_free(struct atmel_nand_host *host)
115 free(host->pmecc_partial_syn);
116 free(host->pmecc_si);
117 free(host->pmecc_lmu);
118 free(host->pmecc_smu);
119 free(host->pmecc_mu);
120 free(host->pmecc_dmu);
121 free(host->pmecc_delta);
124 static int pmecc_data_alloc(struct atmel_nand_host *host)
126 const int cap = host->pmecc_corr_cap;
129 size = (2 * cap + 1) * sizeof(int16_t);
130 host->pmecc_partial_syn = malloc(size);
131 host->pmecc_si = malloc(size);
132 host->pmecc_lmu = malloc((cap + 1) * sizeof(int16_t));
133 host->pmecc_smu = malloc((cap + 2) * size);
135 size = (cap + 1) * sizeof(int);
136 host->pmecc_mu = malloc(size);
137 host->pmecc_dmu = malloc(size);
138 host->pmecc_delta = malloc(size);
140 if (host->pmecc_partial_syn &&
150 pmecc_data_free(host);
155 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
157 struct nand_chip *nand_chip = mtd->priv;
158 struct atmel_nand_host *host = nand_chip->priv;
162 /* Fill odd syndromes */
163 for (i = 0; i < host->pmecc_corr_cap; i++) {
164 value = readl(&host->pmecc->rem_port[sector].rem[i / 2]);
168 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
172 static void pmecc_substitute(struct mtd_info *mtd)
174 struct nand_chip *nand_chip = mtd->priv;
175 struct atmel_nand_host *host = nand_chip->priv;
176 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
177 int16_t __iomem *index_of = host->pmecc_index_of;
178 int16_t *partial_syn = host->pmecc_partial_syn;
179 const int cap = host->pmecc_corr_cap;
183 /* si[] is a table that holds the current syndrome value,
184 * an element of that table belongs to the field
188 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
190 /* Computation 2t syndromes based on S(x) */
192 for (i = 1; i < 2 * cap; i += 2) {
193 for (j = 0; j < host->pmecc_degree; j++) {
194 if (partial_syn[i] & (0x1 << j))
195 si[i] = readw(alpha_to + i * j) ^ si[i];
198 /* Even syndrome = (Odd syndrome) ** 2 */
199 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
205 tmp = readw(index_of + si[j]);
206 tmp = (tmp * 2) % host->pmecc_cw_len;
207 si[i] = readw(alpha_to + tmp);
213 * This function defines a Berlekamp iterative procedure for
214 * finding the value of the error location polynomial.
215 * The input is si[], initialize by pmecc_substitute().
216 * The output is smu[][].
218 * This function is written according to chip datasheet Chapter:
219 * Find the Error Location Polynomial Sigma(x) of Section:
220 * Programmable Multibit ECC Control (PMECC).
222 static void pmecc_get_sigma(struct mtd_info *mtd)
224 struct nand_chip *nand_chip = mtd->priv;
225 struct atmel_nand_host *host = nand_chip->priv;
227 int16_t *lmu = host->pmecc_lmu;
228 int16_t *si = host->pmecc_si;
229 int *mu = host->pmecc_mu;
230 int *dmu = host->pmecc_dmu; /* Discrepancy */
231 int *delta = host->pmecc_delta; /* Delta order */
232 int cw_len = host->pmecc_cw_len;
233 const int16_t cap = host->pmecc_corr_cap;
234 const int num = 2 * cap + 1;
235 int16_t __iomem *index_of = host->pmecc_index_of;
236 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
238 uint32_t dmu_0_count, tmp;
239 int16_t *smu = host->pmecc_smu;
241 /* index of largest delta */
246 /* Init the Sigma(x) */
247 memset(smu, 0, sizeof(int16_t) * ARRAY_SIZE(smu));
258 /* discrepancy set to 1 */
260 /* polynom order set to 0 */
262 /* delta[0] = (mu[0] * 2 - lmu[0]) >> 1; */
269 /* Sigma(x) set to 1 */
272 /* discrepancy set to S1 */
275 /* polynom order set to 0 */
278 /* delta[1] = (mu[1] * 2 - lmu[1]) >> 1; */
281 for (i = 1; i <= cap; i++) {
283 /* Begin Computing Sigma (Mu+1) and L(mu) */
284 /* check if discrepancy is set to 0 */
288 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
289 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
294 if (dmu_0_count == tmp) {
295 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
296 smu[(cap + 1) * num + j] =
299 lmu[cap + 1] = lmu[i];
304 for (j = 0; j <= lmu[i] >> 1; j++)
305 smu[(i + 1) * num + j] = smu[i * num + j];
307 /* copy previous polynom order to the next */
312 /* find largest delta with dmu != 0 */
313 for (j = 0; j < i; j++) {
314 if ((dmu[j]) && (delta[j] > largest)) {
320 /* compute difference */
321 diff = (mu[i] - mu[ro]);
323 /* Compute degree of the new smu polynomial */
324 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
327 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
329 /* Init smu[i+1] with 0 */
330 for (k = 0; k < num; k++)
331 smu[(i + 1) * num + k] = 0;
333 /* Compute smu[i+1] */
334 for (k = 0; k <= lmu[ro] >> 1; k++) {
337 if (!(smu[ro * num + k] && dmu[i]))
339 a = readw(index_of + dmu[i]);
340 b = readw(index_of + dmu[ro]);
341 c = readw(index_of + smu[ro * num + k]);
342 tmp = a + (cw_len - b) + c;
343 a = readw(alpha_to + tmp % cw_len);
344 smu[(i + 1) * num + (k + diff)] = a;
347 for (k = 0; k <= lmu[i] >> 1; k++)
348 smu[(i + 1) * num + k] ^= smu[i * num + k];
351 /* End Computing Sigma (Mu+1) and L(mu) */
352 /* In either case compute delta */
353 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
355 /* Do not compute discrepancy for the last iteration */
359 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
362 dmu[i + 1] = si[tmp + 3];
363 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
366 smu[(i + 1) * num + k]);
367 b = si[2 * (i - 1) + 3 - k];
368 c = readw(index_of + b);
371 dmu[i + 1] = readw(alpha_to + tmp) ^
378 static int pmecc_err_location(struct mtd_info *mtd)
380 struct nand_chip *nand_chip = mtd->priv;
381 struct atmel_nand_host *host = nand_chip->priv;
382 const int cap = host->pmecc_corr_cap;
383 const int num = 2 * cap + 1;
384 int sector_size = host->pmecc_sector_size;
385 int err_nbr = 0; /* number of error */
386 int roots_nbr; /* number of roots */
389 int16_t *smu = host->pmecc_smu;
390 int timeout = PMECC_MAX_TIMEOUT_US;
392 writel(PMERRLOC_DISABLE, &host->pmerrloc->eldis);
394 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
395 writel(smu[(cap + 1) * num + i], &host->pmerrloc->sigma[i]);
399 val = PMERRLOC_ELCFG_NUM_ERRORS(err_nbr - 1);
400 if (sector_size == 1024)
401 val |= PMERRLOC_ELCFG_SECTOR_1024;
403 writel(val, &host->pmerrloc->elcfg);
404 writel(sector_size * 8 + host->pmecc_degree * cap,
405 &host->pmerrloc->elen);
408 if (readl(&host->pmerrloc->elisr) & PMERRLOC_CALC_DONE)
415 printk(KERN_ERR "atmel_nand : Timeout to calculate PMECC error location\n");
419 roots_nbr = (readl(&host->pmerrloc->elisr) & PMERRLOC_ERR_NUM_MASK)
421 /* Number of roots == degree of smu hence <= cap */
422 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
425 /* Number of roots does not match the degree of smu
426 * unable to correct error */
430 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
431 int sector_num, int extra_bytes, int err_nbr)
433 struct nand_chip *nand_chip = mtd->priv;
434 struct atmel_nand_host *host = nand_chip->priv;
436 int byte_pos, bit_pos, sector_size, pos;
440 sector_size = host->pmecc_sector_size;
443 tmp = readl(&host->pmerrloc->el[i]) - 1;
447 if (byte_pos >= (sector_size + extra_bytes))
448 BUG(); /* should never happen */
450 if (byte_pos < sector_size) {
451 err_byte = *(buf + byte_pos);
452 *(buf + byte_pos) ^= (1 << bit_pos);
454 pos = sector_num * host->pmecc_sector_size + byte_pos;
455 printk(KERN_INFO "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
456 pos, bit_pos, err_byte, *(buf + byte_pos));
458 /* Bit flip in OOB area */
459 tmp = sector_num * host->pmecc_bytes_per_sector
460 + (byte_pos - sector_size);
462 ecc[tmp] ^= (1 << bit_pos);
464 pos = tmp + nand_chip->ecc.layout->eccpos[0];
465 printk(KERN_INFO "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
466 pos, bit_pos, err_byte, ecc[tmp]);
476 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
479 struct nand_chip *nand_chip = mtd->priv;
480 struct atmel_nand_host *host = nand_chip->priv;
481 int i, err_nbr, eccbytes;
484 eccbytes = nand_chip->ecc.bytes;
485 for (i = 0; i < eccbytes; i++)
488 /* Erased page, return OK */
492 for (i = 0; i < host->pmecc_sector_number; i++) {
494 if (pmecc_stat & 0x1) {
495 buf_pos = buf + i * host->pmecc_sector_size;
497 pmecc_gen_syndrome(mtd, i);
498 pmecc_substitute(mtd);
499 pmecc_get_sigma(mtd);
501 err_nbr = pmecc_err_location(mtd);
503 printk(KERN_ERR "PMECC: Too many errors\n");
504 mtd->ecc_stats.failed++;
507 pmecc_correct_data(mtd, buf_pos, ecc, i,
508 host->pmecc_bytes_per_sector, err_nbr);
509 mtd->ecc_stats.corrected += err_nbr;
518 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
519 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
521 struct atmel_nand_host *host = chip->priv;
522 int eccsize = chip->ecc.size;
523 uint8_t *oob = chip->oob_poi;
524 uint32_t *eccpos = chip->ecc.layout->eccpos;
526 int timeout = PMECC_MAX_TIMEOUT_US;
528 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
529 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
530 pmecc_writel(host->pmecc, cfg, ((pmecc_readl(host->pmecc, cfg))
531 & ~PMECC_CFG_WRITE_OP) | PMECC_CFG_AUTO_ENABLE);
533 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
534 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
536 chip->read_buf(mtd, buf, eccsize);
537 chip->read_buf(mtd, oob, mtd->oobsize);
540 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
547 printk(KERN_ERR "atmel_nand : Timeout to read PMECC page\n");
551 stat = pmecc_readl(host->pmecc, isr);
553 if (pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]) != 0)
559 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
560 struct nand_chip *chip, const uint8_t *buf,
563 struct atmel_nand_host *host = chip->priv;
564 uint32_t *eccpos = chip->ecc.layout->eccpos;
566 int timeout = PMECC_MAX_TIMEOUT_US;
568 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
569 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
571 pmecc_writel(host->pmecc, cfg, (pmecc_readl(host->pmecc, cfg) |
572 PMECC_CFG_WRITE_OP) & ~PMECC_CFG_AUTO_ENABLE);
574 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
575 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DATA);
577 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
580 if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
587 printk(KERN_ERR "atmel_nand : Timeout to read PMECC status, fail to write PMECC in oob\n");
591 for (i = 0; i < host->pmecc_sector_number; i++) {
592 for (j = 0; j < host->pmecc_bytes_per_sector; j++) {
595 pos = i * host->pmecc_bytes_per_sector + j;
596 chip->oob_poi[eccpos[pos]] =
597 readb(&host->pmecc->ecc_port[i].ecc[j]);
600 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
605 static void atmel_pmecc_core_init(struct mtd_info *mtd)
607 struct nand_chip *nand_chip = mtd->priv;
608 struct atmel_nand_host *host = nand_chip->priv;
610 struct nand_ecclayout *ecc_layout;
612 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_RST);
613 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_DISABLE);
615 switch (host->pmecc_corr_cap) {
617 val = PMECC_CFG_BCH_ERR2;
620 val = PMECC_CFG_BCH_ERR4;
623 val = PMECC_CFG_BCH_ERR8;
626 val = PMECC_CFG_BCH_ERR12;
629 val = PMECC_CFG_BCH_ERR24;
633 if (host->pmecc_sector_size == 512)
634 val |= PMECC_CFG_SECTOR512;
635 else if (host->pmecc_sector_size == 1024)
636 val |= PMECC_CFG_SECTOR1024;
638 switch (host->pmecc_sector_number) {
640 val |= PMECC_CFG_PAGE_1SECTOR;
643 val |= PMECC_CFG_PAGE_2SECTORS;
646 val |= PMECC_CFG_PAGE_4SECTORS;
649 val |= PMECC_CFG_PAGE_8SECTORS;
653 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
654 | PMECC_CFG_AUTO_DISABLE);
655 pmecc_writel(host->pmecc, cfg, val);
657 ecc_layout = nand_chip->ecc.layout;
658 pmecc_writel(host->pmecc, sarea, mtd->oobsize - 1);
659 pmecc_writel(host->pmecc, saddr, ecc_layout->eccpos[0]);
660 pmecc_writel(host->pmecc, eaddr,
661 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
662 /* See datasheet about PMECC Clock Control Register */
663 pmecc_writel(host->pmecc, clk, PMECC_CLK_133MHZ);
664 pmecc_writel(host->pmecc, idr, 0xff);
665 pmecc_writel(host->pmecc, ctrl, PMECC_CTRL_ENABLE);
668 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
670 * get_onfi_ecc_param - Get ECC requirement from ONFI parameters
671 * @ecc_bits: store the ONFI ECC correct bits capbility
672 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
674 * Returns -1 if ONFI parameters is not supported. In this case @ecc_bits,
675 * @sector_size are initialize to 0.
676 * Return 0 if success to get the ECC requirement.
678 static int get_onfi_ecc_param(struct nand_chip *chip,
679 int *ecc_bits, int *sector_size)
681 *ecc_bits = *sector_size = 0;
683 if (chip->onfi_params.ecc_bits == 0xff)
684 /* TODO: the sector_size and ecc_bits need to be find in
685 * extended ecc parameter, currently we don't support it.
689 *ecc_bits = chip->onfi_params.ecc_bits;
691 /* The default sector size (ecc codeword size) is 512 */
698 * pmecc_choose_ecc - Get ecc requirement from ONFI parameters. If
699 * pmecc_corr_cap or pmecc_sector_size is 0, then set it as
700 * ONFI ECC parameters.
701 * @host: point to an atmel_nand_host structure.
702 * if host->pmecc_corr_cap is 0 then set it as the ONFI ecc_bits.
703 * if host->pmecc_sector_size is 0 then set it as the ONFI sector_size.
704 * @chip: point to an nand_chip structure.
705 * @cap: store the ONFI ECC correct bits capbility
706 * @sector_size: in how many bytes that ONFI require to correct @ecc_bits
708 * Return 0 if success. otherwise return the error code.
710 static int pmecc_choose_ecc(struct atmel_nand_host *host,
711 struct nand_chip *chip,
712 int *cap, int *sector_size)
714 /* Get ECC requirement from ONFI parameters */
715 *cap = *sector_size = 0;
716 if (chip->onfi_version) {
717 if (!get_onfi_ecc_param(chip, cap, sector_size)) {
718 MTDDEBUG(MTD_DEBUG_LEVEL1, "ONFI params, minimum required ECC: %d bits in %d bytes\n",
721 dev_info(host->dev, "NAND chip ECC reqirement is in Extended ONFI parameter, we don't support yet.\n");
724 dev_info(host->dev, "NAND chip is not ONFI compliant, assume ecc_bits is 2 in 512 bytes");
726 if (*cap == 0 && *sector_size == 0) {
727 /* Non-ONFI compliant or use extended ONFI parameters */
732 /* If head file doesn't specify then use the one in ONFI parameters */
733 if (host->pmecc_corr_cap == 0) {
734 /* use the most fitable ecc bits (the near bigger one ) */
736 host->pmecc_corr_cap = 2;
738 host->pmecc_corr_cap = 4;
740 host->pmecc_corr_cap = 8;
742 host->pmecc_corr_cap = 12;
744 host->pmecc_corr_cap = 24;
748 if (host->pmecc_sector_size == 0) {
749 /* use the most fitable sector size (the near smaller one ) */
750 if (*sector_size >= 1024)
751 host->pmecc_sector_size = 1024;
752 else if (*sector_size >= 512)
753 host->pmecc_sector_size = 512;
761 static int atmel_pmecc_nand_init_params(struct nand_chip *nand,
762 struct mtd_info *mtd)
764 struct atmel_nand_host *host;
765 int cap, sector_size;
767 host = nand->priv = &pmecc_host;
769 nand->ecc.mode = NAND_ECC_HW;
770 nand->ecc.calculate = NULL;
771 nand->ecc.correct = NULL;
772 nand->ecc.hwctl = NULL;
774 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
775 host->pmecc_corr_cap = host->pmecc_sector_size = 0;
777 #ifdef CONFIG_PMECC_CAP
778 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
780 #ifdef CONFIG_PMECC_SECTOR_SIZE
781 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
783 /* Get ECC requirement of ONFI parameters. And if CONFIG_PMECC_CAP or
784 * CONFIG_PMECC_SECTOR_SIZE not defined, then use ecc_bits, sector_size
787 if (pmecc_choose_ecc(host, nand, &cap, §or_size)) {
788 dev_err(host->dev, "The NAND flash's ECC requirement(ecc_bits: %d, sector_size: %d) are not support!",
793 if (cap > host->pmecc_corr_cap)
794 dev_info(host->dev, "WARNING: Using different ecc correct bits(%d bit) from Nand ONFI ECC reqirement (%d bit).\n",
795 host->pmecc_corr_cap, cap);
796 if (sector_size < host->pmecc_sector_size)
797 dev_info(host->dev, "WARNING: Using different ecc correct sector size (%d bytes) from Nand ONFI ECC reqirement (%d bytes).\n",
798 host->pmecc_sector_size, sector_size);
799 #else /* CONFIG_SYS_NAND_ONFI_DETECTION */
800 host->pmecc_corr_cap = CONFIG_PMECC_CAP;
801 host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE;
804 cap = host->pmecc_corr_cap;
805 sector_size = host->pmecc_sector_size;
807 /* TODO: need check whether cap & sector_size is validate */
809 if (host->pmecc_sector_size == 512)
810 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512;
812 host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024;
814 MTDDEBUG(MTD_DEBUG_LEVEL1,
815 "Initialize PMECC params, cap: %d, sector: %d\n",
818 host->pmecc = (struct pmecc_regs __iomem *) ATMEL_BASE_PMECC;
819 host->pmerrloc = (struct pmecc_errloc_regs __iomem *)
821 host->pmecc_rom_base = (void __iomem *) ATMEL_BASE_ROM;
823 /* ECC is calculated for the whole page (1 step) */
824 nand->ecc.size = mtd->writesize;
826 /* set ECC page size and oob layout */
827 switch (mtd->writesize) {
830 host->pmecc_degree = (sector_size == 512) ?
831 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
832 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
833 host->pmecc_sector_number = mtd->writesize / sector_size;
834 host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
836 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
837 host->pmecc_index_of = host->pmecc_rom_base +
838 host->pmecc_index_table_offset;
841 nand->ecc.bytes = host->pmecc_bytes_per_sector *
842 host->pmecc_sector_number;
843 if (nand->ecc.bytes > mtd->oobsize - 2) {
844 printk(KERN_ERR "No room for ECC bytes\n");
847 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
850 nand->ecc.layout = &atmel_pmecc_oobinfo;
855 printk(KERN_ERR "Unsupported page size for PMECC, use Software ECC\n");
857 /* page size not handled by HW ECC */
858 /* switching back to soft ECC */
859 nand->ecc.mode = NAND_ECC_SOFT;
860 nand->ecc.read_page = NULL;
861 nand->ecc.postpad = 0;
862 nand->ecc.prepad = 0;
867 /* Allocate data for PMECC computation */
868 if (pmecc_data_alloc(host)) {
869 dev_err(host->dev, "Cannot allocate memory for PMECC computation!\n");
873 nand->ecc.read_page = atmel_nand_pmecc_read_page;
874 nand->ecc.write_page = atmel_nand_pmecc_write_page;
875 nand->ecc.strength = cap;
877 atmel_pmecc_core_init(mtd);
884 /* oob layout for large page size
885 * bad block info is on bytes 0 and 1
886 * the bytes have to be consecutives to avoid
887 * several NAND_CMD_RNDOUT during read
889 static struct nand_ecclayout atmel_oobinfo_large = {
891 .eccpos = {60, 61, 62, 63},
897 /* oob layout for small page size
898 * bad block info is on bytes 4 and 5
899 * the bytes have to be consecutives to avoid
900 * several NAND_CMD_RNDOUT during read
902 static struct nand_ecclayout atmel_oobinfo_small = {
904 .eccpos = {0, 1, 2, 3},
913 * function called after a write
915 * mtd: MTD block structure
916 * dat: raw data (unused)
917 * ecc_code: buffer for ECC
919 static int atmel_nand_calculate(struct mtd_info *mtd,
920 const u_char *dat, unsigned char *ecc_code)
922 unsigned int ecc_value;
924 /* get the first 2 ECC bytes */
925 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR);
927 ecc_code[0] = ecc_value & 0xFF;
928 ecc_code[1] = (ecc_value >> 8) & 0xFF;
930 /* get the last 2 ECC bytes */
931 ecc_value = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, NPR) & ATMEL_ECC_NPARITY;
933 ecc_code[2] = ecc_value & 0xFF;
934 ecc_code[3] = (ecc_value >> 8) & 0xFF;
940 * HW ECC read page function
942 * mtd: mtd info structure
943 * chip: nand chip info structure
944 * buf: buffer to store read data
945 * oob_required: caller expects OOB data read to chip->oob_poi
947 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
948 uint8_t *buf, int oob_required, int page)
950 int eccsize = chip->ecc.size;
951 int eccbytes = chip->ecc.bytes;
952 uint32_t *eccpos = chip->ecc.layout->eccpos;
954 uint8_t *oob = chip->oob_poi;
959 chip->read_buf(mtd, p, eccsize);
961 /* move to ECC position if needed */
962 if (eccpos[0] != 0) {
963 /* This only works on large pages
964 * because the ECC controller waits for
965 * NAND_CMD_RNDOUTSTART after the
967 * anyway, for small pages, the eccpos[0] == 0
969 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
970 mtd->writesize + eccpos[0], -1);
973 /* the ECC controller needs to read the ECC just after the data */
974 ecc_pos = oob + eccpos[0];
975 chip->read_buf(mtd, ecc_pos, eccbytes);
977 /* check if there's an error */
978 stat = chip->ecc.correct(mtd, p, oob, NULL);
981 mtd->ecc_stats.failed++;
983 mtd->ecc_stats.corrected += stat;
985 /* get back to oob start (end of page) */
986 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
989 chip->read_buf(mtd, oob, mtd->oobsize);
997 * function called after a read
999 * mtd: MTD block structure
1000 * dat: raw data read from the chip
1001 * read_ecc: ECC from the chip (unused)
1004 * Detect and correct a 1 bit error for a page
1006 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1007 u_char *read_ecc, u_char *isnull)
1009 struct nand_chip *nand_chip = mtd->priv;
1010 unsigned int ecc_status;
1011 unsigned int ecc_word, ecc_bit;
1013 /* get the status from the Status Register */
1014 ecc_status = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, SR);
1016 /* if there's no error */
1017 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1020 /* get error bit offset (4 bits) */
1021 ecc_bit = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_BITADDR;
1022 /* get word address (12 bits) */
1023 ecc_word = ecc_readl(CONFIG_SYS_NAND_ECC_BASE, PR) & ATMEL_ECC_WORDADDR;
1026 /* if there are multiple errors */
1027 if (ecc_status & ATMEL_ECC_MULERR) {
1028 /* check if it is a freshly erased block
1029 * (filled with 0xff) */
1030 if ((ecc_bit == ATMEL_ECC_BITADDR)
1031 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1032 /* the block has just been erased, return OK */
1035 /* it doesn't seems to be a freshly
1037 * We can't correct so many errors */
1038 printk(KERN_WARNING "atmel_nand : multiple errors detected."
1039 " Unable to correct.\n");
1043 /* if there's a single bit error : we can correct it */
1044 if (ecc_status & ATMEL_ECC_ECCERR) {
1045 /* there's nothing much to do here.
1046 * the bit error is on the ECC itself.
1048 printk(KERN_WARNING "atmel_nand : one bit error on ECC code."
1049 " Nothing to correct\n");
1053 printk(KERN_WARNING "atmel_nand : one bit error on data."
1054 " (word offset in the page :"
1055 " 0x%x bit offset : 0x%x)\n",
1057 /* correct the error */
1058 if (nand_chip->options & NAND_BUSWIDTH_16) {
1060 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1063 dat[ecc_word] ^= (1 << ecc_bit);
1065 printk(KERN_WARNING "atmel_nand : error corrected\n");
1070 * Enable HW ECC : unused on most chips
1072 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1076 int atmel_hwecc_nand_init_param(struct nand_chip *nand, struct mtd_info *mtd)
1078 nand->ecc.mode = NAND_ECC_HW;
1079 nand->ecc.calculate = atmel_nand_calculate;
1080 nand->ecc.correct = atmel_nand_correct;
1081 nand->ecc.hwctl = atmel_nand_hwctl;
1082 nand->ecc.read_page = atmel_nand_read_page;
1083 nand->ecc.bytes = 4;
1085 if (nand->ecc.mode == NAND_ECC_HW) {
1086 /* ECC is calculated for the whole page (1 step) */
1087 nand->ecc.size = mtd->writesize;
1089 /* set ECC page size and oob layout */
1090 switch (mtd->writesize) {
1092 nand->ecc.layout = &atmel_oobinfo_small;
1093 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1094 ATMEL_ECC_PAGESIZE_528);
1097 nand->ecc.layout = &atmel_oobinfo_large;
1098 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1099 ATMEL_ECC_PAGESIZE_1056);
1102 nand->ecc.layout = &atmel_oobinfo_large;
1103 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1104 ATMEL_ECC_PAGESIZE_2112);
1107 nand->ecc.layout = &atmel_oobinfo_large;
1108 ecc_writel(CONFIG_SYS_NAND_ECC_BASE, MR,
1109 ATMEL_ECC_PAGESIZE_4224);
1112 /* page size not handled by HW ECC */
1113 /* switching back to soft ECC */
1114 nand->ecc.mode = NAND_ECC_SOFT;
1115 nand->ecc.calculate = NULL;
1116 nand->ecc.correct = NULL;
1117 nand->ecc.hwctl = NULL;
1118 nand->ecc.read_page = NULL;
1119 nand->ecc.postpad = 0;
1120 nand->ecc.prepad = 0;
1121 nand->ecc.bytes = 0;
1129 #endif /* CONFIG_ATMEL_NAND_HW_PMECC */
1131 #endif /* CONFIG_ATMEL_NAND_HWECC */
1133 static void at91_nand_hwcontrol(struct mtd_info *mtd,
1134 int cmd, unsigned int ctrl)
1136 struct nand_chip *this = mtd->priv;
1138 if (ctrl & NAND_CTRL_CHANGE) {
1139 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
1140 IO_ADDR_W &= ~(CONFIG_SYS_NAND_MASK_ALE
1141 | CONFIG_SYS_NAND_MASK_CLE);
1143 if (ctrl & NAND_CLE)
1144 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_CLE;
1145 if (ctrl & NAND_ALE)
1146 IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
1148 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
1149 at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
1150 !(ctrl & NAND_NCE));
1152 this->IO_ADDR_W = (void *) IO_ADDR_W;
1155 if (cmd != NAND_CMD_NONE)
1156 writeb(cmd, this->IO_ADDR_W);
1159 #ifdef CONFIG_SYS_NAND_READY_PIN
1160 static int at91_nand_ready(struct mtd_info *mtd)
1162 return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
1166 #ifndef CONFIG_SYS_NAND_BASE_LIST
1167 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
1169 static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
1170 static ulong base_addr[CONFIG_SYS_MAX_NAND_DEVICE] = CONFIG_SYS_NAND_BASE_LIST;
1172 int atmel_nand_chip_init(int devnum, ulong base_addr)
1175 struct mtd_info *mtd = &nand_info[devnum];
1176 struct nand_chip *nand = &nand_chip[devnum];
1179 nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
1181 #ifdef CONFIG_NAND_ECC_BCH
1182 nand->ecc.mode = NAND_ECC_SOFT_BCH;
1184 nand->ecc.mode = NAND_ECC_SOFT;
1186 #ifdef CONFIG_SYS_NAND_DBW_16
1187 nand->options = NAND_BUSWIDTH_16;
1189 nand->cmd_ctrl = at91_nand_hwcontrol;
1190 #ifdef CONFIG_SYS_NAND_READY_PIN
1191 nand->dev_ready = at91_nand_ready;
1193 nand->chip_delay = 20;
1195 ret = nand_scan_ident(mtd, CONFIG_SYS_NAND_MAX_CHIPS, NULL);
1199 #ifdef CONFIG_ATMEL_NAND_HWECC
1200 #ifdef CONFIG_ATMEL_NAND_HW_PMECC
1201 ret = atmel_pmecc_nand_init_params(nand, mtd);
1203 ret = atmel_hwecc_nand_init_param(nand, mtd);
1209 ret = nand_scan_tail(mtd);
1211 nand_register(devnum);
1216 void board_nand_init(void)
1219 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
1220 if (atmel_nand_chip_init(i, base_addr[i]))
1221 printk(KERN_ERR "atmel_nand: Fail to initialize #%d chip",