3 * Konstantin Kozhevnikov, Cogent Embedded
5 * based on nand_spl_simple code
7 * (C) Copyright 2006-2008
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/mtd/nand_ecc.h>
18 static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
19 static struct mtd_info *mtd;
20 static struct nand_chip nand_chip;
22 #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
23 CONFIG_SYS_NAND_ECCSIZE)
24 #define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
28 * NAND command for large page NAND devices (2k)
30 static int nand_command(int block, int page, uint32_t offs,
33 struct nand_chip *this = mtd_to_nand(mtd);
34 int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
35 void (*hwctrl)(struct mtd_info *mtd, int cmd,
36 unsigned int ctrl) = this->cmd_ctrl;
38 while (!this->dev_ready(mtd))
41 /* Emulate NAND_CMD_READOOB */
42 if (cmd == NAND_CMD_READOOB) {
43 offs += CONFIG_SYS_NAND_PAGE_SIZE;
47 /* Begin command latch cycle */
48 hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
50 if (cmd == NAND_CMD_RESET) {
51 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
52 while (!this->dev_ready(mtd))
57 /* Shift the offset from byte addressing to word addressing. */
58 if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
61 /* Set ALE and clear CLE to start address cycle */
63 hwctrl(mtd, offs & 0xff,
64 NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
65 hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
67 if (cmd != NAND_CMD_RNDOUT) {
68 hwctrl(mtd, (page_addr & 0xff),
69 NAND_CTRL_ALE); /* A[19:12] */
70 hwctrl(mtd, ((page_addr >> 8) & 0xff),
71 NAND_CTRL_ALE); /* A[27:20] */
72 #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
73 /* One more address cycle for devices > 128MiB */
74 hwctrl(mtd, (page_addr >> 16) & 0x0f,
75 NAND_CTRL_ALE); /* A[31:28] */
79 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
81 if (cmd == NAND_CMD_READ0) {
82 /* Latch in address */
83 hwctrl(mtd, NAND_CMD_READSTART,
84 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
85 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
88 * Wait a while for the data to be ready
90 while (!this->dev_ready(mtd))
92 } else if (cmd == NAND_CMD_RNDOUT) {
93 hwctrl(mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE |
95 hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
101 static int nand_is_bad_block(int block)
103 struct nand_chip *this = mtd_to_nand(mtd);
105 nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS,
109 * Read one byte (or two if it's a 16 bit chip).
111 if (this->options & NAND_BUSWIDTH_16) {
112 if (readw(this->IO_ADDR_R) != 0xffff)
115 if (readb(this->IO_ADDR_R) != 0xff)
122 static int nand_read_page(int block, int page, void *dst)
124 struct nand_chip *this = mtd_to_nand(mtd);
125 u_char ecc_calc[ECCTOTAL];
126 u_char ecc_code[ECCTOTAL];
127 u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
129 int eccsize = CONFIG_SYS_NAND_ECCSIZE;
130 int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
131 int eccsteps = ECCSTEPS;
133 uint32_t data_pos = 0;
134 uint8_t *oob = &oob_data[0] + nand_ecc_pos[0];
135 uint32_t oob_pos = eccsize * eccsteps + nand_ecc_pos[0];
137 nand_command(block, page, 0, NAND_CMD_READ0);
139 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
140 this->ecc.hwctl(mtd, NAND_ECC_READ);
141 nand_command(block, page, data_pos, NAND_CMD_RNDOUT);
143 this->read_buf(mtd, p, eccsize);
145 nand_command(block, page, oob_pos, NAND_CMD_RNDOUT);
147 this->read_buf(mtd, oob, eccbytes);
148 this->ecc.calculate(mtd, p, &ecc_calc[i]);
155 /* Pick the ECC bytes out of the oob data */
156 for (i = 0; i < ECCTOTAL; i++)
157 ecc_code[i] = oob_data[nand_ecc_pos[i]];
162 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
163 /* No chance to do something with the possible error message
164 * from correct_data(). We just hope that all possible errors
165 * are corrected by this routine.
167 this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
173 int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
175 unsigned int block, lastblock;
176 unsigned int page, page_offset;
179 * offs has to be aligned to a page address!
181 block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
182 lastblock = (offs + size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
183 page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
184 page_offset = offs % CONFIG_SYS_NAND_PAGE_SIZE;
186 while (block <= lastblock) {
187 if (!nand_is_bad_block(block)) {
191 while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
192 nand_read_page(block, page, dst);
194 * When offs is not aligned to page address the
195 * extra offset is copied to dst as well. Copy
196 * the image such that its first byte will be
199 if (unlikely(page_offset)) {
200 memmove(dst, dst + page_offset,
201 CONFIG_SYS_NAND_PAGE_SIZE);
202 dst = (void *)((int)dst - page_offset);
205 dst += CONFIG_SYS_NAND_PAGE_SIZE;
220 /* nand_init() - initialize data to make nand usable by SPL */
224 * Init board specific nand support
226 mtd = &nand_chip.mtd;
227 nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W =
228 (void __iomem *)CONFIG_SYS_NAND_BASE;
229 board_nand_init(&nand_chip);
231 if (nand_chip.select_chip)
232 nand_chip.select_chip(mtd, 0);
234 /* NAND chip may require reset after power-on */
235 nand_command(0, 0, 0, NAND_CMD_RESET);
238 /* Unselect after operation */
239 void nand_deselect(void)
241 if (nand_chip.select_chip)
242 nand_chip.select_chip(mtd, -1);