1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2013 - 2015 Xilinx, Inc.
5 * Xilinx Zynq SD Host Controller Interface
12 #include "mmc_private.h"
13 #include <dm/device_compat.h>
14 #include <linux/err.h>
15 #include <linux/libfdt.h>
18 #include <zynqmp_tap_delay.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 struct arasan_sdhci_plat {
23 struct mmc_config cfg;
28 struct arasan_sdhci_priv {
29 struct sdhci_host *host;
35 #if defined(CONFIG_ARCH_ZYNQMP)
36 #define MMC_HS200_BUS_SPEED 5
38 static const u8 mode2timing[] = {
39 [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
40 [MMC_HS] = HIGH_SPEED_BUS_SPEED,
41 [SD_HS] = HIGH_SPEED_BUS_SPEED,
42 [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
43 [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
44 [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
45 [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
46 [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
47 [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
48 [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
49 [MMC_HS_200] = MMC_HS200_BUS_SPEED,
52 #define SDHCI_TUNING_LOOP_COUNT 40
54 static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
57 unsigned long timeout;
59 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
60 clk &= ~(SDHCI_CLOCK_CARD_EN);
61 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
64 zynqmp_dll_reset(deviceid);
68 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
69 & SDHCI_CLOCK_INT_STABLE)) {
71 dev_err(mmc_dev(host->mmc),
72 ": Internal clock never stabilised.\n");
79 clk |= SDHCI_CLOCK_CARD_EN;
80 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
83 static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
88 struct sdhci_host *host;
89 struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
90 char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
93 debug("%s\n", __func__);
96 deviceid = priv->deviceid;
98 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
99 ctrl |= SDHCI_CTRL_EXEC_TUNING;
100 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
104 arasan_zynqmp_dll_reset(host, deviceid);
106 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
107 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
111 cmd.resp_type = MMC_RSP_R1;
116 data.flags = MMC_DATA_READ;
118 if (tuning_loop_counter-- == 0)
121 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
123 data.blocksize = 128;
125 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
128 sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
129 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
131 mmc_send_cmd(mmc, &cmd, NULL);
132 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
134 if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
137 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
139 if (tuning_loop_counter < 0) {
140 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
141 sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
144 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
145 printf("%s:Tuning failed\n", __func__);
150 arasan_zynqmp_dll_reset(host, deviceid);
152 /* Enable only interrupts served by the SD controller */
153 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
155 /* Mask all sdhci interrupt sources */
156 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
161 static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
163 struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
164 struct mmc *mmc = (struct mmc *)host->mmc;
167 uhsmode = mode2timing[mmc->selected_mode];
169 if (uhsmode >= UHS_SDR25_BUS_SPEED)
170 arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
174 static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
176 struct mmc *mmc = (struct mmc *)host->mmc;
182 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
183 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
184 reg |= SDHCI_CTRL_VDD_180;
185 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
188 if (mmc->selected_mode > SD_HS &&
189 mmc->selected_mode <= UHS_DDR50)
190 sdhci_set_uhs_timing(host);
194 #if defined(CONFIG_ARCH_ZYNQMP)
195 const struct sdhci_ops arasan_ops = {
196 .platform_execute_tuning = &arasan_sdhci_execute_tuning,
197 .set_delay = &arasan_sdhci_set_tapdelay,
198 .set_control_reg = &arasan_sdhci_set_control_reg,
202 static int arasan_sdhci_probe(struct udevice *dev)
204 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
205 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
206 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
207 struct sdhci_host *host;
214 ret = clk_get_by_index(dev, 0, &clk);
216 dev_err(dev, "failed to get clock\n");
220 clock = clk_get_rate(&clk);
221 if (IS_ERR_VALUE(clock)) {
222 dev_err(dev, "failed to get rate\n");
226 debug("%s: CLK %ld\n", __func__, clock);
228 ret = clk_enable(&clk);
229 if (ret && ret != -ENOSYS) {
230 dev_err(dev, "failed to enable clock\n");
234 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
235 SDHCI_QUIRK_BROKEN_R1B;
237 #ifdef CONFIG_ZYNQ_HISPD_BROKEN
238 host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
242 host->quirks |= SDHCI_QUIRK_NO_1_8_V;
244 host->max_clk = clock;
246 host->mmc = &plat->mmc;
247 host->mmc->dev = dev;
248 host->mmc->priv = host;
250 ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max,
251 CONFIG_ZYNQ_SDHCI_MIN_FREQ);
254 upriv->mmc = host->mmc;
256 return sdhci_probe(dev);
259 static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
261 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
262 struct arasan_sdhci_priv *priv = dev_get_priv(dev);
264 priv->host = calloc(1, sizeof(struct sdhci_host));
268 priv->host->name = dev->name;
270 #if defined(CONFIG_ARCH_ZYNQMP)
271 priv->host->ops = &arasan_ops;
274 priv->host->ioaddr = (void *)dev_read_addr(dev);
275 if (IS_ERR(priv->host->ioaddr))
276 return PTR_ERR(priv->host->ioaddr);
278 priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
279 priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
280 priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
282 plat->f_max = dev_read_u32_default(dev, "max-frequency",
283 CONFIG_ZYNQ_SDHCI_MAX_FREQ);
287 static int arasan_sdhci_bind(struct udevice *dev)
289 struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
291 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
294 static const struct udevice_id arasan_sdhci_ids[] = {
295 { .compatible = "arasan,sdhci-8.9a" },
299 U_BOOT_DRIVER(arasan_sdhci_drv) = {
300 .name = "arasan_sdhci",
302 .of_match = arasan_sdhci_ids,
303 .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
305 .bind = arasan_sdhci_bind,
306 .probe = arasan_sdhci_probe,
307 .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
308 .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),