2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <dm/device.h>
13 #include <linux/compat.h>
15 #include <asm/unaligned.h>
16 #include <asm/dma-mapping.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #define UNIPHIER_SD_CMD 0x000 /* command */
21 #define UNIPHIER_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
22 #define UNIPHIER_SD_CMD_MULTI BIT(13) /* multiple block transfer */
23 #define UNIPHIER_SD_CMD_RD BIT(12) /* 1: read, 0: write */
24 #define UNIPHIER_SD_CMD_DATA BIT(11) /* data transfer */
25 #define UNIPHIER_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
26 #define UNIPHIER_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
27 #define UNIPHIER_SD_CMD_RSP_NONE (3 << 8)/* response: none */
28 #define UNIPHIER_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
29 #define UNIPHIER_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
30 #define UNIPHIER_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
31 #define UNIPHIER_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
32 #define UNIPHIER_SD_ARG 0x008 /* command argument */
33 #define UNIPHIER_SD_STOP 0x010 /* stop action control */
34 #define UNIPHIER_SD_STOP_SEC BIT(8) /* use sector count */
35 #define UNIPHIER_SD_STOP_STP BIT(0) /* issue CMD12 */
36 #define UNIPHIER_SD_SECCNT 0x014 /* sector counter */
37 #define UNIPHIER_SD_RSP10 0x018 /* response[39:8] */
38 #define UNIPHIER_SD_RSP32 0x020 /* response[71:40] */
39 #define UNIPHIER_SD_RSP54 0x028 /* response[103:72] */
40 #define UNIPHIER_SD_RSP76 0x030 /* response[127:104] */
41 #define UNIPHIER_SD_INFO1 0x038 /* IRQ status 1 */
42 #define UNIPHIER_SD_INFO1_CD BIT(5) /* state of card detect */
43 #define UNIPHIER_SD_INFO1_INSERT BIT(4) /* card inserted */
44 #define UNIPHIER_SD_INFO1_REMOVE BIT(3) /* card removed */
45 #define UNIPHIER_SD_INFO1_CMP BIT(2) /* data complete */
46 #define UNIPHIER_SD_INFO1_RSP BIT(0) /* response complete */
47 #define UNIPHIER_SD_INFO2 0x03c /* IRQ status 2 */
48 #define UNIPHIER_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
49 #define UNIPHIER_SD_INFO2_CBSY BIT(14) /* command busy */
50 #define UNIPHIER_SD_INFO2_BWE BIT(9) /* write buffer ready */
51 #define UNIPHIER_SD_INFO2_BRE BIT(8) /* read buffer ready */
52 #define UNIPHIER_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
53 #define UNIPHIER_SD_INFO2_ERR_RTO BIT(6) /* response time out */
54 #define UNIPHIER_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
55 #define UNIPHIER_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
56 #define UNIPHIER_SD_INFO2_ERR_TO BIT(3) /* time out error */
57 #define UNIPHIER_SD_INFO2_ERR_END BIT(2) /* END bit error */
58 #define UNIPHIER_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
59 #define UNIPHIER_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
60 #define UNIPHIER_SD_INFO1_MASK 0x040
61 #define UNIPHIER_SD_INFO2_MASK 0x044
62 #define UNIPHIER_SD_CLKCTL 0x048 /* clock divisor */
63 #define UNIPHIER_SD_CLKCTL_DIV_MASK 0x104ff
64 #define UNIPHIER_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
65 #define UNIPHIER_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
66 #define UNIPHIER_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
67 #define UNIPHIER_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
68 #define UNIPHIER_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
69 #define UNIPHIER_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
70 #define UNIPHIER_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
71 #define UNIPHIER_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
72 #define UNIPHIER_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
73 #define UNIPHIER_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
74 #define UNIPHIER_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
75 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
76 #define UNIPHIER_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
77 #define UNIPHIER_SD_SIZE 0x04c /* block size */
78 #define UNIPHIER_SD_OPTION 0x050
79 #define UNIPHIER_SD_OPTION_WIDTH_MASK (5 << 13)
80 #define UNIPHIER_SD_OPTION_WIDTH_1 (4 << 13)
81 #define UNIPHIER_SD_OPTION_WIDTH_4 (0 << 13)
82 #define UNIPHIER_SD_OPTION_WIDTH_8 (1 << 13)
83 #define UNIPHIER_SD_BUF 0x060 /* read/write buffer */
84 #define UNIPHIER_SD_EXTMODE 0x1b0
85 #define UNIPHIER_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
86 #define UNIPHIER_SD_SOFT_RST 0x1c0
87 #define UNIPHIER_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
88 #define UNIPHIER_SD_VERSION 0x1c4 /* version register */
89 #define UNIPHIER_SD_VERSION_IP 0xff /* IP version */
90 #define UNIPHIER_SD_HOST_MODE 0x1c8
91 #define UNIPHIER_SD_IF_MODE 0x1cc
92 #define UNIPHIER_SD_IF_MODE_DDR BIT(0) /* DDR mode */
93 #define UNIPHIER_SD_VOLT 0x1e4 /* voltage switch */
94 #define UNIPHIER_SD_VOLT_MASK (3 << 0)
95 #define UNIPHIER_SD_VOLT_OFF (0 << 0)
96 #define UNIPHIER_SD_VOLT_330 (1 << 0)/* 3.3V signal */
97 #define UNIPHIER_SD_VOLT_180 (2 << 0)/* 1.8V signal */
98 #define UNIPHIER_SD_DMA_MODE 0x410
99 #define UNIPHIER_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
100 #define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
101 #define UNIPHIER_SD_DMA_CTL 0x414
102 #define UNIPHIER_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
103 #define UNIPHIER_SD_DMA_RST 0x418
104 #define UNIPHIER_SD_DMA_RST_RD BIT(9)
105 #define UNIPHIER_SD_DMA_RST_WR BIT(8)
106 #define UNIPHIER_SD_DMA_INFO1 0x420
107 #define UNIPHIER_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete*/
108 #define UNIPHIER_SD_DMA_INFO1_END_RD BIT(17) /* Don't use! Hardware bug */
109 #define UNIPHIER_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
110 #define UNIPHIER_SD_DMA_INFO1_MASK 0x424
111 #define UNIPHIER_SD_DMA_INFO2 0x428
112 #define UNIPHIER_SD_DMA_INFO2_ERR_RD BIT(17)
113 #define UNIPHIER_SD_DMA_INFO2_ERR_WR BIT(16)
114 #define UNIPHIER_SD_DMA_INFO2_MASK 0x42c
115 #define UNIPHIER_SD_DMA_ADDR_L 0x440
116 #define UNIPHIER_SD_DMA_ADDR_H 0x444
118 /* alignment required by the DMA engine of this controller */
119 #define UNIPHIER_SD_DMA_MINALIGN 0x10
121 struct uniphier_sd_priv {
122 struct mmc_config cfg;
125 void __iomem *regbase;
127 unsigned int version;
129 #define UNIPHIER_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
130 #define UNIPHIER_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
131 #define UNIPHIER_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
134 static dma_addr_t __dma_map_single(void *ptr, size_t size,
135 enum dma_data_direction dir)
137 unsigned long addr = (unsigned long)ptr;
139 if (dir == DMA_FROM_DEVICE)
140 invalidate_dcache_range(addr, addr + size);
142 flush_dcache_range(addr, addr + size);
147 static void __dma_unmap_single(dma_addr_t addr, size_t size,
148 enum dma_data_direction dir)
150 if (dir != DMA_TO_DEVICE)
151 invalidate_dcache_range(addr, addr + size);
154 static int uniphier_sd_check_error(struct uniphier_sd_priv *priv)
156 u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2);
158 if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
160 * TIMEOUT must be returned for unsupported command. Do not
161 * display error log since this might be a part of sequence to
162 * distinguish between SD and MMC.
167 if (info2 & UNIPHIER_SD_INFO2_ERR_TO) {
168 dev_err(priv->dev, "timeout error\n");
172 if (info2 & (UNIPHIER_SD_INFO2_ERR_END | UNIPHIER_SD_INFO2_ERR_CRC |
173 UNIPHIER_SD_INFO2_ERR_IDX)) {
174 dev_err(priv->dev, "communication out of sync\n");
178 if (info2 & (UNIPHIER_SD_INFO2_ERR_ILA | UNIPHIER_SD_INFO2_ERR_ILR |
179 UNIPHIER_SD_INFO2_ERR_ILW)) {
180 dev_err(priv->dev, "illegal access\n");
187 static int uniphier_sd_wait_for_irq(struct uniphier_sd_priv *priv,
188 unsigned int reg, u32 flag)
193 while (!(readl(priv->regbase + reg) & flag)) {
195 dev_err(priv->dev, "timeout\n");
199 ret = uniphier_sd_check_error(priv);
209 static int uniphier_sd_pio_read_one_block(struct mmc *mmc, u32 **pbuf,
212 struct uniphier_sd_priv *priv = mmc->priv;
215 /* wait until the buffer is filled with data */
216 ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO2,
217 UNIPHIER_SD_INFO2_BRE);
222 * Clear the status flag _before_ read the buffer out because
223 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
225 writel(0, priv->regbase + UNIPHIER_SD_INFO2);
227 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
228 for (i = 0; i < blocksize / 4; i++)
229 *(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF);
231 for (i = 0; i < blocksize / 4; i++)
232 put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF),
239 static int uniphier_sd_pio_write_one_block(struct mmc *mmc, const u32 **pbuf,
242 struct uniphier_sd_priv *priv = mmc->priv;
245 /* wait until the buffer becomes empty */
246 ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO2,
247 UNIPHIER_SD_INFO2_BWE);
251 writel(0, priv->regbase + UNIPHIER_SD_INFO2);
253 if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
254 for (i = 0; i < blocksize / 4; i++)
255 writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF);
257 for (i = 0; i < blocksize / 4; i++)
258 writel(get_unaligned((*pbuf)++),
259 priv->regbase + UNIPHIER_SD_BUF);
265 static int uniphier_sd_pio_xfer(struct mmc *mmc, struct mmc_data *data)
267 u32 *dest = (u32 *)data->dest;
268 const u32 *src = (const u32 *)data->src;
271 for (i = 0; i < data->blocks; i++) {
272 if (data->flags & MMC_DATA_READ)
273 ret = uniphier_sd_pio_read_one_block(mmc, &dest,
276 ret = uniphier_sd_pio_write_one_block(mmc, &src,
285 static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
290 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1);
291 writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2);
294 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
295 tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
296 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
298 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L);
300 /* suppress the warning "right shift count >= width of type" */
301 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
303 writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H);
305 writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL);
308 static int uniphier_sd_dma_wait_for_irq(struct uniphier_sd_priv *priv, u32 flag,
311 long wait = 1000000 + 10 * blocks;
313 while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) {
315 dev_err(priv->dev, "timeout during DMA\n");
322 if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) {
323 dev_err(priv->dev, "error during DMA\n");
330 static int uniphier_sd_dma_xfer(struct mmc *mmc, struct mmc_data *data)
332 struct uniphier_sd_priv *priv = mmc->priv;
333 size_t len = data->blocks * data->blocksize;
335 enum dma_data_direction dir;
340 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
342 if (data->flags & MMC_DATA_READ) {
344 dir = DMA_FROM_DEVICE;
345 poll_flag = UNIPHIER_SD_DMA_INFO1_END_RD2;
346 tmp |= UNIPHIER_SD_DMA_MODE_DIR_RD;
348 buf = (void *)data->src;
350 poll_flag = UNIPHIER_SD_DMA_INFO1_END_WR;
351 tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
354 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
356 dma_addr = __dma_map_single(buf, len, dir);
358 uniphier_sd_dma_start(priv, dma_addr);
360 ret = uniphier_sd_dma_wait_for_irq(priv, poll_flag, data->blocks);
362 __dma_unmap_single(dma_addr, len, dir);
367 /* check if the address is DMA'able */
368 static bool uniphier_sd_addr_is_dmaable(unsigned long addr)
370 if (!IS_ALIGNED(addr, UNIPHIER_SD_DMA_MINALIGN))
373 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
374 defined(CONFIG_SPL_BUILD)
376 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
377 * of L2, which is unreachable from the DMA engine.
379 if (addr < CONFIG_SPL_STACK)
386 static int uniphier_sd_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
387 struct mmc_data *data)
389 struct uniphier_sd_priv *priv = mmc->priv;
393 if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
394 dev_err(priv->dev, "command busy\n");
398 /* clear all status flags */
399 writel(0, priv->regbase + UNIPHIER_SD_INFO1);
400 writel(0, priv->regbase + UNIPHIER_SD_INFO2);
402 /* disable DMA once */
403 tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
404 tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
405 writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
407 writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG);
412 writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE);
413 writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT);
415 /* Do not send CMD12 automatically */
416 tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
418 if (data->blocks > 1)
419 tmp |= UNIPHIER_SD_CMD_MULTI;
421 if (data->flags & MMC_DATA_READ)
422 tmp |= UNIPHIER_SD_CMD_RD;
426 * Do not use the response type auto-detection on this hardware.
427 * CMD8, for example, has different response types on SD and eMMC,
428 * while this controller always assumes the response type for SD.
429 * Set the response type manually.
431 switch (cmd->resp_type) {
433 tmp |= UNIPHIER_SD_CMD_RSP_NONE;
436 tmp |= UNIPHIER_SD_CMD_RSP_R1;
439 tmp |= UNIPHIER_SD_CMD_RSP_R1B;
442 tmp |= UNIPHIER_SD_CMD_RSP_R2;
445 tmp |= UNIPHIER_SD_CMD_RSP_R3;
448 dev_err(priv->dev, "unknown response type\n");
452 dev_dbg(priv->dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
453 cmd->cmdidx, tmp, cmd->cmdarg);
454 writel(tmp, priv->regbase + UNIPHIER_SD_CMD);
456 ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO1,
457 UNIPHIER_SD_INFO1_RSP);
461 if (cmd->resp_type & MMC_RSP_136) {
462 u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76);
463 u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54);
464 u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32);
465 u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10);
467 cmd->response[0] = (rsp_127_104 & 0xffffff) << 8 |
469 cmd->response[1] = (rsp_103_72 & 0xffffff) << 8 |
471 cmd->response[2] = (rsp_71_40 & 0xffffff) << 8 |
473 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
476 cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10);
480 /* use DMA if the HW supports it and the buffer is aligned */
481 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL &&
482 uniphier_sd_addr_is_dmaable((long)data->src))
483 ret = uniphier_sd_dma_xfer(mmc, data);
485 ret = uniphier_sd_pio_xfer(mmc, data);
487 ret = uniphier_sd_wait_for_irq(priv, UNIPHIER_SD_INFO1,
488 UNIPHIER_SD_INFO1_CMP);
496 static void uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
501 switch (mmc->bus_width) {
503 val = UNIPHIER_SD_OPTION_WIDTH_1;
506 val = UNIPHIER_SD_OPTION_WIDTH_4;
509 val = UNIPHIER_SD_OPTION_WIDTH_8;
516 tmp = readl(priv->regbase + UNIPHIER_SD_OPTION);
517 tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
519 writel(tmp, priv->regbase + UNIPHIER_SD_OPTION);
522 static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
527 tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE);
529 tmp |= UNIPHIER_SD_IF_MODE_DDR;
531 tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
532 writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE);
535 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
538 unsigned int divisor;
544 divisor = DIV_ROUND_UP(priv->mclk, mmc->clock);
547 val = UNIPHIER_SD_CLKCTL_DIV1;
548 else if (divisor <= 2)
549 val = UNIPHIER_SD_CLKCTL_DIV2;
550 else if (divisor <= 4)
551 val = UNIPHIER_SD_CLKCTL_DIV4;
552 else if (divisor <= 8)
553 val = UNIPHIER_SD_CLKCTL_DIV8;
554 else if (divisor <= 16)
555 val = UNIPHIER_SD_CLKCTL_DIV16;
556 else if (divisor <= 32)
557 val = UNIPHIER_SD_CLKCTL_DIV32;
558 else if (divisor <= 64)
559 val = UNIPHIER_SD_CLKCTL_DIV64;
560 else if (divisor <= 128)
561 val = UNIPHIER_SD_CLKCTL_DIV128;
562 else if (divisor <= 256)
563 val = UNIPHIER_SD_CLKCTL_DIV256;
564 else if (divisor <= 512 || !(priv->caps & UNIPHIER_SD_CAP_DIV1024))
565 val = UNIPHIER_SD_CLKCTL_DIV512;
567 val = UNIPHIER_SD_CLKCTL_DIV1024;
569 tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL);
571 /* stop the clock before changing its rate to avoid a glitch signal */
572 tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
573 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
575 tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
576 tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
577 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
579 tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
580 writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
583 static void uniphier_sd_set_ios(struct mmc *mmc)
585 struct uniphier_sd_priv *priv = mmc->priv;
587 dev_dbg(priv->dev, "clock %uHz, DDRmode %d, width %u\n",
588 mmc->clock, mmc->ddr_mode, mmc->bus_width);
590 uniphier_sd_set_bus_width(priv, mmc);
591 uniphier_sd_set_ddr_mode(priv, mmc);
592 uniphier_sd_set_clk_rate(priv, mmc);
597 static int uniphier_sd_init(struct mmc *mmc)
599 struct uniphier_sd_priv *priv = mmc->priv;
602 /* soft reset of the host */
603 tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST);
604 tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
605 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
606 tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
607 writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
609 /* FIXME: implement eMMC hw_reset */
611 writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP);
614 * Connected to 32bit AXI.
615 * This register dropped backward compatibility at version 0x10.
616 * Write an appropriate value depending on the IP version.
618 writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000,
619 priv->regbase + UNIPHIER_SD_HOST_MODE);
621 if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
622 tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
623 tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
624 writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
630 static int uniphier_sd_getcd(struct mmc *mmc)
632 struct uniphier_sd_priv *priv = mmc->priv;
634 if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
637 return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) &
638 UNIPHIER_SD_INFO1_CD);
641 static const struct mmc_ops uniphier_sd_ops = {
642 .send_cmd = uniphier_sd_send_cmd,
643 .set_ios = uniphier_sd_set_ios,
644 .init = uniphier_sd_init,
645 .getcd = uniphier_sd_getcd,
648 int uniphier_sd_probe(struct udevice *dev)
650 struct uniphier_sd_priv *priv = dev_get_priv(dev);
651 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
654 struct udevice *clk_dev;
660 base = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
661 priv->regbase = map_sysmem(base, size);
665 clk_id = clk_get_by_index(dev, 0, &clk_dev);
667 dev_err(dev, "failed to get host clock\n");
671 /* set to max rate */
672 priv->mclk = clk_set_periph_rate(clk_dev, clk_id, ULONG_MAX);
673 if (IS_ERR_VALUE(priv->mclk)) {
674 dev_err(dev, "failed to set rate for host clock\n");
678 ret = clk_enable(clk_dev, clk_id);
680 dev_err(dev, "failed to enable host clock\n");
684 priv->cfg.name = dev->name;
685 priv->cfg.ops = &uniphier_sd_ops;
686 priv->cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
688 switch (fdtdec_get_int(gd->fdt_blob, dev->of_offset, "bus-width", 1)) {
690 priv->cfg.host_caps |= MMC_MODE_8BIT;
693 priv->cfg.host_caps |= MMC_MODE_4BIT;
698 dev_err(dev, "Invalid \"bus-width\" value\n");
702 if (fdt_get_property(gd->fdt_blob, dev->of_offset, "non-removable",
704 priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
706 priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) &
707 UNIPHIER_SD_VERSION_IP;
708 dev_dbg(dev, "version %x\n", priv->version);
709 if (priv->version >= 0x10) {
710 priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
711 priv->caps |= UNIPHIER_SD_CAP_DIV1024;
714 priv->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
715 priv->cfg.f_min = priv->mclk /
716 (priv->caps & UNIPHIER_SD_CAP_DIV1024 ? 1024 : 512);
717 priv->cfg.f_max = priv->mclk;
718 priv->cfg.b_max = U32_MAX; /* max value of UNIPHIER_SD_SECCNT */
720 priv->mmc = mmc_create(&priv->cfg, priv);
724 upriv->mmc = priv->mmc;
729 int uniphier_sd_remove(struct udevice *dev)
731 struct uniphier_sd_priv *priv = dev_get_priv(dev);
733 unmap_sysmem(priv->regbase);
734 mmc_destroy(priv->mmc);
739 static const struct udevice_id uniphier_sd_match[] = {
740 { .compatible = "socionext,uniphier-sdhc" },
744 U_BOOT_DRIVER(uniphier_mmc) = {
745 .name = "uniphier-mmc",
747 .of_match = uniphier_sd_match,
748 .probe = uniphier_sd_probe,
749 .remove = uniphier_sd_remove,
750 .priv_auto_alloc_size = sizeof(struct uniphier_sd_priv),