1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
13 #include <dm/pinctrl.h>
14 #include <linux/compat.h>
15 #include <linux/dma-direction.h>
17 #include <linux/sizes.h>
18 #include <power/regulator.h>
19 #include <asm/unaligned.h>
21 #include "tmio-common.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
27 return readq(priv->regbase + (reg << 1));
30 static void tmio_sd_writeq(struct tmio_sd_priv *priv,
31 u64 val, unsigned int reg)
33 writeq(val, priv->regbase + (reg << 1));
36 static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
38 return readw(priv->regbase + (reg >> 1));
41 static void tmio_sd_writew(struct tmio_sd_priv *priv,
42 u16 val, unsigned int reg)
44 writew(val, priv->regbase + (reg >> 1));
47 u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
51 if (priv->caps & TMIO_SD_CAP_64BIT)
52 return readl(priv->regbase + (reg << 1));
53 else if (priv->caps & TMIO_SD_CAP_16BIT) {
54 val = readw(priv->regbase + (reg >> 1)) & 0xffff;
55 if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
56 (reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
57 val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
61 return readl(priv->regbase + reg);
64 void tmio_sd_writel(struct tmio_sd_priv *priv,
65 u32 val, unsigned int reg)
67 if (priv->caps & TMIO_SD_CAP_64BIT)
68 writel(val, priv->regbase + (reg << 1));
69 else if (priv->caps & TMIO_SD_CAP_16BIT) {
70 writew(val & 0xffff, priv->regbase + (reg >> 1));
71 if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
72 reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
74 writew(val >> 16, priv->regbase + (reg >> 1) + 2);
76 writel(val, priv->regbase + reg);
79 static dma_addr_t __dma_map_single(void *ptr, size_t size,
80 enum dma_data_direction dir)
82 unsigned long addr = (unsigned long)ptr;
84 if (dir == DMA_FROM_DEVICE)
85 invalidate_dcache_range(addr, addr + size);
87 flush_dcache_range(addr, addr + size);
92 static void __dma_unmap_single(dma_addr_t addr, size_t size,
93 enum dma_data_direction dir)
95 if (dir != DMA_TO_DEVICE)
96 invalidate_dcache_range(addr, addr + size);
99 static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
101 struct tmio_sd_priv *priv = dev_get_priv(dev);
102 u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
104 if (info2 & TMIO_SD_INFO2_ERR_RTO) {
106 * TIMEOUT must be returned for unsupported command. Do not
107 * display error log since this might be a part of sequence to
108 * distinguish between SD and MMC.
113 if (info2 & TMIO_SD_INFO2_ERR_TO) {
114 dev_err(dev, "timeout error\n");
118 if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
119 TMIO_SD_INFO2_ERR_IDX)) {
120 if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
121 (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
122 dev_err(dev, "communication out of sync\n");
126 if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
127 TMIO_SD_INFO2_ERR_ILW)) {
128 dev_err(dev, "illegal access\n");
135 static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
136 unsigned int reg, u32 flag)
138 struct tmio_sd_priv *priv = dev_get_priv(dev);
142 while (!(tmio_sd_readl(priv, reg) & flag)) {
144 dev_err(dev, "timeout\n");
148 ret = tmio_sd_check_error(dev, cmd);
158 #define tmio_pio_read_fifo(__width, __suffix) \
159 static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
160 char *pbuf, uint blksz) \
162 u##__width *buf = (u##__width *)pbuf; \
165 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
166 for (i = 0; i < blksz / ((__width) / 8); i++) { \
167 *buf++ = tmio_sd_read##__suffix(priv, \
171 for (i = 0; i < blksz / ((__width) / 8); i++) { \
173 data = tmio_sd_read##__suffix(priv, \
175 put_unaligned(data, buf++); \
180 tmio_pio_read_fifo(64, q)
181 tmio_pio_read_fifo(32, l)
182 tmio_pio_read_fifo(16, w)
184 static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
185 char *pbuf, uint blocksize)
187 struct tmio_sd_priv *priv = dev_get_priv(dev);
190 /* wait until the buffer is filled with data */
191 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
197 * Clear the status flag _before_ read the buffer out because
198 * TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
200 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
202 if (priv->caps & TMIO_SD_CAP_64BIT)
203 tmio_pio_read_fifo_64(priv, pbuf, blocksize);
204 else if (priv->caps & TMIO_SD_CAP_16BIT)
205 tmio_pio_read_fifo_16(priv, pbuf, blocksize);
207 tmio_pio_read_fifo_32(priv, pbuf, blocksize);
212 #define tmio_pio_write_fifo(__width, __suffix) \
213 static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
214 const char *pbuf, uint blksz)\
216 const u##__width *buf = (const u##__width *)pbuf; \
219 if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
220 for (i = 0; i < blksz / ((__width) / 8); i++) { \
221 tmio_sd_write##__suffix(priv, *buf++, \
225 for (i = 0; i < blksz / ((__width) / 8); i++) { \
226 u##__width data = get_unaligned(buf++); \
227 tmio_sd_write##__suffix(priv, data, \
233 tmio_pio_write_fifo(64, q)
234 tmio_pio_write_fifo(32, l)
235 tmio_pio_write_fifo(16, w)
237 static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
238 const char *pbuf, uint blocksize)
240 struct tmio_sd_priv *priv = dev_get_priv(dev);
243 /* wait until the buffer becomes empty */
244 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
249 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
251 if (priv->caps & TMIO_SD_CAP_64BIT)
252 tmio_pio_write_fifo_64(priv, pbuf, blocksize);
253 else if (priv->caps & TMIO_SD_CAP_16BIT)
254 tmio_pio_write_fifo_16(priv, pbuf, blocksize);
256 tmio_pio_write_fifo_32(priv, pbuf, blocksize);
261 static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
262 struct mmc_data *data)
264 const char *src = data->src;
265 char *dest = data->dest;
268 for (i = 0; i < data->blocks; i++) {
269 if (data->flags & MMC_DATA_READ)
270 ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
273 ret = tmio_sd_pio_write_one_block(dev, cmd, src,
278 if (data->flags & MMC_DATA_READ)
279 dest += data->blocksize;
281 src += data->blocksize;
287 static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
292 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
293 tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
296 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
297 tmp |= TMIO_SD_EXTMODE_DMA_EN;
298 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
300 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
302 /* suppress the warning "right shift count >= width of type" */
303 dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
305 tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
307 tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
310 static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
313 struct tmio_sd_priv *priv = dev_get_priv(dev);
314 long wait = 1000000 + 10 * blocks;
316 while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
318 dev_err(dev, "timeout during DMA\n");
325 if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
326 dev_err(dev, "error during DMA\n");
333 static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
335 struct tmio_sd_priv *priv = dev_get_priv(dev);
336 size_t len = data->blocks * data->blocksize;
338 enum dma_data_direction dir;
343 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
345 if (data->flags & MMC_DATA_READ) {
347 dir = DMA_FROM_DEVICE;
349 * The DMA READ completion flag position differs on Socionext
350 * and Renesas SoCs. It is bit 20 on Socionext SoCs and using
351 * bit 17 is a hardware bug and forbidden. It is either bit 17
352 * or bit 20 on Renesas SoCs, depending on SoC.
354 poll_flag = priv->read_poll_flag;
355 tmp |= TMIO_SD_DMA_MODE_DIR_RD;
357 buf = (void *)data->src;
359 poll_flag = TMIO_SD_DMA_INFO1_END_WR;
360 tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
363 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
365 dma_addr = __dma_map_single(buf, len, dir);
367 tmio_sd_dma_start(priv, dma_addr);
369 ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
371 if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
374 __dma_unmap_single(dma_addr, len, dir);
379 /* check if the address is DMA'able */
380 static bool tmio_sd_addr_is_dmaable(const char *src)
382 uintptr_t addr = (uintptr_t)src;
384 if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
387 #if defined(CONFIG_RCAR_GEN3)
388 /* Gen3 DMA has 32bit limit */
393 #if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
394 defined(CONFIG_SPL_BUILD)
396 * For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
397 * of L2, which is unreachable from the DMA engine.
399 if (addr < CONFIG_SPL_STACK)
406 int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
407 struct mmc_data *data)
409 struct tmio_sd_priv *priv = dev_get_priv(dev);
413 if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
414 dev_err(dev, "command busy\n");
418 /* clear all status flags */
419 tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
420 tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
422 /* disable DMA once */
423 tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
424 tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
425 tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
427 tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
432 tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
433 tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
435 /* Do not send CMD12 automatically */
436 tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
438 if (data->blocks > 1)
439 tmp |= TMIO_SD_CMD_MULTI;
441 if (data->flags & MMC_DATA_READ)
442 tmp |= TMIO_SD_CMD_RD;
446 * Do not use the response type auto-detection on this hardware.
447 * CMD8, for example, has different response types on SD and eMMC,
448 * while this controller always assumes the response type for SD.
449 * Set the response type manually.
451 switch (cmd->resp_type) {
453 tmp |= TMIO_SD_CMD_RSP_NONE;
456 tmp |= TMIO_SD_CMD_RSP_R1;
459 tmp |= TMIO_SD_CMD_RSP_R1B;
462 tmp |= TMIO_SD_CMD_RSP_R2;
465 tmp |= TMIO_SD_CMD_RSP_R3;
468 dev_err(dev, "unknown response type\n");
472 dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
473 cmd->cmdidx, tmp, cmd->cmdarg);
474 tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
476 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
481 if (cmd->resp_type & MMC_RSP_136) {
482 u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
483 u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
484 u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
485 u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
487 cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
488 ((rsp_103_72 & 0xff000000) >> 24);
489 cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
490 ((rsp_71_40 & 0xff000000) >> 24);
491 cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
492 ((rsp_39_8 & 0xff000000) >> 24);
493 cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
496 cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
500 /* use DMA if the HW supports it and the buffer is aligned */
501 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
502 tmio_sd_addr_is_dmaable(data->src))
503 ret = tmio_sd_dma_xfer(dev, data);
505 ret = tmio_sd_pio_xfer(dev, cmd, data);
509 ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
515 return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
516 TMIO_SD_INFO2_SCLKDIVEN);
519 static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
524 switch (mmc->bus_width) {
527 val = TMIO_SD_OPTION_WIDTH_1;
530 val = TMIO_SD_OPTION_WIDTH_4;
533 val = TMIO_SD_OPTION_WIDTH_8;
539 tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
540 tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
542 tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
547 static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
552 tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
554 tmp |= TMIO_SD_IF_MODE_DDR;
556 tmp &= ~TMIO_SD_IF_MODE_DDR;
557 tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
560 static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
562 return priv->clk_get_rate(priv);
565 static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
567 unsigned int divisor;
572 mclk = tmio_sd_clk_get_rate(priv);
574 divisor = DIV_ROUND_UP(mclk, mmc->clock);
576 /* Do not set divider to 0xff in DDR mode */
577 if (mmc->ddr_mode && (divisor == 1))
581 val = (priv->caps & TMIO_SD_CAP_RCAR) ?
582 TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
583 else if (divisor <= 2)
584 val = TMIO_SD_CLKCTL_DIV2;
585 else if (divisor <= 4)
586 val = TMIO_SD_CLKCTL_DIV4;
587 else if (divisor <= 8)
588 val = TMIO_SD_CLKCTL_DIV8;
589 else if (divisor <= 16)
590 val = TMIO_SD_CLKCTL_DIV16;
591 else if (divisor <= 32)
592 val = TMIO_SD_CLKCTL_DIV32;
593 else if (divisor <= 64)
594 val = TMIO_SD_CLKCTL_DIV64;
595 else if (divisor <= 128)
596 val = TMIO_SD_CLKCTL_DIV128;
597 else if (divisor <= 256)
598 val = TMIO_SD_CLKCTL_DIV256;
599 else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
600 val = TMIO_SD_CLKCTL_DIV512;
602 val = TMIO_SD_CLKCTL_DIV1024;
605 tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
607 !((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
608 ((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
610 * Stop the clock before changing its rate
611 * to avoid a glitch signal
613 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
614 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
616 /* Change the clock rate. */
617 tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
621 /* Enable or Disable the clock */
622 if (mmc->clk_disable) {
623 tmp |= TMIO_SD_CLKCTL_OFFEN;
624 tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
626 tmp &= ~TMIO_SD_CLKCTL_OFFEN;
627 tmp |= TMIO_SD_CLKCTL_SCLKEN;
630 tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
635 static void tmio_sd_set_pins(struct udevice *dev)
637 __maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
639 #ifdef CONFIG_DM_REGULATOR
640 struct tmio_sd_priv *priv = dev_get_priv(dev);
642 if (priv->vqmmc_dev) {
643 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
644 regulator_set_value(priv->vqmmc_dev, 1800000);
646 regulator_set_value(priv->vqmmc_dev, 3300000);
647 regulator_set_enable(priv->vqmmc_dev, true);
651 #ifdef CONFIG_PINCTRL
652 if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
653 pinctrl_select_state(dev, "state_uhs");
655 pinctrl_select_state(dev, "default");
659 int tmio_sd_set_ios(struct udevice *dev)
661 struct tmio_sd_priv *priv = dev_get_priv(dev);
662 struct mmc *mmc = mmc_get_mmc_dev(dev);
665 dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
666 mmc->clock, mmc->ddr_mode, mmc->bus_width);
668 tmio_sd_set_clk_rate(priv, mmc);
669 ret = tmio_sd_set_bus_width(priv, mmc);
672 tmio_sd_set_ddr_mode(priv, mmc);
673 tmio_sd_set_pins(dev);
678 int tmio_sd_get_cd(struct udevice *dev)
680 struct tmio_sd_priv *priv = dev_get_priv(dev);
682 if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
685 return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
689 static void tmio_sd_host_init(struct tmio_sd_priv *priv)
693 /* soft reset of the host */
694 tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
695 tmp &= ~TMIO_SD_SOFT_RST_RSTX;
696 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
697 tmp |= TMIO_SD_SOFT_RST_RSTX;
698 tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
700 /* FIXME: implement eMMC hw_reset */
702 tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
705 * Connected to 32bit AXI.
706 * This register dropped backward compatibility at version 0x10.
707 * Write an appropriate value depending on the IP version.
709 if (priv->version >= 0x10) {
710 if (priv->caps & TMIO_SD_CAP_64BIT)
711 tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
713 tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
715 tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
718 if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
719 tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
720 tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
721 tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
725 int tmio_sd_bind(struct udevice *dev)
727 struct tmio_sd_plat *plat = dev_get_platdata(dev);
729 return mmc_bind(dev, &plat->mmc, &plat->cfg);
732 int tmio_sd_probe(struct udevice *dev, u32 quirks)
734 struct tmio_sd_plat *plat = dev_get_platdata(dev);
735 struct tmio_sd_priv *priv = dev_get_priv(dev);
736 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
741 base = devfdt_get_addr(dev);
742 if (base == FDT_ADDR_T_NONE)
745 priv->regbase = devm_ioremap(dev, base, SZ_2K);
749 #ifdef CONFIG_DM_REGULATOR
750 device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
752 regulator_set_value(priv->vqmmc_dev, 3300000);
755 ret = mmc_of_parse(dev, &plat->cfg);
757 dev_err(dev, "failed to parse host caps\n");
761 plat->cfg.name = dev->name;
762 plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
767 priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
769 dev_dbg(dev, "version %x\n", priv->version);
770 if (priv->version >= 0x10) {
771 priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
772 priv->caps |= TMIO_SD_CAP_DIV1024;
775 if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
777 priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
779 tmio_sd_host_init(priv);
781 mclk = tmio_sd_clk_get_rate(priv);
783 plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
784 plat->cfg.f_min = mclk /
785 (priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
786 plat->cfg.f_max = mclk;
787 if (quirks & TMIO_SD_CAP_16BIT)
788 plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
790 plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
792 upriv->mmc = &plat->mmc;