drivers/mmc/tegra_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009 SAMSUNG Electronics
   4  * Minkyu Kang <mk7.kang@samsung.com>
   5  * Jaehoon Chung <jh80.chung@samsung.com>
   6  * Portions Copyright 2011-2019 NVIDIA Corporation
   7  */
   8
   9 #include <bouncebuf.h>
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <mmc.h>
  14 #include <asm/gpio.h>
  15 #include <asm/io.h>
  16 #include <asm/arch-tegra/tegra_mmc.h>
  17 #include <linux/err.h>
  18 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
  19 #include <asm/arch/clock.h>
  20 #endif
  21
  22 struct tegra_mmc_plat {
  23         struct mmc_config cfg;
  24         struct mmc mmc;
  25 };
  26
  27 struct tegra_mmc_priv {
  28         struct tegra_mmc *reg;
  29         struct reset_ctl reset_ctl;
  30         struct clk clk;
  31         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  32         struct gpio_desc pwr_gpio;      /* Power GPIO */
  33         struct gpio_desc wp_gpio;       /* Write Protect GPIO */
  34         unsigned int version;   /* SDHCI spec. version */
  35         unsigned int clock;     /* Current clock (MHz) */
  36         int mmc_id;             /* peripheral id */
  37 };
  38
  39 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
  40                                 unsigned short power)
  41 {
  42         u8 pwr = 0;
  43         debug("%s: power = %x\n", __func__, power);
  44
  45         if (power != (unsigned short)-1) {
  46                 switch (1 << power) {
  47                 case MMC_VDD_165_195:
  48                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
  49                         break;
  50                 case MMC_VDD_29_30:
  51                 case MMC_VDD_30_31:
  52                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
  53                         break;
  54                 case MMC_VDD_32_33:
  55                 case MMC_VDD_33_34:
  56                         pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
  57                         break;
  58                 }
  59         }
  60         debug("%s: pwr = %X\n", __func__, pwr);
  61
  62         /* Set the bus voltage first (if any) */
  63         writeb(pwr, &priv->reg->pwrcon);
  64         if (pwr == 0)
  65                 return;
  66
  67         /* Now enable bus power */
  68         pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
  69         writeb(pwr, &priv->reg->pwrcon);
  70 }
  71
  72 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
  73                                    struct mmc_data *data,
  74                                    struct bounce_buffer *bbstate)
  75 {
  76         unsigned char ctrl;
  77
  78
  79         debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
  80                 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
  81                 data->blocksize);
  82
  83         writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
  84         /*
  85          * DMASEL[4:3]
  86          * 00 = Selects SDMA
  87          * 01 = Reserved
  88          * 10 = Selects 32-bit Address ADMA2
  89          * 11 = Selects 64-bit Address ADMA2
  90          */
  91         ctrl = readb(&priv->reg->hostctl);
  92         ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
  93         ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
  94         writeb(ctrl, &priv->reg->hostctl);
  95
  96         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  97         writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
  98         writew(data->blocks, &priv->reg->blkcnt);
  99 }
 100
 101 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
 102                                         struct mmc_data *data)
 103 {
 104         unsigned short mode;
 105         debug(" mmc_set_transfer_mode called\n");
 106         /*
 107          * TRNMOD
 108          * MUL1SIN0[5]  : Multi/Single Block Select
 109          * RD1WT0[4]    : Data Transfer Direction Select
 110          *      1 = read
 111          *      0 = write
 112          * ENACMD12[2]  : Auto CMD12 Enable
 113          * ENBLKCNT[1]  : Block Count Enable
 114          * ENDMA[0]     : DMA Enable
 115          */
 116         mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
 117                 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
 118
 119         if (data->blocks > 1)
 120                 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
 121
 122         if (data->flags & MMC_DATA_READ)
 123                 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
 124
 125         writew(mode, &priv->reg->trnmod);
 126 }
 127
 128 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
 129                                   struct mmc_cmd *cmd,
 130                                   struct mmc_data *data,
 131                                   unsigned int timeout)
 132 {
 133         /*
 134          * PRNSTS
 135          * CMDINHDAT[1] : Command Inhibit (DAT)
 136          * CMDINHCMD[0] : Command Inhibit (CMD)
 137          */
 138         unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
 139
 140         /*
 141          * We shouldn't wait for data inhibit for stop commands, even
 142          * though they might use busy signaling
 143          */
 144         if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
 145                 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
 146
 147         while (readl(&priv->reg->prnsts) & mask) {
 148                 if (timeout == 0) {
 149                         printf("%s: timeout error\n", __func__);
 150                         return -1;
 151                 }
 152                 timeout--;
 153                 udelay(1000);
 154         }
 155
 156         return 0;
 157 }
 158
 159 static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
 160                                       struct mmc_data *data,
 161                                       struct bounce_buffer *bbstate)
 162 {
 163         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 164         int flags, i;
 165         int result;
 166         unsigned int mask = 0;
 167         unsigned int retry = 0x100000;
 168         debug(" mmc_send_cmd called\n");
 169
 170         result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
 171
 172         if (result < 0)
 173                 return result;
 174
 175         if (data)
 176                 tegra_mmc_prepare_data(priv, data, bbstate);
 177
 178         debug("cmd->arg: %08x\n", cmd->cmdarg);
 179         writel(cmd->cmdarg, &priv->reg->argument);
 180
 181         if (data)
 182                 tegra_mmc_set_transfer_mode(priv, data);
 183
 184         if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
 185                 return -1;
 186
 187         /*
 188          * CMDREG
 189          * CMDIDX[13:8] : Command index
 190          * DATAPRNT[5]  : Data Present Select
 191          * ENCMDIDX[4]  : Command Index Check Enable
 192          * ENCMDCRC[3]  : Command CRC Check Enable
 193          * RSPTYP[1:0]
 194          *      00 = No Response
 195          *      01 = Length 136
 196          *      10 = Length 48
 197          *      11 = Length 48 Check busy after response
 198          */
 199         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 200                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
 201         else if (cmd->resp_type & MMC_RSP_136)
 202                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
 203         else if (cmd->resp_type & MMC_RSP_BUSY)
 204                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
 205         else
 206                 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
 207
 208         if (cmd->resp_type & MMC_RSP_CRC)
 209                 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
 210         if (cmd->resp_type & MMC_RSP_OPCODE)
 211                 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
 212         if (data)
 213                 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
 214
 215         debug("cmd: %d\n", cmd->cmdidx);
 216
 217         writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
 218
 219         for (i = 0; i < retry; i++) {
 220                 mask = readl(&priv->reg->norintsts);
 221                 /* Command Complete */
 222                 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
 223                         if (!data)
 224                                 writel(mask, &priv->reg->norintsts);
 225                         break;
 226                 }
 227         }
 228
 229         if (i == retry) {
 230                 printf("%s: waiting for status update\n", __func__);
 231                 writel(mask, &priv->reg->norintsts);
 232                 return -ETIMEDOUT;
 233         }
 234
 235         if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
 236                 /* Timeout Error */
 237                 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
 238                 writel(mask, &priv->reg->norintsts);
 239                 return -ETIMEDOUT;
 240         } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 241                 /* Error Interrupt */
 242                 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
 243                 writel(mask, &priv->reg->norintsts);
 244                 return -1;
 245         }
 246
 247         if (cmd->resp_type & MMC_RSP_PRESENT) {
 248                 if (cmd->resp_type & MMC_RSP_136) {
 249                         /* CRC is stripped so we need to do some shifting. */
 250                         for (i = 0; i < 4; i++) {
 251                                 unsigned long offset = (unsigned long)
 252                                         (&priv->reg->rspreg3 - i);
 253                                 cmd->response[i] = readl(offset) << 8;
 254
 255                                 if (i != 3) {
 256                                         cmd->response[i] |=
 257                                                 readb(offset - 1);
 258                                 }
 259                                 debug("cmd->resp[%d]: %08x\n",
 260                                                 i, cmd->response[i]);
 261                         }
 262                 } else if (cmd->resp_type & MMC_RSP_BUSY) {
 263                         for (i = 0; i < retry; i++) {
 264                                 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
 265                                 if (readl(&priv->reg->prnsts)
 266                                         & (1 << 20))    /* DAT[0] */
 267                                         break;
 268                         }
 269
 270                         if (i == retry) {
 271                                 printf("%s: card is still busy\n", __func__);
 272                                 writel(mask, &priv->reg->norintsts);
 273                                 return -ETIMEDOUT;
 274                         }
 275
 276                         cmd->response[0] = readl(&priv->reg->rspreg0);
 277                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 278                 } else {
 279                         cmd->response[0] = readl(&priv->reg->rspreg0);
 280                         debug("cmd->resp[0]: %08x\n", cmd->response[0]);
 281                 }
 282         }
 283
 284         if (data) {
 285                 unsigned long   start = get_timer(0);
 286
 287                 while (1) {
 288                         mask = readl(&priv->reg->norintsts);
 289
 290                         if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
 291                                 /* Error Interrupt */
 292                                 writel(mask, &priv->reg->norintsts);
 293                                 printf("%s: error during transfer: 0x%08x\n",
 294                                                 __func__, mask);
 295                                 return -1;
 296                         } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
 297                                 /*
 298                                  * DMA Interrupt, restart the transfer where
 299                                  * it was interrupted.
 300                                  */
 301                                 unsigned int address = readl(&priv->reg->sysad);
 302
 303                                 debug("DMA end\n");
 304                                 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
 305                                        &priv->reg->norintsts);
 306                                 writel(address, &priv->reg->sysad);
 307                         } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
 308                                 /* Transfer Complete */
 309                                 debug("r/w is done\n");
 310                                 break;
 311                         } else if (get_timer(start) > 8000UL) {
 312                                 writel(mask, &priv->reg->norintsts);
 313                                 printf("%s: MMC Timeout\n"
 314                                        "    Interrupt status        0x%08x\n"
 315                                        "    Interrupt status enable 0x%08x\n"
 316                                        "    Interrupt signal enable 0x%08x\n"
 317                                        "    Present status          0x%08x\n",
 318                                        __func__, mask,
 319                                        readl(&priv->reg->norintstsen),
 320                                        readl(&priv->reg->norintsigen),
 321                                        readl(&priv->reg->prnsts));
 322                                 return -1;
 323                         }
 324                 }
 325                 writel(mask, &priv->reg->norintsts);
 326         }
 327
 328         udelay(1000);
 329         return 0;
 330 }
 331
 332 static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 333                               struct mmc_data *data)
 334 {
 335         void *buf;
 336         unsigned int bbflags;
 337         size_t len;
 338         struct bounce_buffer bbstate;
 339         int ret;
 340
 341         if (data) {
 342                 if (data->flags & MMC_DATA_READ) {
 343                         buf = data->dest;
 344                         bbflags = GEN_BB_WRITE;
 345                 } else {
 346                         buf = (void *)data->src;
 347                         bbflags = GEN_BB_READ;
 348                 }
 349                 len = data->blocks * data->blocksize;
 350
 351                 bounce_buffer_start(&bbstate, buf, len, bbflags);
 352         }
 353
 354         ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
 355
 356         if (data)
 357                 bounce_buffer_stop(&bbstate);
 358
 359         return ret;
 360 }
 361
 362 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
 363 {
 364         ulong rate;
 365         int div;
 366         unsigned short clk;
 367         unsigned long timeout;
 368
 369         debug(" mmc_change_clock called\n");
 370
 371         /*
 372          * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
 373          */
 374         if (clock == 0)
 375                 goto out;
 376
 377         rate = clk_set_rate(&priv->clk, clock);
 378         div = (rate + clock - 1) / clock;
 379
 380 #if defined(CONFIG_TEGRA210)
 381         if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) {
 382                 /* clock_adjust_periph_pll_div() chooses a 'bad' clock
 383                  * on SDMMC1 T210, so skip it here and force a clock
 384                  * that's been spec'd in the table in the TRM for
 385                  * card-detect (400KHz).
 386                  */
 387                 uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id,
 388                                 CLOCK_ID_PERIPH, 24727273, NULL);
 389                 div = 62;
 390
 391                 debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n",
 392                       __func__, effective_rate, div, clock);
 393         } else {
 394                 clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH,
 395                                             clock, &div);
 396         }
 397 #endif
 398         debug("div = %d\n", div);
 399
 400         writew(0, &priv->reg->clkcon);
 401
 402         /*
 403          * CLKCON
 404          * SELFREQ[15:8]        : base clock divided by value
 405          * ENSDCLK[2]           : SD Clock Enable
 406          * STBLINTCLK[1]        : Internal Clock Stable
 407          * ENINTCLK[0]          : Internal Clock Enable
 408          */
 409         div >>= 1;
 410         clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
 411                TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
 412         writew(clk, &priv->reg->clkcon);
 413
 414         /* Wait max 10 ms */
 415         timeout = 10;
 416         while (!(readw(&priv->reg->clkcon) &
 417                  TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
 418                 if (timeout == 0) {
 419                         printf("%s: timeout error\n", __func__);
 420                         return;
 421                 }
 422                 timeout--;
 423                 udelay(1000);
 424         }
 425
 426         clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 427         writew(clk, &priv->reg->clkcon);
 428
 429         debug("mmc_change_clock: clkcon = %08X\n", clk);
 430
 431 out:
 432         priv->clock = clock;
 433 }
 434
 435 static int tegra_mmc_set_ios(struct udevice *dev)
 436 {
 437         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 438         struct mmc *mmc = mmc_get_mmc_dev(dev);
 439         unsigned char ctrl;
 440         debug(" mmc_set_ios called\n");
 441
 442         debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
 443
 444         /* Change clock first */
 445         tegra_mmc_change_clock(priv, mmc->clock);
 446
 447         ctrl = readb(&priv->reg->hostctl);
 448
 449         /*
 450          * WIDE8[5]
 451          * 0 = Depend on WIDE4
 452          * 1 = 8-bit mode
 453          * WIDE4[1]
 454          * 1 = 4-bit mode
 455          * 0 = 1-bit mode
 456          */
 457         if (mmc->bus_width == 8)
 458                 ctrl |= (1 << 5);
 459         else if (mmc->bus_width == 4)
 460                 ctrl |= (1 << 1);
 461         else
 462                 ctrl &= ~(1 << 1 | 1 << 5);
 463
 464         writeb(ctrl, &priv->reg->hostctl);
 465         debug("mmc_set_ios: hostctl = %08X\n", ctrl);
 466
 467         return 0;
 468 }
 469
 470 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
 471 {
 472 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210)
 473         u32 val;
 474         u16 clk_con;
 475         int timeout;
 476         int id = priv->mmc_id;
 477
 478         debug("%s: sdmmc address = %p, id = %d\n", __func__,
 479                 priv->reg, id);
 480
 481         /* Set the pad drive strength for SDMMC1 or 3 only */
 482         if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
 483                 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
 484                         __func__);
 485                 return;
 486         }
 487
 488         val = readl(&priv->reg->sdmemcmppadctl);
 489         val &= 0xFFFFFFF0;
 490         val |= MEMCOMP_PADCTRL_VREF;
 491         writel(val, &priv->reg->sdmemcmppadctl);
 492
 493         /* Disable SD Clock Enable before running auto-cal as per TRM */
 494         clk_con = readw(&priv->reg->clkcon);
 495         debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
 496         clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 497         writew(clk_con, &priv->reg->clkcon);
 498
 499         val = readl(&priv->reg->autocalcfg);
 500         val &= 0xFFFF0000;
 501         val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET;
 502         writel(val, &priv->reg->autocalcfg);
 503         val |= AUTO_CAL_START | AUTO_CAL_ENABLE;
 504         writel(val, &priv->reg->autocalcfg);
 505         debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val);
 506         udelay(1);
 507         timeout = 100;                          /* 10 mSec max (100*100uS) */
 508         do {
 509                 val = readl(&priv->reg->autocalsts);
 510                 udelay(100);
 511         } while ((val & AUTO_CAL_ACTIVE) && --timeout);
 512         val = readl(&priv->reg->autocalsts);
 513         debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n",
 514               __func__, val, timeout);
 515
 516         /* Re-enable SD Clock Enable when auto-cal is done */
 517         clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
 518         writew(clk_con, &priv->reg->clkcon);
 519         clk_con = readw(&priv->reg->clkcon);
 520         debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con);
 521
 522         if (timeout == 0) {
 523                 printf("%s: Warning: Autocal timed out!\n", __func__);
 524                 /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */
 525         }
 526
 527 #if defined(CONFIG_TEGRA210)
 528         u32 tap_value, trim_value;
 529
 530         /* Set tap/trim values for SDMMC1/3 @ <48MHz here */
 531         val = readl(&priv->reg->venspictl);     /* aka VENDOR_SYS_SW_CNTL */
 532         val &= IO_TRIM_BYPASS_MASK;
 533         if (id == PERIPH_ID_SDMMC1) {
 534                 tap_value = 4;                  /* default */
 535                 if (val)
 536                         tap_value = 3;
 537                 trim_value = 2;
 538         } else {                                /* SDMMC3 */
 539                 tap_value = 3;
 540                 trim_value = 3;
 541         }
 542
 543         val = readl(&priv->reg->venclkctl);
 544         val &= ~TRIM_VAL_MASK;
 545         val |= (trim_value << TRIM_VAL_SHIFT);
 546         val &= ~TAP_VAL_MASK;
 547         val |= (tap_value << TAP_VAL_SHIFT);
 548         writel(val, &priv->reg->venclkctl);
 549         debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val);
 550 #endif  /* T210 */
 551 #endif  /* T30/T210 */
 552 }
 553
 554 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
 555 {
 556         unsigned int timeout;
 557         debug(" mmc_reset called\n");
 558
 559         /*
 560          * RSTALL[0] : Software reset for all
 561          * 1 = reset
 562          * 0 = work
 563          */
 564         writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
 565
 566         priv->clock = 0;
 567
 568         /* Wait max 100 ms */
 569         timeout = 100;
 570
 571         /* hw clears the bit when it's done */
 572         while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
 573                 if (timeout == 0) {
 574                         printf("%s: timeout error\n", __func__);
 575                         return;
 576                 }
 577                 timeout--;
 578                 udelay(1000);
 579         }
 580
 581         /* Set SD bus voltage & enable bus power */
 582         tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
 583         debug("%s: power control = %02X, host control = %02X\n", __func__,
 584                 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
 585
 586         /* Make sure SDIO pads are set up */
 587         tegra_mmc_pad_init(priv);
 588 }
 589
 590 static int tegra_mmc_init(struct udevice *dev)
 591 {
 592         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 593         struct mmc *mmc = mmc_get_mmc_dev(dev);
 594         unsigned int mask;
 595         debug(" tegra_mmc_init called\n");
 596
 597 #if defined(CONFIG_TEGRA210)
 598         priv->mmc_id = clock_decode_periph_id(dev);
 599         if (priv->mmc_id == PERIPH_ID_NONE) {
 600                 printf("%s: Missing/invalid peripheral ID\n", __func__);
 601                 return -EINVAL;
 602         }
 603 #endif
 604         tegra_mmc_reset(priv, mmc);
 605
 606 #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
 607         /*
 608          * Disable the external clock loopback and use the internal one on
 609          * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
 610          * bits being set to 0xfffd according to the TRM.
 611          *
 612          * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
 613          * approach once proper kernel integration made it mainline.
 614          */
 615         if (priv->reg == (void *)0x700b0400) {
 616                 mask = readl(&priv->reg->venmiscctl);
 617                 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
 618                 writel(mask, &priv->reg->venmiscctl);
 619         }
 620 #endif
 621
 622         priv->version = readw(&priv->reg->hcver);
 623         debug("host version = %x\n", priv->version);
 624
 625         /* mask all */
 626         writel(0xffffffff, &priv->reg->norintstsen);
 627         writel(0xffffffff, &priv->reg->norintsigen);
 628
 629         writeb(0xe, &priv->reg->timeoutcon);    /* TMCLK * 2^27 */
 630         /*
 631          * NORMAL Interrupt Status Enable Register init
 632          * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
 633          * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
 634          * [3] ENSTADMAINT   : DMA boundary interrupt
 635          * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
 636          * [0] ENSTACMDCMPLT : Command Complete Status Enable
 637         */
 638         mask = readl(&priv->reg->norintstsen);
 639         mask &= ~(0xffff);
 640         mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
 641                  TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
 642                  TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
 643                  TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
 644                  TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
 645         writel(mask, &priv->reg->norintstsen);
 646
 647         /*
 648          * NORMAL Interrupt Signal Enable Register init
 649          * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
 650          */
 651         mask = readl(&priv->reg->norintsigen);
 652         mask &= ~(0xffff);
 653         mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
 654         writel(mask, &priv->reg->norintsigen);
 655
 656         return 0;
 657 }
 658
 659 static int tegra_mmc_getcd(struct udevice *dev)
 660 {
 661         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 662
 663         debug("tegra_mmc_getcd called\n");
 664
 665         if (dm_gpio_is_valid(&priv->cd_gpio))
 666                 return dm_gpio_get_value(&priv->cd_gpio);
 667
 668         return 1;
 669 }
 670
 671 static const struct dm_mmc_ops tegra_mmc_ops = {
 672         .send_cmd       = tegra_mmc_send_cmd,
 673         .set_ios        = tegra_mmc_set_ios,
 674         .get_cd         = tegra_mmc_getcd,
 675 };
 676
 677 static int tegra_mmc_probe(struct udevice *dev)
 678 {
 679         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 680         struct tegra_mmc_plat *plat = dev_get_platdata(dev);
 681         struct tegra_mmc_priv *priv = dev_get_priv(dev);
 682         struct mmc_config *cfg = &plat->cfg;
 683         int bus_width, ret;
 684
 685         cfg->name = dev->name;
 686
 687         bus_width = dev_read_u32_default(dev, "bus-width", 1);
 688
 689         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 690         cfg->host_caps = 0;
 691         if (bus_width == 8)
 692                 cfg->host_caps |= MMC_MODE_8BIT;
 693         if (bus_width >= 4)
 694                 cfg->host_caps |= MMC_MODE_4BIT;
 695         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 696
 697         /*
 698          * min freq is for card identification, and is the highest
 699          *  low-speed SDIO card frequency (actually 400KHz)
 700          * max freq is highest HS eMMC clock as per the SD/MMC spec
 701          *  (actually 52MHz)
 702          */
 703         cfg->f_min = 375000;
 704         cfg->f_max = 48000000;
 705
 706         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 707
 708         priv->reg = (void *)dev_read_addr(dev);
 709
 710         ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
 711         if (ret) {
 712                 debug("reset_get_by_name() failed: %d\n", ret);
 713                 return ret;
 714         }
 715         ret = clk_get_by_index(dev, 0, &priv->clk);
 716         if (ret) {
 717                 debug("clk_get_by_index() failed: %d\n", ret);
 718                 return ret;
 719         }
 720
 721         ret = reset_assert(&priv->reset_ctl);
 722         if (ret)
 723                 return ret;
 724         ret = clk_enable(&priv->clk);
 725         if (ret)
 726                 return ret;
 727         ret = clk_set_rate(&priv->clk, 20000000);
 728         if (IS_ERR_VALUE(ret))
 729                 return ret;
 730         ret = reset_deassert(&priv->reset_ctl);
 731         if (ret)
 732                 return ret;
 733
 734         /* These GPIOs are optional */
 735         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
 736         gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
 737         gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
 738                              GPIOD_IS_OUT);
 739         if (dm_gpio_is_valid(&priv->pwr_gpio))
 740                 dm_gpio_set_value(&priv->pwr_gpio, 1);
 741
 742         upriv->mmc = &plat->mmc;
 743
 744         return tegra_mmc_init(dev);
 745 }
 746
 747 static int tegra_mmc_bind(struct udevice *dev)
 748 {
 749         struct tegra_mmc_plat *plat = dev_get_platdata(dev);
 750
 751         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 752 }
 753
 754 static const struct udevice_id tegra_mmc_ids[] = {
 755         { .compatible = "nvidia,tegra20-sdhci" },
 756         { .compatible = "nvidia,tegra30-sdhci" },
 757         { .compatible = "nvidia,tegra114-sdhci" },
 758         { .compatible = "nvidia,tegra124-sdhci" },
 759         { .compatible = "nvidia,tegra210-sdhci" },
 760         { .compatible = "nvidia,tegra186-sdhci" },
 761         { }
 762 };
 763
 764 U_BOOT_DRIVER(tegra_mmc_drv) = {
 765         .name           = "tegra_mmc",
 766         .id             = UCLASS_MMC,
 767         .of_match       = tegra_mmc_ids,
 768         .bind           = tegra_mmc_bind,
 769         .probe          = tegra_mmc_probe,
 770         .ops            = &tegra_mmc_ops,
 771         .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
 772         .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
 773 };