2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 * Portions Copyright 2011 NVIDIA Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <asm/arch/clk_rst.h>
26 #include <asm/arch/clock.h>
27 #include "tegra2_mmc.h"
29 /* support 4 mmc hosts */
30 struct mmc mmc_dev[4];
31 struct mmc_host mmc_host[4];
35 * Get the host address and peripheral ID for a device. Devices are numbered
38 * @param host Structure to fill in (base, reg, mmc_id)
39 * @param dev_index Device index (0-3)
41 static void tegra2_get_setup(struct mmc_host *host, int dev_index)
43 debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
47 host->base = TEGRA2_SDMMC3_BASE;
48 host->mmc_id = PERIPH_ID_SDMMC3;
51 host->base = TEGRA2_SDMMC2_BASE;
52 host->mmc_id = PERIPH_ID_SDMMC2;
55 host->base = TEGRA2_SDMMC1_BASE;
56 host->mmc_id = PERIPH_ID_SDMMC1;
60 host->base = TEGRA2_SDMMC4_BASE;
61 host->mmc_id = PERIPH_ID_SDMMC4;
65 host->reg = (struct tegra2_mmc *)host->base;
68 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
72 debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
73 (u32)data->dest, data->blocks, data->blocksize);
75 writel((u32)data->dest, &host->reg->sysad);
80 * 10 = Selects 32-bit Address ADMA2
81 * 11 = Selects 64-bit Address ADMA2
83 ctrl = readb(&host->reg->hostctl);
84 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
85 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
86 writeb(ctrl, &host->reg->hostctl);
88 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
89 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
90 writew(data->blocks, &host->reg->blkcnt);
93 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
96 debug(" mmc_set_transfer_mode called\n");
99 * MUL1SIN0[5] : Multi/Single Block Select
100 * RD1WT0[4] : Data Transfer Direction Select
103 * ENACMD12[2] : Auto CMD12 Enable
104 * ENBLKCNT[1] : Block Count Enable
105 * ENDMA[0] : DMA Enable
107 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
108 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
110 if (data->blocks > 1)
111 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
113 if (data->flags & MMC_DATA_READ)
114 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
116 writew(mode, &host->reg->trnmod);
119 static int mmc_wait_inhibit(struct mmc_host *host,
121 struct mmc_data *data,
122 unsigned int timeout)
126 * CMDINHDAT[1] : Command Inhibit (DAT)
127 * CMDINHCMD[0] : Command Inhibit (CMD)
129 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
132 * We shouldn't wait for data inhibit for stop commands, even
133 * though they might use busy signaling
135 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
136 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
138 while (readl(&host->reg->prnsts) & mask) {
140 printf("%s: timeout error\n", __func__);
150 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
151 struct mmc_data *data)
153 struct mmc_host *host = (struct mmc_host *)mmc->priv;
157 unsigned int retry = 0x100000;
158 debug(" mmc_send_cmd called\n");
160 result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
166 mmc_prepare_data(host, data);
168 debug("cmd->arg: %08x\n", cmd->cmdarg);
169 writel(cmd->cmdarg, &host->reg->argument);
172 mmc_set_transfer_mode(host, data);
174 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
179 * CMDIDX[13:8] : Command index
180 * DATAPRNT[5] : Data Present Select
181 * ENCMDIDX[4] : Command Index Check Enable
182 * ENCMDCRC[3] : Command CRC Check Enable
187 * 11 = Length 48 Check busy after response
189 if (!(cmd->resp_type & MMC_RSP_PRESENT))
190 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
191 else if (cmd->resp_type & MMC_RSP_136)
192 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
193 else if (cmd->resp_type & MMC_RSP_BUSY)
194 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
196 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
198 if (cmd->resp_type & MMC_RSP_CRC)
199 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
200 if (cmd->resp_type & MMC_RSP_OPCODE)
201 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
203 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
205 debug("cmd: %d\n", cmd->cmdidx);
207 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
209 for (i = 0; i < retry; i++) {
210 mask = readl(&host->reg->norintsts);
211 /* Command Complete */
212 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
214 writel(mask, &host->reg->norintsts);
220 printf("%s: waiting for status update\n", __func__);
224 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
226 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
228 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
229 /* Error Interrupt */
230 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
234 if (cmd->resp_type & MMC_RSP_PRESENT) {
235 if (cmd->resp_type & MMC_RSP_136) {
236 /* CRC is stripped so we need to do some shifting. */
237 for (i = 0; i < 4; i++) {
238 unsigned int offset =
239 (unsigned int)(&host->reg->rspreg3 - i);
240 cmd->response[i] = readl(offset) << 8;
246 debug("cmd->resp[%d]: %08x\n",
247 i, cmd->response[i]);
249 } else if (cmd->resp_type & MMC_RSP_BUSY) {
250 for (i = 0; i < retry; i++) {
251 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
252 if (readl(&host->reg->prnsts)
253 & (1 << 20)) /* DAT[0] */
258 printf("%s: card is still busy\n", __func__);
262 cmd->response[0] = readl(&host->reg->rspreg0);
263 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
265 cmd->response[0] = readl(&host->reg->rspreg0);
266 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
271 unsigned long start = get_timer(0);
274 mask = readl(&host->reg->norintsts);
276 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
277 /* Error Interrupt */
278 writel(mask, &host->reg->norintsts);
279 printf("%s: error during transfer: 0x%08x\n",
282 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
284 * DMA Interrupt, restart the transfer where
285 * it was interrupted.
287 unsigned int address = readl(&host->reg->sysad);
290 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
291 &host->reg->norintsts);
292 writel(address, &host->reg->sysad);
293 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
294 /* Transfer Complete */
295 debug("r/w is done\n");
297 } else if (get_timer(start) > 2000UL) {
298 writel(mask, &host->reg->norintsts);
299 printf("%s: MMC Timeout\n"
300 " Interrupt status 0x%08x\n"
301 " Interrupt status enable 0x%08x\n"
302 " Interrupt signal enable 0x%08x\n"
303 " Present status 0x%08x\n",
305 readl(&host->reg->norintstsen),
306 readl(&host->reg->norintsigen),
307 readl(&host->reg->prnsts));
311 writel(mask, &host->reg->norintsts);
318 static void mmc_change_clock(struct mmc_host *host, uint clock)
322 unsigned long timeout;
324 debug(" mmc_change_clock called\n");
327 * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
332 clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
334 debug("div = %d\n", div);
336 writew(0, &host->reg->clkcon);
340 * SELFREQ[15:8] : base clock divided by value
341 * ENSDCLK[2] : SD Clock Enable
342 * STBLINTCLK[1] : Internal Clock Stable
343 * ENINTCLK[0] : Internal Clock Enable
346 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
347 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
348 writew(clk, &host->reg->clkcon);
352 while (!(readw(&host->reg->clkcon) &
353 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
355 printf("%s: timeout error\n", __func__);
362 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
363 writew(clk, &host->reg->clkcon);
365 debug("mmc_change_clock: clkcon = %08X\n", clk);
371 static void mmc_set_ios(struct mmc *mmc)
373 struct mmc_host *host = mmc->priv;
375 debug(" mmc_set_ios called\n");
377 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
379 /* Change clock first */
380 mmc_change_clock(host, mmc->clock);
382 ctrl = readb(&host->reg->hostctl);
386 * 0 = Depend on WIDE4
392 if (mmc->bus_width == 8)
394 else if (mmc->bus_width == 4)
399 writeb(ctrl, &host->reg->hostctl);
400 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
403 static void mmc_reset(struct mmc_host *host)
405 unsigned int timeout;
406 debug(" mmc_reset called\n");
409 * RSTALL[0] : Software reset for all
413 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
417 /* Wait max 100 ms */
420 /* hw clears the bit when it's done */
421 while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
423 printf("%s: timeout error\n", __func__);
431 static int mmc_core_init(struct mmc *mmc)
433 struct mmc_host *host = (struct mmc_host *)mmc->priv;
435 debug(" mmc_core_init called\n");
439 host->version = readw(&host->reg->hcver);
440 debug("host version = %x\n", host->version);
443 writel(0xffffffff, &host->reg->norintstsen);
444 writel(0xffffffff, &host->reg->norintsigen);
446 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
448 * NORMAL Interrupt Status Enable Register init
449 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
450 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
451 * [3] ENSTADMAINT : DMA boundary interrupt
452 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
453 * [0] ENSTACMDCMPLT : Command Complete Status Enable
455 mask = readl(&host->reg->norintstsen);
457 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
458 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
459 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
460 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
461 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
462 writel(mask, &host->reg->norintstsen);
465 * NORMAL Interrupt Signal Enable Register init
466 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
468 mask = readl(&host->reg->norintsigen);
470 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
471 writel(mask, &host->reg->norintsigen);
476 static int tegra2_mmc_initialize(int dev_index, int bus_width)
478 struct mmc_host *host;
481 debug(" mmc_initialize called\n");
483 host = &mmc_host[dev_index];
486 tegra2_get_setup(host, dev_index);
488 clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
490 mmc = &mmc_dev[dev_index];
492 sprintf(mmc->name, "Tegra2 SD/MMC");
494 mmc->send_cmd = mmc_send_cmd;
495 mmc->set_ios = mmc_set_ios;
496 mmc->init = mmc_core_init;
498 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
500 mmc->host_caps = MMC_MODE_8BIT;
502 mmc->host_caps = MMC_MODE_4BIT;
503 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
506 * min freq is for card identification, and is the highest
507 * low-speed SDIO card frequency (actually 400KHz)
508 * max freq is highest HS eMMC clock as per the SD/MMC spec
510 * Both of these are the closest equivalents w/216MHz source
511 * clock and Tegra2 SDMMC divisors.
514 mmc->f_max = 48000000;
521 int tegra2_mmc_init(int dev_index, int bus_width)
523 debug(" tegra2_mmc_init: index %d, bus width %d\n",
524 dev_index, bus_width);
525 return tegra2_mmc_initialize(dev_index, bus_width);