2 * (C) Copyright 2009 SAMSUNG Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Jaehoon Chung <jh80.chung@samsung.com>
5 * Portions Copyright 2011 NVIDIA Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <asm/arch/clk_rst.h>
27 #include <asm/arch/clock.h>
28 #include "tegra2_mmc.h"
30 /* support 4 mmc hosts */
31 struct mmc mmc_dev[4];
32 struct mmc_host mmc_host[4];
36 * Get the host address and peripheral ID for a device. Devices are numbered
39 * @param host Structure to fill in (base, reg, mmc_id)
40 * @param dev_index Device index (0-3)
42 static void tegra2_get_setup(struct mmc_host *host, int dev_index)
44 debug("tegra2_get_base_mmc: dev_index = %d\n", dev_index);
48 host->base = TEGRA2_SDMMC3_BASE;
49 host->mmc_id = PERIPH_ID_SDMMC3;
52 host->base = TEGRA2_SDMMC2_BASE;
53 host->mmc_id = PERIPH_ID_SDMMC2;
56 host->base = TEGRA2_SDMMC1_BASE;
57 host->mmc_id = PERIPH_ID_SDMMC1;
61 host->base = TEGRA2_SDMMC4_BASE;
62 host->mmc_id = PERIPH_ID_SDMMC4;
66 host->reg = (struct tegra2_mmc *)host->base;
69 static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
73 debug("data->dest: %08X, data->blocks: %u, data->blocksize: %u\n",
74 (u32)data->dest, data->blocks, data->blocksize);
76 writel((u32)data->dest, &host->reg->sysad);
81 * 10 = Selects 32-bit Address ADMA2
82 * 11 = Selects 64-bit Address ADMA2
84 ctrl = readb(&host->reg->hostctl);
85 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
86 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
87 writeb(ctrl, &host->reg->hostctl);
89 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
90 writew((7 << 12) | (data->blocksize & 0xFFF), &host->reg->blksize);
91 writew(data->blocks, &host->reg->blkcnt);
94 static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
97 debug(" mmc_set_transfer_mode called\n");
100 * MUL1SIN0[5] : Multi/Single Block Select
101 * RD1WT0[4] : Data Transfer Direction Select
104 * ENACMD12[2] : Auto CMD12 Enable
105 * ENBLKCNT[1] : Block Count Enable
106 * ENDMA[0] : DMA Enable
108 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
109 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
111 if (data->blocks > 1)
112 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
114 if (data->flags & MMC_DATA_READ)
115 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
117 writew(mode, &host->reg->trnmod);
120 static int mmc_wait_inhibit(struct mmc_host *host,
122 struct mmc_data *data,
123 unsigned int timeout)
127 * CMDINHDAT[1] : Command Inhibit (DAT)
128 * CMDINHCMD[0] : Command Inhibit (CMD)
130 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
133 * We shouldn't wait for data inhibit for stop commands, even
134 * though they might use busy signaling
136 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
137 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
139 while (readl(&host->reg->prnsts) & mask) {
141 printf("%s: timeout error\n", __func__);
151 static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
152 struct mmc_data *data)
154 struct mmc_host *host = (struct mmc_host *)mmc->priv;
158 unsigned int retry = 0x100000;
159 debug(" mmc_send_cmd called\n");
161 result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
167 mmc_prepare_data(host, data);
169 debug("cmd->arg: %08x\n", cmd->cmdarg);
170 writel(cmd->cmdarg, &host->reg->argument);
173 mmc_set_transfer_mode(host, data);
175 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
180 * CMDIDX[13:8] : Command index
181 * DATAPRNT[5] : Data Present Select
182 * ENCMDIDX[4] : Command Index Check Enable
183 * ENCMDCRC[3] : Command CRC Check Enable
188 * 11 = Length 48 Check busy after response
190 if (!(cmd->resp_type & MMC_RSP_PRESENT))
191 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
192 else if (cmd->resp_type & MMC_RSP_136)
193 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
194 else if (cmd->resp_type & MMC_RSP_BUSY)
195 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
197 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
199 if (cmd->resp_type & MMC_RSP_CRC)
200 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
201 if (cmd->resp_type & MMC_RSP_OPCODE)
202 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
204 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
206 debug("cmd: %d\n", cmd->cmdidx);
208 writew((cmd->cmdidx << 8) | flags, &host->reg->cmdreg);
210 for (i = 0; i < retry; i++) {
211 mask = readl(&host->reg->norintsts);
212 /* Command Complete */
213 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
215 writel(mask, &host->reg->norintsts);
221 printf("%s: waiting for status update\n", __func__);
225 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
227 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
229 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
230 /* Error Interrupt */
231 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
235 if (cmd->resp_type & MMC_RSP_PRESENT) {
236 if (cmd->resp_type & MMC_RSP_136) {
237 /* CRC is stripped so we need to do some shifting. */
238 for (i = 0; i < 4; i++) {
239 unsigned int offset =
240 (unsigned int)(&host->reg->rspreg3 - i);
241 cmd->response[i] = readl(offset) << 8;
247 debug("cmd->resp[%d]: %08x\n",
248 i, cmd->response[i]);
250 } else if (cmd->resp_type & MMC_RSP_BUSY) {
251 for (i = 0; i < retry; i++) {
252 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
253 if (readl(&host->reg->prnsts)
254 & (1 << 20)) /* DAT[0] */
259 printf("%s: card is still busy\n", __func__);
263 cmd->response[0] = readl(&host->reg->rspreg0);
264 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
266 cmd->response[0] = readl(&host->reg->rspreg0);
267 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
272 unsigned long start = get_timer(0);
275 mask = readl(&host->reg->norintsts);
277 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
278 /* Error Interrupt */
279 writel(mask, &host->reg->norintsts);
280 printf("%s: error during transfer: 0x%08x\n",
283 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
285 * DMA Interrupt, restart the transfer where
286 * it was interrupted.
288 unsigned int address = readl(&host->reg->sysad);
291 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
292 &host->reg->norintsts);
293 writel(address, &host->reg->sysad);
294 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
295 /* Transfer Complete */
296 debug("r/w is done\n");
298 } else if (get_timer(start) > 2000UL) {
299 writel(mask, &host->reg->norintsts);
300 printf("%s: MMC Timeout\n"
301 " Interrupt status 0x%08x\n"
302 " Interrupt status enable 0x%08x\n"
303 " Interrupt signal enable 0x%08x\n"
304 " Present status 0x%08x\n",
306 readl(&host->reg->norintstsen),
307 readl(&host->reg->norintsigen),
308 readl(&host->reg->prnsts));
312 writel(mask, &host->reg->norintsts);
319 static void mmc_change_clock(struct mmc_host *host, uint clock)
323 unsigned long timeout;
325 debug(" mmc_change_clock called\n");
328 * Change Tegra2 SDMMCx clock divisor here. Source is 216MHz,
333 clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock,
335 debug("div = %d\n", div);
337 writew(0, &host->reg->clkcon);
341 * SELFREQ[15:8] : base clock divided by value
342 * ENSDCLK[2] : SD Clock Enable
343 * STBLINTCLK[1] : Internal Clock Stable
344 * ENINTCLK[0] : Internal Clock Enable
347 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
348 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
349 writew(clk, &host->reg->clkcon);
353 while (!(readw(&host->reg->clkcon) &
354 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
356 printf("%s: timeout error\n", __func__);
363 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
364 writew(clk, &host->reg->clkcon);
366 debug("mmc_change_clock: clkcon = %08X\n", clk);
372 static void mmc_set_ios(struct mmc *mmc)
374 struct mmc_host *host = mmc->priv;
376 debug(" mmc_set_ios called\n");
378 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
380 /* Change clock first */
381 mmc_change_clock(host, mmc->clock);
383 ctrl = readb(&host->reg->hostctl);
387 * 0 = Depend on WIDE4
393 if (mmc->bus_width == 8)
395 else if (mmc->bus_width == 4)
400 writeb(ctrl, &host->reg->hostctl);
401 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
404 static void mmc_reset(struct mmc_host *host)
406 unsigned int timeout;
407 debug(" mmc_reset called\n");
410 * RSTALL[0] : Software reset for all
414 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
418 /* Wait max 100 ms */
421 /* hw clears the bit when it's done */
422 while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
424 printf("%s: timeout error\n", __func__);
432 static int mmc_core_init(struct mmc *mmc)
434 struct mmc_host *host = (struct mmc_host *)mmc->priv;
436 debug(" mmc_core_init called\n");
440 host->version = readw(&host->reg->hcver);
441 debug("host version = %x\n", host->version);
444 writel(0xffffffff, &host->reg->norintstsen);
445 writel(0xffffffff, &host->reg->norintsigen);
447 writeb(0xe, &host->reg->timeoutcon); /* TMCLK * 2^27 */
449 * NORMAL Interrupt Status Enable Register init
450 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
451 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
452 * [3] ENSTADMAINT : DMA boundary interrupt
453 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
454 * [0] ENSTACMDCMPLT : Command Complete Status Enable
456 mask = readl(&host->reg->norintstsen);
458 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
459 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
460 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
461 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
462 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
463 writel(mask, &host->reg->norintstsen);
466 * NORMAL Interrupt Signal Enable Register init
467 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
469 mask = readl(&host->reg->norintsigen);
471 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
472 writel(mask, &host->reg->norintsigen);
477 int tegra2_mmc_init(int dev_index, int bus_width, int pwr_gpio, int cd_gpio)
479 struct mmc_host *host;
480 char gpusage[12]; /* "SD/MMCn PWR" or "SD/MMCn CD" */
483 debug(" tegra2_mmc_init: index %d, bus width %d "
484 "pwr_gpio %d cd_gpio %d\n",
485 dev_index, bus_width, pwr_gpio, cd_gpio);
487 host = &mmc_host[dev_index];
490 host->pwr_gpio = pwr_gpio;
491 host->cd_gpio = cd_gpio;
492 tegra2_get_setup(host, dev_index);
494 clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000);
496 if (host->pwr_gpio >= 0) {
497 sprintf(gpusage, "SD/MMC%d PWR", dev_index);
498 gpio_request(host->pwr_gpio, gpusage);
499 gpio_direction_output(host->pwr_gpio, 1);
502 if (host->cd_gpio >= 0) {
503 sprintf(gpusage, "SD/MMC%d CD", dev_index);
504 gpio_request(host->cd_gpio, gpusage);
505 gpio_direction_input(host->cd_gpio);
508 mmc = &mmc_dev[dev_index];
510 sprintf(mmc->name, "Tegra2 SD/MMC");
512 mmc->send_cmd = mmc_send_cmd;
513 mmc->set_ios = mmc_set_ios;
514 mmc->init = mmc_core_init;
516 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
518 mmc->host_caps = MMC_MODE_8BIT;
520 mmc->host_caps = MMC_MODE_4BIT;
521 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
524 * min freq is for card identification, and is the highest
525 * low-speed SDIO card frequency (actually 400KHz)
526 * max freq is highest HS eMMC clock as per the SD/MMC spec
528 * Both of these are the closest equivalents w/216MHz source
529 * clock and Tegra2 SDMMC divisors.
532 mmc->f_max = 48000000;
539 /* this is a weak define that we are overriding */
540 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
542 struct mmc_host *host = (struct mmc_host *)mmc->priv;
544 debug("board_mmc_getcd called\n");
546 *cd = 1; /* Assume card is inserted, or eMMC */
549 if (host->cd_gpio >= 0) {
550 if (gpio_get_value(host->cd_gpio))