2 * (C) Copyright 2007-2011
3 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
4 * Aaron <leafy.myeh@allwinnertech.com>
6 * MMC driver for allwinner sunxi platform.
8 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc.h>
21 #include <asm-generic/gpio.h>
23 struct sunxi_mmc_plat {
24 struct mmc_config cfg;
28 struct sunxi_mmc_priv {
32 struct gpio_desc cd_gpio; /* Change Detect GPIO */
33 int cd_inverted; /* Inverted Card Detect */
34 struct sunxi_mmc *reg;
35 struct mmc_config cfg;
38 #if !CONFIG_IS_ENABLED(DM_MMC)
39 /* support 4 mmc hosts */
40 struct sunxi_mmc_priv mmc_host[4];
42 static int sunxi_mmc_getcd_gpio(int sdc_no)
45 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
46 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
47 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
48 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
53 static int mmc_resource_init(int sdc_no)
55 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
56 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
59 debug("init mmc %d resource\n", sdc_no);
63 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
64 priv->mclkreg = &ccm->sd0_clk_cfg;
67 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
68 priv->mclkreg = &ccm->sd1_clk_cfg;
71 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
72 priv->mclkreg = &ccm->sd2_clk_cfg;
75 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
76 priv->mclkreg = &ccm->sd3_clk_cfg;
79 printf("Wrong mmc number %d\n", sdc_no);
82 priv->mmc_no = sdc_no;
84 cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
86 ret = gpio_request(cd_pin, "mmc_cd");
88 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
89 ret = gpio_direction_input(cd_pin);
97 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
99 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
100 bool new_mode = false;
103 if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
107 * The MMC clock has an extra /2 post-divider when operating in the new
113 if (hz <= 24000000) {
114 pll = CCM_MMC_CTRL_OSCM24;
117 #ifdef CONFIG_MACH_SUN9I
118 pll = CCM_MMC_CTRL_PLL_PERIPH0;
119 pll_hz = clock_get_pll4_periph0();
121 pll = CCM_MMC_CTRL_PLL6;
122 pll_hz = clock_get_pll6();
137 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
142 /* determine delays */
146 } else if (hz <= 25000000) {
149 #ifdef CONFIG_MACH_SUN9I
150 } else if (hz <= 52000000) {
158 } else if (hz <= 52000000) {
169 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
170 val = CCM_MMC_CTRL_MODE_SEL_NEW;
171 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
174 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
175 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
178 writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
179 CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
181 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
182 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
187 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
190 unsigned timeout_msecs = 2000;
191 unsigned long start = get_timer(0);
193 cmd = SUNXI_MMC_CMD_START |
194 SUNXI_MMC_CMD_UPCLK_ONLY |
195 SUNXI_MMC_CMD_WAIT_PRE_OVER;
197 writel(cmd, &priv->reg->cmd);
198 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
199 if (get_timer(start) > timeout_msecs)
203 /* clock update sets various irq status bits, clear these */
204 writel(readl(&priv->reg->rint), &priv->reg->rint);
209 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
211 unsigned rval = readl(&priv->reg->clkcr);
214 rval &= ~SUNXI_MMC_CLK_ENABLE;
215 writel(rval, &priv->reg->clkcr);
216 if (mmc_update_clk(priv))
219 /* Set mod_clk to new rate */
220 if (mmc_set_mod_clk(priv, mmc->clock))
223 /* Clear internal divider */
224 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
225 writel(rval, &priv->reg->clkcr);
227 /* Re-enable Clock */
228 rval |= SUNXI_MMC_CLK_ENABLE;
229 writel(rval, &priv->reg->clkcr);
230 if (mmc_update_clk(priv))
236 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
239 debug("set ios: bus_width: %x, clock: %d\n",
240 mmc->bus_width, mmc->clock);
242 /* Change clock first */
243 if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
248 /* Change bus width */
249 if (mmc->bus_width == 8)
250 writel(0x2, &priv->reg->width);
251 else if (mmc->bus_width == 4)
252 writel(0x1, &priv->reg->width);
254 writel(0x0, &priv->reg->width);
259 #if !CONFIG_IS_ENABLED(DM_MMC)
260 static int sunxi_mmc_core_init(struct mmc *mmc)
262 struct sunxi_mmc_priv *priv = mmc->priv;
264 /* Reset controller */
265 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
272 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
273 struct mmc_data *data)
275 const int reading = !!(data->flags & MMC_DATA_READ);
276 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
277 SUNXI_MMC_STATUS_FIFO_FULL;
279 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
280 unsigned byte_cnt = data->blocksize * data->blocks;
281 unsigned timeout_msecs = byte_cnt >> 8;
284 if (timeout_msecs < 2000)
285 timeout_msecs = 2000;
287 /* Always read / write data through the CPU */
288 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
290 start = get_timer(0);
292 for (i = 0; i < (byte_cnt >> 2); i++) {
293 while (readl(&priv->reg->status) & status_bit) {
294 if (get_timer(start) > timeout_msecs)
299 buff[i] = readl(&priv->reg->fifo);
301 writel(buff[i], &priv->reg->fifo);
307 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
308 uint timeout_msecs, uint done_bit, const char *what)
311 unsigned long start = get_timer(0);
314 status = readl(&priv->reg->rint);
315 if ((get_timer(start) > timeout_msecs) ||
316 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
317 debug("%s timeout %x\n", what,
318 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
321 } while (!(status & done_bit));
326 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
327 struct mmc *mmc, struct mmc_cmd *cmd,
328 struct mmc_data *data)
330 unsigned int cmdval = SUNXI_MMC_CMD_START;
331 unsigned int timeout_msecs;
333 unsigned int status = 0;
334 unsigned int bytecnt = 0;
338 if (cmd->resp_type & MMC_RSP_BUSY)
339 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
340 if (cmd->cmdidx == 12)
344 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
345 if (cmd->resp_type & MMC_RSP_PRESENT)
346 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
347 if (cmd->resp_type & MMC_RSP_136)
348 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
349 if (cmd->resp_type & MMC_RSP_CRC)
350 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
353 if ((u32)(long)data->dest & 0x3) {
358 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
359 if (data->flags & MMC_DATA_WRITE)
360 cmdval |= SUNXI_MMC_CMD_WRITE;
361 if (data->blocks > 1)
362 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
363 writel(data->blocksize, &priv->reg->blksz);
364 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
367 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
368 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
369 writel(cmd->cmdarg, &priv->reg->arg);
372 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
375 * transfer data and check status
376 * STATREG[2] : FIFO empty
377 * STATREG[3] : FIFO full
382 bytecnt = data->blocksize * data->blocks;
383 debug("trans data %d bytes\n", bytecnt);
384 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
385 ret = mmc_trans_data_by_cpu(priv, mmc, data);
387 error = readl(&priv->reg->rint) &
388 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
394 error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
401 debug("cacl timeout %x msec\n", timeout_msecs);
402 error = mmc_rint_wait(priv, mmc, timeout_msecs,
404 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
405 SUNXI_MMC_RINT_DATA_OVER,
411 if (cmd->resp_type & MMC_RSP_BUSY) {
412 unsigned long start = get_timer(0);
413 timeout_msecs = 2000;
416 status = readl(&priv->reg->status);
417 if (get_timer(start) > timeout_msecs) {
418 debug("busy timeout\n");
422 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
425 if (cmd->resp_type & MMC_RSP_136) {
426 cmd->response[0] = readl(&priv->reg->resp3);
427 cmd->response[1] = readl(&priv->reg->resp2);
428 cmd->response[2] = readl(&priv->reg->resp1);
429 cmd->response[3] = readl(&priv->reg->resp0);
430 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
431 cmd->response[3], cmd->response[2],
432 cmd->response[1], cmd->response[0]);
434 cmd->response[0] = readl(&priv->reg->resp0);
435 debug("mmc resp 0x%08x\n", cmd->response[0]);
439 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
440 mmc_update_clk(priv);
442 writel(0xffffffff, &priv->reg->rint);
443 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
449 #if !CONFIG_IS_ENABLED(DM_MMC)
450 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
452 struct sunxi_mmc_priv *priv = mmc->priv;
454 return sunxi_mmc_set_ios_common(priv, mmc);
457 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
458 struct mmc_data *data)
460 struct sunxi_mmc_priv *priv = mmc->priv;
462 return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
465 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
467 struct sunxi_mmc_priv *priv = mmc->priv;
470 cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
474 return !gpio_get_value(cd_pin);
477 static const struct mmc_ops sunxi_mmc_ops = {
478 .send_cmd = sunxi_mmc_send_cmd_legacy,
479 .set_ios = sunxi_mmc_set_ios_legacy,
480 .init = sunxi_mmc_core_init,
481 .getcd = sunxi_mmc_getcd_legacy,
484 struct mmc *sunxi_mmc_init(int sdc_no)
486 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
487 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
488 struct mmc_config *cfg = &priv->cfg;
491 memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
493 cfg->name = "SUNXI SD/MMC";
494 cfg->ops = &sunxi_mmc_ops;
496 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
497 cfg->host_caps = MMC_MODE_4BIT;
498 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I)
500 cfg->host_caps = MMC_MODE_8BIT;
502 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
503 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
506 cfg->f_max = 52000000;
508 if (mmc_resource_init(sdc_no) != 0)
511 /* config ahb clock */
512 debug("init mmc %d clock and io\n", sdc_no);
513 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
515 #ifdef CONFIG_SUNXI_GEN_SUN6I
517 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
519 #if defined(CONFIG_MACH_SUN9I)
520 /* sun9i has a mmc-common module, also set the gate and reset there */
521 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
522 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
524 ret = mmc_set_mod_clk(priv, 24000000);
528 return mmc_create(cfg, priv);
532 static int sunxi_mmc_set_ios(struct udevice *dev)
534 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
535 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
537 return sunxi_mmc_set_ios_common(priv, &plat->mmc);
540 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
541 struct mmc_data *data)
543 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
544 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
546 return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
549 static int sunxi_mmc_getcd(struct udevice *dev)
551 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
553 if (dm_gpio_is_valid(&priv->cd_gpio)) {
554 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
556 return cd_state ^ priv->cd_inverted;
561 static const struct dm_mmc_ops sunxi_mmc_ops = {
562 .send_cmd = sunxi_mmc_send_cmd,
563 .set_ios = sunxi_mmc_set_ios,
564 .get_cd = sunxi_mmc_getcd,
567 static int sunxi_mmc_probe(struct udevice *dev)
569 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
570 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
571 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
572 struct mmc_config *cfg = &plat->cfg;
573 struct ofnode_phandle_args args;
577 cfg->name = dev->name;
578 bus_width = dev_read_u32_default(dev, "bus-width", 1);
580 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
583 cfg->host_caps |= MMC_MODE_8BIT;
585 cfg->host_caps |= MMC_MODE_4BIT;
586 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
587 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
590 cfg->f_max = 52000000;
592 priv->reg = (void *)dev_read_addr(dev);
594 /* We don't have a sunxi clock driver so find the clock address here */
595 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
599 priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
601 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
605 gate_reg = (u32 *)ofnode_get_addr(args.node);
606 setbits_le32(gate_reg, 1 << args.args[0]);
607 priv->mmc_no = args.args[0] - 8;
609 ret = mmc_set_mod_clk(priv, 24000000);
613 /* This GPIO is optional */
614 if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
616 int cd_pin = gpio_get_number(&priv->cd_gpio);
618 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
621 /* Check if card detect is inverted */
622 priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
624 upriv->mmc = &plat->mmc;
626 /* Reset controller */
627 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
633 static int sunxi_mmc_bind(struct udevice *dev)
635 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
637 return mmc_bind(dev, &plat->mmc, &plat->cfg);
640 static const struct udevice_id sunxi_mmc_ids[] = {
641 { .compatible = "allwinner,sun5i-a13-mmc" },
645 U_BOOT_DRIVER(sunxi_mmc_drv) = {
648 .of_match = sunxi_mmc_ids,
649 .bind = sunxi_mmc_bind,
650 .probe = sunxi_mmc_probe,
651 .ops = &sunxi_mmc_ops,
652 .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
653 .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),