1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2011
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Aaron <leafy.myeh@allwinnertech.com>
7 * MMC driver for allwinner sunxi platform.
16 #include <asm/arch/clock.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/gpio.h>
19 #include <asm/arch/mmc.h>
20 #include <asm-generic/gpio.h>
22 struct sunxi_mmc_plat {
23 struct mmc_config cfg;
27 struct sunxi_mmc_priv {
31 struct gpio_desc cd_gpio; /* Change Detect GPIO */
32 int cd_inverted; /* Inverted Card Detect */
33 struct sunxi_mmc *reg;
34 struct mmc_config cfg;
37 #if !CONFIG_IS_ENABLED(DM_MMC)
38 /* support 4 mmc hosts */
39 struct sunxi_mmc_priv mmc_host[4];
41 static int sunxi_mmc_getcd_gpio(int sdc_no)
44 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
45 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
46 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
47 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
52 static int mmc_resource_init(int sdc_no)
54 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
55 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
58 debug("init mmc %d resource\n", sdc_no);
62 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
63 priv->mclkreg = &ccm->sd0_clk_cfg;
66 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
67 priv->mclkreg = &ccm->sd1_clk_cfg;
70 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
71 priv->mclkreg = &ccm->sd2_clk_cfg;
73 #ifdef SUNXI_MMC3_BASE
75 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
76 priv->mclkreg = &ccm->sd3_clk_cfg;
80 printf("Wrong mmc number %d\n", sdc_no);
83 priv->mmc_no = sdc_no;
85 cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
87 ret = gpio_request(cd_pin, "mmc_cd");
89 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
90 ret = gpio_direction_input(cd_pin);
98 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
100 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
101 bool new_mode = true;
102 bool calibrate = false;
105 if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
108 /* A83T support new mode only on eMMC */
109 if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
112 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
116 if (hz <= 24000000) {
117 pll = CCM_MMC_CTRL_OSCM24;
120 #ifdef CONFIG_MACH_SUN9I
121 pll = CCM_MMC_CTRL_PLL_PERIPH0;
122 pll_hz = clock_get_pll4_periph0();
123 #elif defined(CONFIG_MACH_SUN50I_H6)
124 pll = CCM_MMC_CTRL_PLL6X2;
125 pll_hz = clock_get_pll6() * 2;
127 pll = CCM_MMC_CTRL_PLL6;
128 pll_hz = clock_get_pll6();
143 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
148 /* determine delays */
152 } else if (hz <= 25000000) {
155 #ifdef CONFIG_MACH_SUN9I
156 } else if (hz <= 52000000) {
164 } else if (hz <= 52000000) {
175 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
176 #ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
177 val = CCM_MMC_CTRL_MODE_SEL_NEW;
179 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
181 } else if (!calibrate) {
183 * Use hardcoded delay values if controller doesn't support
186 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
187 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
190 writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
191 CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
193 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
194 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
199 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
202 unsigned timeout_msecs = 2000;
203 unsigned long start = get_timer(0);
205 cmd = SUNXI_MMC_CMD_START |
206 SUNXI_MMC_CMD_UPCLK_ONLY |
207 SUNXI_MMC_CMD_WAIT_PRE_OVER;
209 writel(cmd, &priv->reg->cmd);
210 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
211 if (get_timer(start) > timeout_msecs)
215 /* clock update sets various irq status bits, clear these */
216 writel(readl(&priv->reg->rint), &priv->reg->rint);
221 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
223 unsigned rval = readl(&priv->reg->clkcr);
226 rval &= ~SUNXI_MMC_CLK_ENABLE;
227 writel(rval, &priv->reg->clkcr);
228 if (mmc_update_clk(priv))
231 /* Set mod_clk to new rate */
232 if (mmc_set_mod_clk(priv, mmc->clock))
235 /* Clear internal divider */
236 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
237 writel(rval, &priv->reg->clkcr);
239 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
240 /* A64 supports calibration of delays on MMC controller and we
241 * have to set delay of zero before starting calibration.
242 * Allwinner BSP driver sets a delay only in the case of
243 * using HS400 which is not supported by mainline U-Boot or
244 * Linux at the moment
246 writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
249 /* Re-enable Clock */
250 rval |= SUNXI_MMC_CLK_ENABLE;
251 writel(rval, &priv->reg->clkcr);
252 if (mmc_update_clk(priv))
258 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
261 debug("set ios: bus_width: %x, clock: %d\n",
262 mmc->bus_width, mmc->clock);
264 /* Change clock first */
265 if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
270 /* Change bus width */
271 if (mmc->bus_width == 8)
272 writel(0x2, &priv->reg->width);
273 else if (mmc->bus_width == 4)
274 writel(0x1, &priv->reg->width);
276 writel(0x0, &priv->reg->width);
281 #if !CONFIG_IS_ENABLED(DM_MMC)
282 static int sunxi_mmc_core_init(struct mmc *mmc)
284 struct sunxi_mmc_priv *priv = mmc->priv;
286 /* Reset controller */
287 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
294 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
295 struct mmc_data *data)
297 const int reading = !!(data->flags & MMC_DATA_READ);
298 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
299 SUNXI_MMC_STATUS_FIFO_FULL;
301 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
302 unsigned byte_cnt = data->blocksize * data->blocks;
303 unsigned timeout_msecs = byte_cnt >> 8;
306 if (timeout_msecs < 2000)
307 timeout_msecs = 2000;
309 /* Always read / write data through the CPU */
310 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
312 start = get_timer(0);
314 for (i = 0; i < (byte_cnt >> 2); i++) {
315 while (readl(&priv->reg->status) & status_bit) {
316 if (get_timer(start) > timeout_msecs)
321 buff[i] = readl(&priv->reg->fifo);
323 writel(buff[i], &priv->reg->fifo);
329 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
330 uint timeout_msecs, uint done_bit, const char *what)
333 unsigned long start = get_timer(0);
336 status = readl(&priv->reg->rint);
337 if ((get_timer(start) > timeout_msecs) ||
338 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
339 debug("%s timeout %x\n", what,
340 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
343 } while (!(status & done_bit));
348 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
349 struct mmc *mmc, struct mmc_cmd *cmd,
350 struct mmc_data *data)
352 unsigned int cmdval = SUNXI_MMC_CMD_START;
353 unsigned int timeout_msecs;
355 unsigned int status = 0;
356 unsigned int bytecnt = 0;
360 if (cmd->resp_type & MMC_RSP_BUSY)
361 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
362 if (cmd->cmdidx == 12)
366 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
367 if (cmd->resp_type & MMC_RSP_PRESENT)
368 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
369 if (cmd->resp_type & MMC_RSP_136)
370 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
371 if (cmd->resp_type & MMC_RSP_CRC)
372 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
375 if ((u32)(long)data->dest & 0x3) {
380 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
381 if (data->flags & MMC_DATA_WRITE)
382 cmdval |= SUNXI_MMC_CMD_WRITE;
383 if (data->blocks > 1)
384 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
385 writel(data->blocksize, &priv->reg->blksz);
386 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
389 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
390 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
391 writel(cmd->cmdarg, &priv->reg->arg);
394 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
397 * transfer data and check status
398 * STATREG[2] : FIFO empty
399 * STATREG[3] : FIFO full
404 bytecnt = data->blocksize * data->blocks;
405 debug("trans data %d bytes\n", bytecnt);
406 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
407 ret = mmc_trans_data_by_cpu(priv, mmc, data);
409 error = readl(&priv->reg->rint) &
410 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
416 error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
423 debug("cacl timeout %x msec\n", timeout_msecs);
424 error = mmc_rint_wait(priv, mmc, timeout_msecs,
426 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
427 SUNXI_MMC_RINT_DATA_OVER,
433 if (cmd->resp_type & MMC_RSP_BUSY) {
434 unsigned long start = get_timer(0);
435 timeout_msecs = 2000;
438 status = readl(&priv->reg->status);
439 if (get_timer(start) > timeout_msecs) {
440 debug("busy timeout\n");
444 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
447 if (cmd->resp_type & MMC_RSP_136) {
448 cmd->response[0] = readl(&priv->reg->resp3);
449 cmd->response[1] = readl(&priv->reg->resp2);
450 cmd->response[2] = readl(&priv->reg->resp1);
451 cmd->response[3] = readl(&priv->reg->resp0);
452 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
453 cmd->response[3], cmd->response[2],
454 cmd->response[1], cmd->response[0]);
456 cmd->response[0] = readl(&priv->reg->resp0);
457 debug("mmc resp 0x%08x\n", cmd->response[0]);
461 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
462 mmc_update_clk(priv);
464 writel(0xffffffff, &priv->reg->rint);
465 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
471 #if !CONFIG_IS_ENABLED(DM_MMC)
472 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
474 struct sunxi_mmc_priv *priv = mmc->priv;
476 return sunxi_mmc_set_ios_common(priv, mmc);
479 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
480 struct mmc_data *data)
482 struct sunxi_mmc_priv *priv = mmc->priv;
484 return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
487 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
489 struct sunxi_mmc_priv *priv = mmc->priv;
492 cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
496 return !gpio_get_value(cd_pin);
499 static const struct mmc_ops sunxi_mmc_ops = {
500 .send_cmd = sunxi_mmc_send_cmd_legacy,
501 .set_ios = sunxi_mmc_set_ios_legacy,
502 .init = sunxi_mmc_core_init,
503 .getcd = sunxi_mmc_getcd_legacy,
506 struct mmc *sunxi_mmc_init(int sdc_no)
508 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
509 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
510 struct mmc_config *cfg = &priv->cfg;
513 memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
515 cfg->name = "SUNXI SD/MMC";
516 cfg->ops = &sunxi_mmc_ops;
518 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
519 cfg->host_caps = MMC_MODE_4BIT;
520 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
522 cfg->host_caps = MMC_MODE_8BIT;
524 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
525 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
528 cfg->f_max = 52000000;
530 if (mmc_resource_init(sdc_no) != 0)
533 /* config ahb clock */
534 debug("init mmc %d clock and io\n", sdc_no);
535 #if !defined(CONFIG_MACH_SUN50I_H6)
536 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
538 #ifdef CONFIG_SUNXI_GEN_SUN6I
540 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
542 #if defined(CONFIG_MACH_SUN9I)
543 /* sun9i has a mmc-common module, also set the gate and reset there */
544 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
545 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
547 #else /* CONFIG_MACH_SUN50I_H6 */
548 setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
550 setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
552 ret = mmc_set_mod_clk(priv, 24000000);
556 return mmc_create(cfg, priv);
560 static int sunxi_mmc_set_ios(struct udevice *dev)
562 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
563 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
565 return sunxi_mmc_set_ios_common(priv, &plat->mmc);
568 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
569 struct mmc_data *data)
571 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
572 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
574 return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
577 static int sunxi_mmc_getcd(struct udevice *dev)
579 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
581 if (dm_gpio_is_valid(&priv->cd_gpio)) {
582 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
584 return cd_state ^ priv->cd_inverted;
589 static const struct dm_mmc_ops sunxi_mmc_ops = {
590 .send_cmd = sunxi_mmc_send_cmd,
591 .set_ios = sunxi_mmc_set_ios,
592 .get_cd = sunxi_mmc_getcd,
595 static int sunxi_mmc_probe(struct udevice *dev)
597 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
598 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
599 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
600 struct mmc_config *cfg = &plat->cfg;
601 struct ofnode_phandle_args args;
605 cfg->name = dev->name;
606 bus_width = dev_read_u32_default(dev, "bus-width", 1);
608 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
611 cfg->host_caps |= MMC_MODE_8BIT;
613 cfg->host_caps |= MMC_MODE_4BIT;
614 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
615 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
618 cfg->f_max = 52000000;
620 priv->reg = (void *)dev_read_addr(dev);
622 /* We don't have a sunxi clock driver so find the clock address here */
623 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
627 priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
629 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
633 gate_reg = (u32 *)ofnode_get_addr(args.node);
634 setbits_le32(gate_reg, 1 << args.args[0]);
635 priv->mmc_no = args.args[0] - 8;
637 ret = mmc_set_mod_clk(priv, 24000000);
641 /* This GPIO is optional */
642 if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
644 int cd_pin = gpio_get_number(&priv->cd_gpio);
646 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
649 /* Check if card detect is inverted */
650 priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
652 upriv->mmc = &plat->mmc;
654 /* Reset controller */
655 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
661 static int sunxi_mmc_bind(struct udevice *dev)
663 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
665 return mmc_bind(dev, &plat->mmc, &plat->cfg);
668 static const struct udevice_id sunxi_mmc_ids[] = {
669 { .compatible = "allwinner,sun4i-a10-mmc" },
670 { .compatible = "allwinner,sun5i-a13-mmc" },
671 { .compatible = "allwinner,sun7i-a20-mmc" },
675 U_BOOT_DRIVER(sunxi_mmc_drv) = {
678 .of_match = sunxi_mmc_ids,
679 .bind = sunxi_mmc_bind,
680 .probe = sunxi_mmc_probe,
681 .ops = &sunxi_mmc_ops,
682 .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
683 .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),