drivers/mmc/sunxi_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2011
   4  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   5  * Aaron <leafy.myeh@allwinnertech.com>
   6  *
   7  * MMC driver for allwinner sunxi platform.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <malloc.h>
  14 #include <mmc.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc.h>
  20 #include <asm-generic/gpio.h>
  21
  22 struct sunxi_mmc_plat {
  23         struct mmc_config cfg;
  24         struct mmc mmc;
  25 };
  26
  27 struct sunxi_mmc_priv {
  28         unsigned mmc_no;
  29         uint32_t *mclkreg;
  30         unsigned fatal_err;
  31         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  32         int cd_inverted;                /* Inverted Card Detect */
  33         struct sunxi_mmc *reg;
  34         struct mmc_config cfg;
  35 };
  36
  37 #if !CONFIG_IS_ENABLED(DM_MMC)
  38 /* support 4 mmc hosts */
  39 struct sunxi_mmc_priv mmc_host[4];
  40
  41 static int sunxi_mmc_getcd_gpio(int sdc_no)
  42 {
  43         switch (sdc_no) {
  44         case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  45         case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  46         case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  47         case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  48         }
  49         return -EINVAL;
  50 }
  51
  52 static int mmc_resource_init(int sdc_no)
  53 {
  54         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  55         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  56         int cd_pin, ret = 0;
  57
  58         debug("init mmc %d resource\n", sdc_no);
  59
  60         switch (sdc_no) {
  61         case 0:
  62                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  63                 priv->mclkreg = &ccm->sd0_clk_cfg;
  64                 break;
  65         case 1:
  66                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  67                 priv->mclkreg = &ccm->sd1_clk_cfg;
  68                 break;
  69         case 2:
  70                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  71                 priv->mclkreg = &ccm->sd2_clk_cfg;
  72                 break;
  73 #ifdef SUNXI_MMC3_BASE
  74         case 3:
  75                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  76                 priv->mclkreg = &ccm->sd3_clk_cfg;
  77                 break;
  78 #endif
  79         default:
  80                 printf("Wrong mmc number %d\n", sdc_no);
  81                 return -1;
  82         }
  83         priv->mmc_no = sdc_no;
  84
  85         cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  86         if (cd_pin >= 0) {
  87                 ret = gpio_request(cd_pin, "mmc_cd");
  88                 if (!ret) {
  89                         sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
  90                         ret = gpio_direction_input(cd_pin);
  91                 }
  92         }
  93
  94         return ret;
  95 }
  96 #endif
  97
  98 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
  99 {
 100         unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
 101         bool new_mode = false;
 102         u32 val = 0;
 103
 104         if (IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && (priv->mmc_no == 2))
 105                 new_mode = true;
 106
 107         /*
 108          * The MMC clock has an extra /2 post-divider when operating in the new
 109          * mode.
 110          */
 111         if (new_mode)
 112                 hz = hz * 2;
 113
 114         if (hz <= 24000000) {
 115                 pll = CCM_MMC_CTRL_OSCM24;
 116                 pll_hz = 24000000;
 117         } else {
 118 #ifdef CONFIG_MACH_SUN9I
 119                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
 120                 pll_hz = clock_get_pll4_periph0();
 121 #elif defined(CONFIG_MACH_SUN50I_H6)
 122                 pll = CCM_MMC_CTRL_PLL6X2;
 123                 pll_hz = clock_get_pll6() * 2;
 124 #else
 125                 pll = CCM_MMC_CTRL_PLL6;
 126                 pll_hz = clock_get_pll6();
 127 #endif
 128         }
 129
 130         div = pll_hz / hz;
 131         if (pll_hz % hz)
 132                 div++;
 133
 134         n = 0;
 135         while (div > 16) {
 136                 n++;
 137                 div = (div + 1) / 2;
 138         }
 139
 140         if (n > 3) {
 141                 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
 142                        hz);
 143                 return -1;
 144         }
 145
 146         /* determine delays */
 147         if (hz <= 400000) {
 148                 oclk_dly = 0;
 149                 sclk_dly = 0;
 150         } else if (hz <= 25000000) {
 151                 oclk_dly = 0;
 152                 sclk_dly = 5;
 153 #ifdef CONFIG_MACH_SUN9I
 154         } else if (hz <= 52000000) {
 155                 oclk_dly = 5;
 156                 sclk_dly = 4;
 157         } else {
 158                 /* hz > 52000000 */
 159                 oclk_dly = 2;
 160                 sclk_dly = 4;
 161 #else
 162         } else if (hz <= 52000000) {
 163                 oclk_dly = 3;
 164                 sclk_dly = 4;
 165         } else {
 166                 /* hz > 52000000 */
 167                 oclk_dly = 1;
 168                 sclk_dly = 4;
 169 #endif
 170         }
 171
 172         if (new_mode) {
 173 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
 174                 val = CCM_MMC_CTRL_MODE_SEL_NEW;
 175                 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 176 #endif
 177         } else {
 178                 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 179                         CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
 180         }
 181
 182         writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
 183                CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
 184
 185         debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 186               priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
 187
 188         return 0;
 189 }
 190
 191 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
 192 {
 193         unsigned int cmd;
 194         unsigned timeout_msecs = 2000;
 195         unsigned long start = get_timer(0);
 196
 197         cmd = SUNXI_MMC_CMD_START |
 198               SUNXI_MMC_CMD_UPCLK_ONLY |
 199               SUNXI_MMC_CMD_WAIT_PRE_OVER;
 200
 201         writel(cmd, &priv->reg->cmd);
 202         while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
 203                 if (get_timer(start) > timeout_msecs)
 204                         return -1;
 205         }
 206
 207         /* clock update sets various irq status bits, clear these */
 208         writel(readl(&priv->reg->rint), &priv->reg->rint);
 209
 210         return 0;
 211 }
 212
 213 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
 214 {
 215         unsigned rval = readl(&priv->reg->clkcr);
 216
 217         /* Disable Clock */
 218         rval &= ~SUNXI_MMC_CLK_ENABLE;
 219         writel(rval, &priv->reg->clkcr);
 220         if (mmc_update_clk(priv))
 221                 return -1;
 222
 223         /* Set mod_clk to new rate */
 224         if (mmc_set_mod_clk(priv, mmc->clock))
 225                 return -1;
 226
 227         /* Clear internal divider */
 228         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 229         writel(rval, &priv->reg->clkcr);
 230
 231         /* Re-enable Clock */
 232         rval |= SUNXI_MMC_CLK_ENABLE;
 233         writel(rval, &priv->reg->clkcr);
 234         if (mmc_update_clk(priv))
 235                 return -1;
 236
 237         return 0;
 238 }
 239
 240 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
 241                                     struct mmc *mmc)
 242 {
 243         debug("set ios: bus_width: %x, clock: %d\n",
 244               mmc->bus_width, mmc->clock);
 245
 246         /* Change clock first */
 247         if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
 248                 priv->fatal_err = 1;
 249                 return -EINVAL;
 250         }
 251
 252         /* Change bus width */
 253         if (mmc->bus_width == 8)
 254                 writel(0x2, &priv->reg->width);
 255         else if (mmc->bus_width == 4)
 256                 writel(0x1, &priv->reg->width);
 257         else
 258                 writel(0x0, &priv->reg->width);
 259
 260         return 0;
 261 }
 262
 263 #if !CONFIG_IS_ENABLED(DM_MMC)
 264 static int sunxi_mmc_core_init(struct mmc *mmc)
 265 {
 266         struct sunxi_mmc_priv *priv = mmc->priv;
 267
 268         /* Reset controller */
 269         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 270         udelay(1000);
 271
 272         return 0;
 273 }
 274 #endif
 275
 276 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 277                                  struct mmc_data *data)
 278 {
 279         const int reading = !!(data->flags & MMC_DATA_READ);
 280         const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
 281                                               SUNXI_MMC_STATUS_FIFO_FULL;
 282         unsigned i;
 283         unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 284         unsigned byte_cnt = data->blocksize * data->blocks;
 285         unsigned timeout_msecs = byte_cnt >> 8;
 286         unsigned long  start;
 287
 288         if (timeout_msecs < 2000)
 289                 timeout_msecs = 2000;
 290
 291         /* Always read / write data through the CPU */
 292         setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 293
 294         start = get_timer(0);
 295
 296         for (i = 0; i < (byte_cnt >> 2); i++) {
 297                 while (readl(&priv->reg->status) & status_bit) {
 298                         if (get_timer(start) > timeout_msecs)
 299                                 return -1;
 300                 }
 301
 302                 if (reading)
 303                         buff[i] = readl(&priv->reg->fifo);
 304                 else
 305                         writel(buff[i], &priv->reg->fifo);
 306         }
 307
 308         return 0;
 309 }
 310
 311 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 312                          uint timeout_msecs, uint done_bit, const char *what)
 313 {
 314         unsigned int status;
 315         unsigned long start = get_timer(0);
 316
 317         do {
 318                 status = readl(&priv->reg->rint);
 319                 if ((get_timer(start) > timeout_msecs) ||
 320                     (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
 321                         debug("%s timeout %x\n", what,
 322                               status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
 323                         return -ETIMEDOUT;
 324                 }
 325         } while (!(status & done_bit));
 326
 327         return 0;
 328 }
 329
 330 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
 331                                      struct mmc *mmc, struct mmc_cmd *cmd,
 332                                      struct mmc_data *data)
 333 {
 334         unsigned int cmdval = SUNXI_MMC_CMD_START;
 335         unsigned int timeout_msecs;
 336         int error = 0;
 337         unsigned int status = 0;
 338         unsigned int bytecnt = 0;
 339
 340         if (priv->fatal_err)
 341                 return -1;
 342         if (cmd->resp_type & MMC_RSP_BUSY)
 343                 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
 344         if (cmd->cmdidx == 12)
 345                 return 0;
 346
 347         if (!cmd->cmdidx)
 348                 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 349         if (cmd->resp_type & MMC_RSP_PRESENT)
 350                 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 351         if (cmd->resp_type & MMC_RSP_136)
 352                 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 353         if (cmd->resp_type & MMC_RSP_CRC)
 354                 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 355
 356         if (data) {
 357                 if ((u32)(long)data->dest & 0x3) {
 358                         error = -1;
 359                         goto out;
 360                 }
 361
 362                 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 363                 if (data->flags & MMC_DATA_WRITE)
 364                         cmdval |= SUNXI_MMC_CMD_WRITE;
 365                 if (data->blocks > 1)
 366                         cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 367                 writel(data->blocksize, &priv->reg->blksz);
 368                 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
 369         }
 370
 371         debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
 372               cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 373         writel(cmd->cmdarg, &priv->reg->arg);
 374
 375         if (!data)
 376                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 377
 378         /*
 379          * transfer data and check status
 380          * STATREG[2] : FIFO empty
 381          * STATREG[3] : FIFO full
 382          */
 383         if (data) {
 384                 int ret = 0;
 385
 386                 bytecnt = data->blocksize * data->blocks;
 387                 debug("trans data %d bytes\n", bytecnt);
 388                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 389                 ret = mmc_trans_data_by_cpu(priv, mmc, data);
 390                 if (ret) {
 391                         error = readl(&priv->reg->rint) &
 392                                 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 393                         error = -ETIMEDOUT;
 394                         goto out;
 395                 }
 396         }
 397
 398         error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
 399                               "cmd");
 400         if (error)
 401                 goto out;
 402
 403         if (data) {
 404                 timeout_msecs = 120;
 405                 debug("cacl timeout %x msec\n", timeout_msecs);
 406                 error = mmc_rint_wait(priv, mmc, timeout_msecs,
 407                                       data->blocks > 1 ?
 408                                       SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
 409                                       SUNXI_MMC_RINT_DATA_OVER,
 410                                       "data");
 411                 if (error)
 412                         goto out;
 413         }
 414
 415         if (cmd->resp_type & MMC_RSP_BUSY) {
 416                 unsigned long start = get_timer(0);
 417                 timeout_msecs = 2000;
 418
 419                 do {
 420                         status = readl(&priv->reg->status);
 421                         if (get_timer(start) > timeout_msecs) {
 422                                 debug("busy timeout\n");
 423                                 error = -ETIMEDOUT;
 424                                 goto out;
 425                         }
 426                 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 427         }
 428
 429         if (cmd->resp_type & MMC_RSP_136) {
 430                 cmd->response[0] = readl(&priv->reg->resp3);
 431                 cmd->response[1] = readl(&priv->reg->resp2);
 432                 cmd->response[2] = readl(&priv->reg->resp1);
 433                 cmd->response[3] = readl(&priv->reg->resp0);
 434                 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
 435                       cmd->response[3], cmd->response[2],
 436                       cmd->response[1], cmd->response[0]);
 437         } else {
 438                 cmd->response[0] = readl(&priv->reg->resp0);
 439                 debug("mmc resp 0x%08x\n", cmd->response[0]);
 440         }
 441 out:
 442         if (error < 0) {
 443                 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 444                 mmc_update_clk(priv);
 445         }
 446         writel(0xffffffff, &priv->reg->rint);
 447         writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
 448                &priv->reg->gctrl);
 449
 450         return error;
 451 }
 452
 453 #if !CONFIG_IS_ENABLED(DM_MMC)
 454 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
 455 {
 456         struct sunxi_mmc_priv *priv = mmc->priv;
 457
 458         return sunxi_mmc_set_ios_common(priv, mmc);
 459 }
 460
 461 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
 462                                      struct mmc_data *data)
 463 {
 464         struct sunxi_mmc_priv *priv = mmc->priv;
 465
 466         return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
 467 }
 468
 469 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
 470 {
 471         struct sunxi_mmc_priv *priv = mmc->priv;
 472         int cd_pin;
 473
 474         cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
 475         if (cd_pin < 0)
 476                 return 1;
 477
 478         return !gpio_get_value(cd_pin);
 479 }
 480
 481 static const struct mmc_ops sunxi_mmc_ops = {
 482         .send_cmd       = sunxi_mmc_send_cmd_legacy,
 483         .set_ios        = sunxi_mmc_set_ios_legacy,
 484         .init           = sunxi_mmc_core_init,
 485         .getcd          = sunxi_mmc_getcd_legacy,
 486 };
 487
 488 struct mmc *sunxi_mmc_init(int sdc_no)
 489 {
 490         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 491         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
 492         struct mmc_config *cfg = &priv->cfg;
 493         int ret;
 494
 495         memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
 496
 497         cfg->name = "SUNXI SD/MMC";
 498         cfg->ops  = &sunxi_mmc_ops;
 499
 500         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 501         cfg->host_caps = MMC_MODE_4BIT;
 502 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
 503         if (sdc_no == 2)
 504                 cfg->host_caps = MMC_MODE_8BIT;
 505 #endif
 506         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 507         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 508
 509         cfg->f_min = 400000;
 510         cfg->f_max = 52000000;
 511
 512         if (mmc_resource_init(sdc_no) != 0)
 513                 return NULL;
 514
 515         /* config ahb clock */
 516         debug("init mmc %d clock and io\n", sdc_no);
 517 #if !defined(CONFIG_MACH_SUN50I_H6)
 518         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 519
 520 #ifdef CONFIG_SUNXI_GEN_SUN6I
 521         /* unassert reset */
 522         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 523 #endif
 524 #if defined(CONFIG_MACH_SUN9I)
 525         /* sun9i has a mmc-common module, also set the gate and reset there */
 526         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
 527                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
 528 #endif
 529 #else /* CONFIG_MACH_SUN50I_H6 */
 530         setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
 531         /* unassert reset */
 532         setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
 533 #endif
 534         ret = mmc_set_mod_clk(priv, 24000000);
 535         if (ret)
 536                 return NULL;
 537
 538         return mmc_create(cfg, priv);
 539 }
 540 #else
 541
 542 static int sunxi_mmc_set_ios(struct udevice *dev)
 543 {
 544         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 545         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 546
 547         return sunxi_mmc_set_ios_common(priv, &plat->mmc);
 548 }
 549
 550 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 551                               struct mmc_data *data)
 552 {
 553         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 554         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 555
 556         return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
 557 }
 558
 559 static int sunxi_mmc_getcd(struct udevice *dev)
 560 {
 561         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 562
 563         if (dm_gpio_is_valid(&priv->cd_gpio)) {
 564                 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
 565
 566                 return cd_state ^ priv->cd_inverted;
 567         }
 568         return 1;
 569 }
 570
 571 static const struct dm_mmc_ops sunxi_mmc_ops = {
 572         .send_cmd       = sunxi_mmc_send_cmd,
 573         .set_ios        = sunxi_mmc_set_ios,
 574         .get_cd         = sunxi_mmc_getcd,
 575 };
 576
 577 static int sunxi_mmc_probe(struct udevice *dev)
 578 {
 579         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 580         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 581         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 582         struct mmc_config *cfg = &plat->cfg;
 583         struct ofnode_phandle_args args;
 584         u32 *gate_reg;
 585         int bus_width, ret;
 586
 587         cfg->name = dev->name;
 588         bus_width = dev_read_u32_default(dev, "bus-width", 1);
 589
 590         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 591         cfg->host_caps = 0;
 592         if (bus_width == 8)
 593                 cfg->host_caps |= MMC_MODE_8BIT;
 594         if (bus_width >= 4)
 595                 cfg->host_caps |= MMC_MODE_4BIT;
 596         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 597         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 598
 599         cfg->f_min = 400000;
 600         cfg->f_max = 52000000;
 601
 602         priv->reg = (void *)dev_read_addr(dev);
 603
 604         /* We don't have a sunxi clock driver so find the clock address here */
 605         ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
 606                                           1, &args);
 607         if (ret)
 608                 return ret;
 609         priv->mclkreg = (u32 *)ofnode_get_addr(args.node);
 610
 611         ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
 612                                           0, &args);
 613         if (ret)
 614                 return ret;
 615         gate_reg = (u32 *)ofnode_get_addr(args.node);
 616         setbits_le32(gate_reg, 1 << args.args[0]);
 617         priv->mmc_no = args.args[0] - 8;
 618
 619         ret = mmc_set_mod_clk(priv, 24000000);
 620         if (ret)
 621                 return ret;
 622
 623         /* This GPIO is optional */
 624         if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 625                                   GPIOD_IS_IN)) {
 626                 int cd_pin = gpio_get_number(&priv->cd_gpio);
 627
 628                 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
 629         }
 630
 631         /* Check if card detect is inverted */
 632         priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
 633
 634         upriv->mmc = &plat->mmc;
 635
 636         /* Reset controller */
 637         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 638         udelay(1000);
 639
 640         return 0;
 641 }
 642
 643 static int sunxi_mmc_bind(struct udevice *dev)
 644 {
 645         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 646
 647         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 648 }
 649
 650 static const struct udevice_id sunxi_mmc_ids[] = {
 651         { .compatible = "allwinner,sun4i-a10-mmc" },
 652         { .compatible = "allwinner,sun5i-a13-mmc" },
 653         { .compatible = "allwinner,sun7i-a20-mmc" },
 654         { }
 655 };
 656
 657 U_BOOT_DRIVER(sunxi_mmc_drv) = {
 658         .name           = "sunxi_mmc",
 659         .id             = UCLASS_MMC,
 660         .of_match       = sunxi_mmc_ids,
 661         .bind           = sunxi_mmc_bind,
 662         .probe          = sunxi_mmc_probe,
 663         .ops            = &sunxi_mmc_ops,
 664         .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
 665         .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),
 666 };
 667 #endif