drivers/mmc/sunxi_mmc.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2007-2011
   4  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   5  * Aaron <leafy.myeh@allwinnertech.com>
   6  *
   7  * MMC driver for allwinner sunxi platform.
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <errno.h>
  13 #include <malloc.h>
  14 #include <mmc.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/clock.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/gpio.h>
  19 #include <asm/arch/mmc.h>
  20 #include <asm-generic/gpio.h>
  21
  22 #ifdef CONFIG_DM_MMC
  23 struct sunxi_mmc_variant {
  24         u16 gate_offset;
  25         u16 mclk_offset;
  26 };
  27 #endif
  28
  29 struct sunxi_mmc_plat {
  30         struct mmc_config cfg;
  31         struct mmc mmc;
  32 };
  33
  34 struct sunxi_mmc_priv {
  35         unsigned mmc_no;
  36         uint32_t *mclkreg;
  37         unsigned fatal_err;
  38         struct gpio_desc cd_gpio;       /* Change Detect GPIO */
  39         int cd_inverted;                /* Inverted Card Detect */
  40         struct sunxi_mmc *reg;
  41         struct mmc_config cfg;
  42 #ifdef CONFIG_DM_MMC
  43         const struct sunxi_mmc_variant *variant;
  44 #endif
  45 };
  46
  47 #if !CONFIG_IS_ENABLED(DM_MMC)
  48 /* support 4 mmc hosts */
  49 struct sunxi_mmc_priv mmc_host[4];
  50
  51 static int sunxi_mmc_getcd_gpio(int sdc_no)
  52 {
  53         switch (sdc_no) {
  54         case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
  55         case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
  56         case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
  57         case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
  58         }
  59         return -EINVAL;
  60 }
  61
  62 static int mmc_resource_init(int sdc_no)
  63 {
  64         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
  65         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  66         int cd_pin, ret = 0;
  67
  68         debug("init mmc %d resource\n", sdc_no);
  69
  70         switch (sdc_no) {
  71         case 0:
  72                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  73                 priv->mclkreg = &ccm->sd0_clk_cfg;
  74                 break;
  75         case 1:
  76                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  77                 priv->mclkreg = &ccm->sd1_clk_cfg;
  78                 break;
  79         case 2:
  80                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  81                 priv->mclkreg = &ccm->sd2_clk_cfg;
  82                 break;
  83 #ifdef SUNXI_MMC3_BASE
  84         case 3:
  85                 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  86                 priv->mclkreg = &ccm->sd3_clk_cfg;
  87                 break;
  88 #endif
  89         default:
  90                 printf("Wrong mmc number %d\n", sdc_no);
  91                 return -1;
  92         }
  93         priv->mmc_no = sdc_no;
  94
  95         cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
  96         if (cd_pin >= 0) {
  97                 ret = gpio_request(cd_pin, "mmc_cd");
  98                 if (!ret) {
  99                         sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
 100                         ret = gpio_direction_input(cd_pin);
 101                 }
 102         }
 103
 104         return ret;
 105 }
 106 #endif
 107
 108 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
 109 {
 110         unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
 111         bool new_mode = true;
 112         bool calibrate = false;
 113         u32 val = 0;
 114
 115         if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
 116                 new_mode = false;
 117
 118         /* A83T support new mode only on eMMC */
 119         if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
 120                 new_mode = false;
 121
 122 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
 123         calibrate = true;
 124 #endif
 125
 126         if (hz <= 24000000) {
 127                 pll = CCM_MMC_CTRL_OSCM24;
 128                 pll_hz = 24000000;
 129         } else {
 130 #ifdef CONFIG_MACH_SUN9I
 131                 pll = CCM_MMC_CTRL_PLL_PERIPH0;
 132                 pll_hz = clock_get_pll4_periph0();
 133 #elif defined(CONFIG_MACH_SUN50I_H6)
 134                 pll = CCM_MMC_CTRL_PLL6X2;
 135                 pll_hz = clock_get_pll6() * 2;
 136 #else
 137                 pll = CCM_MMC_CTRL_PLL6;
 138                 pll_hz = clock_get_pll6();
 139 #endif
 140         }
 141
 142         div = pll_hz / hz;
 143         if (pll_hz % hz)
 144                 div++;
 145
 146         n = 0;
 147         while (div > 16) {
 148                 n++;
 149                 div = (div + 1) / 2;
 150         }
 151
 152         if (n > 3) {
 153                 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
 154                        hz);
 155                 return -1;
 156         }
 157
 158         /* determine delays */
 159         if (hz <= 400000) {
 160                 oclk_dly = 0;
 161                 sclk_dly = 0;
 162         } else if (hz <= 25000000) {
 163                 oclk_dly = 0;
 164                 sclk_dly = 5;
 165 #ifdef CONFIG_MACH_SUN9I
 166         } else if (hz <= 52000000) {
 167                 oclk_dly = 5;
 168                 sclk_dly = 4;
 169         } else {
 170                 /* hz > 52000000 */
 171                 oclk_dly = 2;
 172                 sclk_dly = 4;
 173 #else
 174         } else if (hz <= 52000000) {
 175                 oclk_dly = 3;
 176                 sclk_dly = 4;
 177         } else {
 178                 /* hz > 52000000 */
 179                 oclk_dly = 1;
 180                 sclk_dly = 4;
 181 #endif
 182         }
 183
 184         if (new_mode) {
 185 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
 186 #ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
 187                 val = CCM_MMC_CTRL_MODE_SEL_NEW;
 188 #endif
 189                 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
 190 #endif
 191         } else if (!calibrate) {
 192                 /*
 193                  * Use hardcoded delay values if controller doesn't support
 194                  * calibration
 195                  */
 196                 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
 197                         CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
 198         }
 199
 200         writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
 201                CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
 202
 203         debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
 204               priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
 205
 206         return 0;
 207 }
 208
 209 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
 210 {
 211         unsigned int cmd;
 212         unsigned timeout_msecs = 2000;
 213         unsigned long start = get_timer(0);
 214
 215         cmd = SUNXI_MMC_CMD_START |
 216               SUNXI_MMC_CMD_UPCLK_ONLY |
 217               SUNXI_MMC_CMD_WAIT_PRE_OVER;
 218
 219         writel(cmd, &priv->reg->cmd);
 220         while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
 221                 if (get_timer(start) > timeout_msecs)
 222                         return -1;
 223         }
 224
 225         /* clock update sets various irq status bits, clear these */
 226         writel(readl(&priv->reg->rint), &priv->reg->rint);
 227
 228         return 0;
 229 }
 230
 231 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
 232 {
 233         unsigned rval = readl(&priv->reg->clkcr);
 234
 235         /* Disable Clock */
 236         rval &= ~SUNXI_MMC_CLK_ENABLE;
 237         writel(rval, &priv->reg->clkcr);
 238         if (mmc_update_clk(priv))
 239                 return -1;
 240
 241         /* Set mod_clk to new rate */
 242         if (mmc_set_mod_clk(priv, mmc->clock))
 243                 return -1;
 244
 245         /* Clear internal divider */
 246         rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
 247         writel(rval, &priv->reg->clkcr);
 248
 249 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
 250         /* A64 supports calibration of delays on MMC controller and we
 251          * have to set delay of zero before starting calibration.
 252          * Allwinner BSP driver sets a delay only in the case of
 253          * using HS400 which is not supported by mainline U-Boot or
 254          * Linux at the moment
 255          */
 256         writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
 257 #endif
 258
 259         /* Re-enable Clock */
 260         rval |= SUNXI_MMC_CLK_ENABLE;
 261         writel(rval, &priv->reg->clkcr);
 262         if (mmc_update_clk(priv))
 263                 return -1;
 264
 265         return 0;
 266 }
 267
 268 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
 269                                     struct mmc *mmc)
 270 {
 271         debug("set ios: bus_width: %x, clock: %d\n",
 272               mmc->bus_width, mmc->clock);
 273
 274         /* Change clock first */
 275         if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
 276                 priv->fatal_err = 1;
 277                 return -EINVAL;
 278         }
 279
 280         /* Change bus width */
 281         if (mmc->bus_width == 8)
 282                 writel(0x2, &priv->reg->width);
 283         else if (mmc->bus_width == 4)
 284                 writel(0x1, &priv->reg->width);
 285         else
 286                 writel(0x0, &priv->reg->width);
 287
 288         return 0;
 289 }
 290
 291 #if !CONFIG_IS_ENABLED(DM_MMC)
 292 static int sunxi_mmc_core_init(struct mmc *mmc)
 293 {
 294         struct sunxi_mmc_priv *priv = mmc->priv;
 295
 296         /* Reset controller */
 297         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 298         udelay(1000);
 299
 300         return 0;
 301 }
 302 #endif
 303
 304 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 305                                  struct mmc_data *data)
 306 {
 307         const int reading = !!(data->flags & MMC_DATA_READ);
 308         const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
 309                                               SUNXI_MMC_STATUS_FIFO_FULL;
 310         unsigned i;
 311         unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
 312         unsigned byte_cnt = data->blocksize * data->blocks;
 313         unsigned timeout_msecs = byte_cnt >> 8;
 314         unsigned long  start;
 315
 316         if (timeout_msecs < 2000)
 317                 timeout_msecs = 2000;
 318
 319         /* Always read / write data through the CPU */
 320         setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
 321
 322         start = get_timer(0);
 323
 324         for (i = 0; i < (byte_cnt >> 2); i++) {
 325                 while (readl(&priv->reg->status) & status_bit) {
 326                         if (get_timer(start) > timeout_msecs)
 327                                 return -1;
 328                 }
 329
 330                 if (reading)
 331                         buff[i] = readl(&priv->reg->fifo);
 332                 else
 333                         writel(buff[i], &priv->reg->fifo);
 334         }
 335
 336         return 0;
 337 }
 338
 339 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
 340                          uint timeout_msecs, uint done_bit, const char *what)
 341 {
 342         unsigned int status;
 343         unsigned long start = get_timer(0);
 344
 345         do {
 346                 status = readl(&priv->reg->rint);
 347                 if ((get_timer(start) > timeout_msecs) ||
 348                     (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
 349                         debug("%s timeout %x\n", what,
 350                               status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
 351                         return -ETIMEDOUT;
 352                 }
 353         } while (!(status & done_bit));
 354
 355         return 0;
 356 }
 357
 358 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
 359                                      struct mmc *mmc, struct mmc_cmd *cmd,
 360                                      struct mmc_data *data)
 361 {
 362         unsigned int cmdval = SUNXI_MMC_CMD_START;
 363         unsigned int timeout_msecs;
 364         int error = 0;
 365         unsigned int status = 0;
 366         unsigned int bytecnt = 0;
 367
 368         if (priv->fatal_err)
 369                 return -1;
 370         if (cmd->resp_type & MMC_RSP_BUSY)
 371                 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
 372         if (cmd->cmdidx == 12)
 373                 return 0;
 374
 375         if (!cmd->cmdidx)
 376                 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
 377         if (cmd->resp_type & MMC_RSP_PRESENT)
 378                 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
 379         if (cmd->resp_type & MMC_RSP_136)
 380                 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
 381         if (cmd->resp_type & MMC_RSP_CRC)
 382                 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
 383
 384         if (data) {
 385                 if ((u32)(long)data->dest & 0x3) {
 386                         error = -1;
 387                         goto out;
 388                 }
 389
 390                 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
 391                 if (data->flags & MMC_DATA_WRITE)
 392                         cmdval |= SUNXI_MMC_CMD_WRITE;
 393                 if (data->blocks > 1)
 394                         cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
 395                 writel(data->blocksize, &priv->reg->blksz);
 396                 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
 397         }
 398
 399         debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
 400               cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
 401         writel(cmd->cmdarg, &priv->reg->arg);
 402
 403         if (!data)
 404                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 405
 406         /*
 407          * transfer data and check status
 408          * STATREG[2] : FIFO empty
 409          * STATREG[3] : FIFO full
 410          */
 411         if (data) {
 412                 int ret = 0;
 413
 414                 bytecnt = data->blocksize * data->blocks;
 415                 debug("trans data %d bytes\n", bytecnt);
 416                 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
 417                 ret = mmc_trans_data_by_cpu(priv, mmc, data);
 418                 if (ret) {
 419                         error = readl(&priv->reg->rint) &
 420                                 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
 421                         error = -ETIMEDOUT;
 422                         goto out;
 423                 }
 424         }
 425
 426         error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
 427                               "cmd");
 428         if (error)
 429                 goto out;
 430
 431         if (data) {
 432                 timeout_msecs = 120;
 433                 debug("cacl timeout %x msec\n", timeout_msecs);
 434                 error = mmc_rint_wait(priv, mmc, timeout_msecs,
 435                                       data->blocks > 1 ?
 436                                       SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
 437                                       SUNXI_MMC_RINT_DATA_OVER,
 438                                       "data");
 439                 if (error)
 440                         goto out;
 441         }
 442
 443         if (cmd->resp_type & MMC_RSP_BUSY) {
 444                 unsigned long start = get_timer(0);
 445                 timeout_msecs = 2000;
 446
 447                 do {
 448                         status = readl(&priv->reg->status);
 449                         if (get_timer(start) > timeout_msecs) {
 450                                 debug("busy timeout\n");
 451                                 error = -ETIMEDOUT;
 452                                 goto out;
 453                         }
 454                 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
 455         }
 456
 457         if (cmd->resp_type & MMC_RSP_136) {
 458                 cmd->response[0] = readl(&priv->reg->resp3);
 459                 cmd->response[1] = readl(&priv->reg->resp2);
 460                 cmd->response[2] = readl(&priv->reg->resp1);
 461                 cmd->response[3] = readl(&priv->reg->resp0);
 462                 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
 463                       cmd->response[3], cmd->response[2],
 464                       cmd->response[1], cmd->response[0]);
 465         } else {
 466                 cmd->response[0] = readl(&priv->reg->resp0);
 467                 debug("mmc resp 0x%08x\n", cmd->response[0]);
 468         }
 469 out:
 470         if (error < 0) {
 471                 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 472                 mmc_update_clk(priv);
 473         }
 474         writel(0xffffffff, &priv->reg->rint);
 475         writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
 476                &priv->reg->gctrl);
 477
 478         return error;
 479 }
 480
 481 #if !CONFIG_IS_ENABLED(DM_MMC)
 482 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
 483 {
 484         struct sunxi_mmc_priv *priv = mmc->priv;
 485
 486         return sunxi_mmc_set_ios_common(priv, mmc);
 487 }
 488
 489 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
 490                                      struct mmc_data *data)
 491 {
 492         struct sunxi_mmc_priv *priv = mmc->priv;
 493
 494         return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
 495 }
 496
 497 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
 498 {
 499         struct sunxi_mmc_priv *priv = mmc->priv;
 500         int cd_pin;
 501
 502         cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
 503         if (cd_pin < 0)
 504                 return 1;
 505
 506         return !gpio_get_value(cd_pin);
 507 }
 508
 509 static const struct mmc_ops sunxi_mmc_ops = {
 510         .send_cmd       = sunxi_mmc_send_cmd_legacy,
 511         .set_ios        = sunxi_mmc_set_ios_legacy,
 512         .init           = sunxi_mmc_core_init,
 513         .getcd          = sunxi_mmc_getcd_legacy,
 514 };
 515
 516 struct mmc *sunxi_mmc_init(int sdc_no)
 517 {
 518         struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 519         struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
 520         struct mmc_config *cfg = &priv->cfg;
 521         int ret;
 522
 523         memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
 524
 525         cfg->name = "SUNXI SD/MMC";
 526         cfg->ops  = &sunxi_mmc_ops;
 527
 528         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 529         cfg->host_caps = MMC_MODE_4BIT;
 530 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
 531         if (sdc_no == 2)
 532                 cfg->host_caps = MMC_MODE_8BIT;
 533 #endif
 534         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 535         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 536
 537         cfg->f_min = 400000;
 538         cfg->f_max = 52000000;
 539
 540         if (mmc_resource_init(sdc_no) != 0)
 541                 return NULL;
 542
 543         /* config ahb clock */
 544         debug("init mmc %d clock and io\n", sdc_no);
 545 #if !defined(CONFIG_MACH_SUN50I_H6)
 546         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 547
 548 #ifdef CONFIG_SUNXI_GEN_SUN6I
 549         /* unassert reset */
 550         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 551 #endif
 552 #if defined(CONFIG_MACH_SUN9I)
 553         /* sun9i has a mmc-common module, also set the gate and reset there */
 554         writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
 555                SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
 556 #endif
 557 #else /* CONFIG_MACH_SUN50I_H6 */
 558         setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
 559         /* unassert reset */
 560         setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
 561 #endif
 562         ret = mmc_set_mod_clk(priv, 24000000);
 563         if (ret)
 564                 return NULL;
 565
 566         return mmc_create(cfg, priv);
 567 }
 568 #else
 569
 570 static int sunxi_mmc_set_ios(struct udevice *dev)
 571 {
 572         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 573         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 574
 575         return sunxi_mmc_set_ios_common(priv, &plat->mmc);
 576 }
 577
 578 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 579                               struct mmc_data *data)
 580 {
 581         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 582         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 583
 584         return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
 585 }
 586
 587 static int sunxi_mmc_getcd(struct udevice *dev)
 588 {
 589         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 590
 591         if (dm_gpio_is_valid(&priv->cd_gpio)) {
 592                 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
 593
 594                 return cd_state ^ priv->cd_inverted;
 595         }
 596         return 1;
 597 }
 598
 599 static const struct dm_mmc_ops sunxi_mmc_ops = {
 600         .send_cmd       = sunxi_mmc_send_cmd,
 601         .set_ios        = sunxi_mmc_set_ios,
 602         .get_cd         = sunxi_mmc_getcd,
 603 };
 604
 605 static int sunxi_mmc_probe(struct udevice *dev)
 606 {
 607         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 608         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 609         struct sunxi_mmc_priv *priv = dev_get_priv(dev);
 610         struct mmc_config *cfg = &plat->cfg;
 611         struct ofnode_phandle_args args;
 612         u32 *gate_reg, *ccu_reg;
 613         int bus_width, ret;
 614
 615         cfg->name = dev->name;
 616         bus_width = dev_read_u32_default(dev, "bus-width", 1);
 617
 618         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 619         cfg->host_caps = 0;
 620         if (bus_width == 8)
 621                 cfg->host_caps |= MMC_MODE_8BIT;
 622         if (bus_width >= 4)
 623                 cfg->host_caps |= MMC_MODE_4BIT;
 624         cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 625         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 626
 627         cfg->f_min = 400000;
 628         cfg->f_max = 52000000;
 629
 630         priv->reg = (void *)dev_read_addr(dev);
 631         priv->variant =
 632                 (const struct sunxi_mmc_variant *)dev_get_driver_data(dev);
 633
 634         /* We don't have a sunxi clock driver so find the clock address here */
 635         ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
 636                                           1, &args);
 637         if (ret)
 638                 return ret;
 639         ccu_reg = (u32 *)ofnode_get_addr(args.node);
 640
 641         priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
 642         priv->mclkreg = (void *)ccu_reg +
 643                         (priv->variant->mclk_offset + (priv->mmc_no * 4));
 644         gate_reg = (void *)ccu_reg + priv->variant->gate_offset;
 645         setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
 646
 647         ret = mmc_set_mod_clk(priv, 24000000);
 648         if (ret)
 649                 return ret;
 650
 651         /* This GPIO is optional */
 652         if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 653                                   GPIOD_IS_IN)) {
 654                 int cd_pin = gpio_get_number(&priv->cd_gpio);
 655
 656                 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
 657         }
 658
 659         /* Check if card detect is inverted */
 660         priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
 661
 662         upriv->mmc = &plat->mmc;
 663
 664         /* Reset controller */
 665         writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
 666         udelay(1000);
 667
 668         return 0;
 669 }
 670
 671 static int sunxi_mmc_bind(struct udevice *dev)
 672 {
 673         struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
 674
 675         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 676 }
 677
 678 static const struct sunxi_mmc_variant sun4i_a10_variant = {
 679         .gate_offset = 0x60,
 680         .mclk_offset = 0x88,
 681 };
 682
 683 static const struct sunxi_mmc_variant sun50i_h6_variant = {
 684         .mclk_offset = 0x830,
 685 };
 686
 687 static const struct udevice_id sunxi_mmc_ids[] = {
 688         {
 689           .compatible = "allwinner,sun4i-a10-mmc",
 690           .data = (ulong)&sun4i_a10_variant,
 691         },
 692         {
 693           .compatible = "allwinner,sun5i-a13-mmc",
 694           .data = (ulong)&sun4i_a10_variant,
 695         },
 696         {
 697           .compatible = "allwinner,sun7i-a20-mmc",
 698           .data = (ulong)&sun4i_a10_variant,
 699         },
 700         {
 701           .compatible = "allwinner,sun8i-a83t-emmc",
 702           .data = (ulong)&sun4i_a10_variant,
 703         },
 704         {
 705           .compatible = "allwinner,sun50i-a64-mmc",
 706           .data = (ulong)&sun4i_a10_variant,
 707         },
 708         {
 709           .compatible = "allwinner,sun50i-a64-emmc",
 710           .data = (ulong)&sun4i_a10_variant,
 711         },
 712         {
 713           .compatible = "allwinner,sun50i-h6-mmc",
 714           .data = (ulong)&sun50i_h6_variant,
 715         },
 716         {
 717           .compatible = "allwinner,sun50i-h6-emmc",
 718           .data = (ulong)&sun50i_h6_variant,
 719         },
 720         { /* sentinel */ }
 721 };
 722
 723 U_BOOT_DRIVER(sunxi_mmc_drv) = {
 724         .name           = "sunxi_mmc",
 725         .id             = UCLASS_MMC,
 726         .of_match       = sunxi_mmc_ids,
 727         .bind           = sunxi_mmc_bind,
 728         .probe          = sunxi_mmc_probe,
 729         .ops            = &sunxi_mmc_ops,
 730         .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
 731         .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),
 732 };
 733 #endif