drivers/mmc/stm32_sdmmc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <dm.h>
  10 #include <fdtdec.h>
  11 #include <linux/libfdt.h>
  12 #include <mmc.h>
  13 #include <reset.h>
  14 #include <asm/io.h>
  15 #include <asm/gpio.h>
  16 #include <linux/iopoll.h>
  17
  18 struct stm32_sdmmc2_plat {
  19         struct mmc_config cfg;
  20         struct mmc mmc;
  21 };
  22
  23 struct stm32_sdmmc2_priv {
  24         fdt_addr_t base;
  25         struct clk clk;
  26         struct reset_ctl reset_ctl;
  27         struct gpio_desc cd_gpio;
  28         u32 clk_reg_msk;
  29         u32 pwr_reg_msk;
  30 };
  31
  32 struct stm32_sdmmc2_ctx {
  33         u32 cache_start;
  34         u32 cache_end;
  35         u32 data_length;
  36         bool dpsm_abort;
  37 };
  38
  39 /* SDMMC REGISTERS OFFSET */
  40 #define SDMMC_POWER             0x00    /* SDMMC power control             */
  41 #define SDMMC_CLKCR             0x04    /* SDMMC clock control             */
  42 #define SDMMC_ARG               0x08    /* SDMMC argument                  */
  43 #define SDMMC_CMD               0x0C    /* SDMMC command                   */
  44 #define SDMMC_RESP1             0x14    /* SDMMC response 1                */
  45 #define SDMMC_RESP2             0x18    /* SDMMC response 2                */
  46 #define SDMMC_RESP3             0x1C    /* SDMMC response 3                */
  47 #define SDMMC_RESP4             0x20    /* SDMMC response 4                */
  48 #define SDMMC_DTIMER            0x24    /* SDMMC data timer                */
  49 #define SDMMC_DLEN              0x28    /* SDMMC data length               */
  50 #define SDMMC_DCTRL             0x2C    /* SDMMC data control              */
  51 #define SDMMC_DCOUNT            0x30    /* SDMMC data counter              */
  52 #define SDMMC_STA               0x34    /* SDMMC status                    */
  53 #define SDMMC_ICR               0x38    /* SDMMC interrupt clear           */
  54 #define SDMMC_MASK              0x3C    /* SDMMC mask                      */
  55 #define SDMMC_IDMACTRL          0x50    /* SDMMC DMA control               */
  56 #define SDMMC_IDMABASE0         0x58    /* SDMMC DMA buffer 0 base address */
  57
  58 /* SDMMC_POWER register */
  59 #define SDMMC_POWER_PWRCTRL_MASK        GENMASK(1, 0)
  60 #define SDMMC_POWER_PWRCTRL_OFF         0
  61 #define SDMMC_POWER_PWRCTRL_CYCLE       2
  62 #define SDMMC_POWER_PWRCTRL_ON          3
  63 #define SDMMC_POWER_VSWITCH             BIT(2)
  64 #define SDMMC_POWER_VSWITCHEN           BIT(3)
  65 #define SDMMC_POWER_DIRPOL              BIT(4)
  66
  67 /* SDMMC_CLKCR register */
  68 #define SDMMC_CLKCR_CLKDIV              GENMASK(9, 0)
  69 #define SDMMC_CLKCR_CLKDIV_MAX          SDMMC_CLKCR_CLKDIV
  70 #define SDMMC_CLKCR_PWRSAV              BIT(12)
  71 #define SDMMC_CLKCR_WIDBUS_4            BIT(14)
  72 #define SDMMC_CLKCR_WIDBUS_8            BIT(15)
  73 #define SDMMC_CLKCR_NEGEDGE             BIT(16)
  74 #define SDMMC_CLKCR_HWFC_EN             BIT(17)
  75 #define SDMMC_CLKCR_DDR                 BIT(18)
  76 #define SDMMC_CLKCR_BUSSPEED            BIT(19)
  77 #define SDMMC_CLKCR_SELCLKRX_MASK       GENMASK(21, 20)
  78 #define SDMMC_CLKCR_SELCLKRX_CK         0
  79 #define SDMMC_CLKCR_SELCLKRX_CKIN       BIT(20)
  80 #define SDMMC_CLKCR_SELCLKRX_FBCK       BIT(21)
  81
  82 /* SDMMC_CMD register */
  83 #define SDMMC_CMD_CMDINDEX              GENMASK(5, 0)
  84 #define SDMMC_CMD_CMDTRANS              BIT(6)
  85 #define SDMMC_CMD_CMDSTOP               BIT(7)
  86 #define SDMMC_CMD_WAITRESP              GENMASK(9, 8)
  87 #define SDMMC_CMD_WAITRESP_0            BIT(8)
  88 #define SDMMC_CMD_WAITRESP_1            BIT(9)
  89 #define SDMMC_CMD_WAITINT               BIT(10)
  90 #define SDMMC_CMD_WAITPEND              BIT(11)
  91 #define SDMMC_CMD_CPSMEN                BIT(12)
  92 #define SDMMC_CMD_DTHOLD                BIT(13)
  93 #define SDMMC_CMD_BOOTMODE              BIT(14)
  94 #define SDMMC_CMD_BOOTEN                BIT(15)
  95 #define SDMMC_CMD_CMDSUSPEND            BIT(16)
  96
  97 /* SDMMC_DCTRL register */
  98 #define SDMMC_DCTRL_DTEN                BIT(0)
  99 #define SDMMC_DCTRL_DTDIR               BIT(1)
 100 #define SDMMC_DCTRL_DTMODE              GENMASK(3, 2)
 101 #define SDMMC_DCTRL_DBLOCKSIZE          GENMASK(7, 4)
 102 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT    4
 103 #define SDMMC_DCTRL_RWSTART             BIT(8)
 104 #define SDMMC_DCTRL_RWSTOP              BIT(9)
 105 #define SDMMC_DCTRL_RWMOD               BIT(10)
 106 #define SDMMC_DCTRL_SDMMCEN             BIT(11)
 107 #define SDMMC_DCTRL_BOOTACKEN           BIT(12)
 108 #define SDMMC_DCTRL_FIFORST             BIT(13)
 109
 110 /* SDMMC_STA register */
 111 #define SDMMC_STA_CCRCFAIL              BIT(0)
 112 #define SDMMC_STA_DCRCFAIL              BIT(1)
 113 #define SDMMC_STA_CTIMEOUT              BIT(2)
 114 #define SDMMC_STA_DTIMEOUT              BIT(3)
 115 #define SDMMC_STA_TXUNDERR              BIT(4)
 116 #define SDMMC_STA_RXOVERR               BIT(5)
 117 #define SDMMC_STA_CMDREND               BIT(6)
 118 #define SDMMC_STA_CMDSENT               BIT(7)
 119 #define SDMMC_STA_DATAEND               BIT(8)
 120 #define SDMMC_STA_DHOLD                 BIT(9)
 121 #define SDMMC_STA_DBCKEND               BIT(10)
 122 #define SDMMC_STA_DABORT                BIT(11)
 123 #define SDMMC_STA_DPSMACT               BIT(12)
 124 #define SDMMC_STA_CPSMACT               BIT(13)
 125 #define SDMMC_STA_TXFIFOHE              BIT(14)
 126 #define SDMMC_STA_RXFIFOHF              BIT(15)
 127 #define SDMMC_STA_TXFIFOF               BIT(16)
 128 #define SDMMC_STA_RXFIFOF               BIT(17)
 129 #define SDMMC_STA_TXFIFOE               BIT(18)
 130 #define SDMMC_STA_RXFIFOE               BIT(19)
 131 #define SDMMC_STA_BUSYD0                BIT(20)
 132 #define SDMMC_STA_BUSYD0END             BIT(21)
 133 #define SDMMC_STA_SDMMCIT               BIT(22)
 134 #define SDMMC_STA_ACKFAIL               BIT(23)
 135 #define SDMMC_STA_ACKTIMEOUT            BIT(24)
 136 #define SDMMC_STA_VSWEND                BIT(25)
 137 #define SDMMC_STA_CKSTOP                BIT(26)
 138 #define SDMMC_STA_IDMATE                BIT(27)
 139 #define SDMMC_STA_IDMABTC               BIT(28)
 140
 141 /* SDMMC_ICR register */
 142 #define SDMMC_ICR_CCRCFAILC             BIT(0)
 143 #define SDMMC_ICR_DCRCFAILC             BIT(1)
 144 #define SDMMC_ICR_CTIMEOUTC             BIT(2)
 145 #define SDMMC_ICR_DTIMEOUTC             BIT(3)
 146 #define SDMMC_ICR_TXUNDERRC             BIT(4)
 147 #define SDMMC_ICR_RXOVERRC              BIT(5)
 148 #define SDMMC_ICR_CMDRENDC              BIT(6)
 149 #define SDMMC_ICR_CMDSENTC              BIT(7)
 150 #define SDMMC_ICR_DATAENDC              BIT(8)
 151 #define SDMMC_ICR_DHOLDC                BIT(9)
 152 #define SDMMC_ICR_DBCKENDC              BIT(10)
 153 #define SDMMC_ICR_DABORTC               BIT(11)
 154 #define SDMMC_ICR_BUSYD0ENDC            BIT(21)
 155 #define SDMMC_ICR_SDMMCITC              BIT(22)
 156 #define SDMMC_ICR_ACKFAILC              BIT(23)
 157 #define SDMMC_ICR_ACKTIMEOUTC           BIT(24)
 158 #define SDMMC_ICR_VSWENDC               BIT(25)
 159 #define SDMMC_ICR_CKSTOPC               BIT(26)
 160 #define SDMMC_ICR_IDMATEC               BIT(27)
 161 #define SDMMC_ICR_IDMABTCC              BIT(28)
 162 #define SDMMC_ICR_STATIC_FLAGS          ((GENMASK(28, 21)) | (GENMASK(11, 0)))
 163
 164 /* SDMMC_MASK register */
 165 #define SDMMC_MASK_CCRCFAILIE           BIT(0)
 166 #define SDMMC_MASK_DCRCFAILIE           BIT(1)
 167 #define SDMMC_MASK_CTIMEOUTIE           BIT(2)
 168 #define SDMMC_MASK_DTIMEOUTIE           BIT(3)
 169 #define SDMMC_MASK_TXUNDERRIE           BIT(4)
 170 #define SDMMC_MASK_RXOVERRIE            BIT(5)
 171 #define SDMMC_MASK_CMDRENDIE            BIT(6)
 172 #define SDMMC_MASK_CMDSENTIE            BIT(7)
 173 #define SDMMC_MASK_DATAENDIE            BIT(8)
 174 #define SDMMC_MASK_DHOLDIE              BIT(9)
 175 #define SDMMC_MASK_DBCKENDIE            BIT(10)
 176 #define SDMMC_MASK_DABORTIE             BIT(11)
 177 #define SDMMC_MASK_TXFIFOHEIE           BIT(14)
 178 #define SDMMC_MASK_RXFIFOHFIE           BIT(15)
 179 #define SDMMC_MASK_RXFIFOFIE            BIT(17)
 180 #define SDMMC_MASK_TXFIFOEIE            BIT(18)
 181 #define SDMMC_MASK_BUSYD0ENDIE          BIT(21)
 182 #define SDMMC_MASK_SDMMCITIE            BIT(22)
 183 #define SDMMC_MASK_ACKFAILIE            BIT(23)
 184 #define SDMMC_MASK_ACKTIMEOUTIE         BIT(24)
 185 #define SDMMC_MASK_VSWENDIE             BIT(25)
 186 #define SDMMC_MASK_CKSTOPIE             BIT(26)
 187 #define SDMMC_MASK_IDMABTCIE            BIT(28)
 188
 189 /* SDMMC_IDMACTRL register */
 190 #define SDMMC_IDMACTRL_IDMAEN           BIT(0)
 191
 192 #define SDMMC_CMD_TIMEOUT               0xFFFFFFFF
 193
 194 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
 195                                     struct mmc_data *data,
 196                                     struct stm32_sdmmc2_ctx *ctx)
 197 {
 198         u32 data_ctrl, idmabase0;
 199
 200         /* Configure the SDMMC DPSM (Data Path State Machine) */
 201         data_ctrl = (__ilog2(data->blocksize) <<
 202                      SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
 203                     SDMMC_DCTRL_DBLOCKSIZE;
 204
 205         if (data->flags & MMC_DATA_READ) {
 206                 data_ctrl |= SDMMC_DCTRL_DTDIR;
 207                 idmabase0 = (u32)data->dest;
 208         } else {
 209                 idmabase0 = (u32)data->src;
 210         }
 211
 212         /* Set the SDMMC Data TimeOut value */
 213         writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER);
 214
 215         /* Set the SDMMC DataLength value */
 216         writel(ctx->data_length, priv->base + SDMMC_DLEN);
 217
 218         /* Write to SDMMC DCTRL */
 219         writel(data_ctrl, priv->base + SDMMC_DCTRL);
 220
 221         /* Cache align */
 222         ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
 223         ctx->cache_end = roundup(idmabase0 + ctx->data_length,
 224                                  ARCH_DMA_MINALIGN);
 225
 226         /*
 227          * Flush data cache before DMA start (clean and invalidate)
 228          * Clean also needed for read
 229          * Avoid issue on buffer not cached-aligned
 230          */
 231         flush_dcache_range(ctx->cache_start, ctx->cache_end);
 232
 233         /* Enable internal DMA */
 234         writel(idmabase0, priv->base + SDMMC_IDMABASE0);
 235         writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
 236 }
 237
 238 static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
 239                                    struct mmc_cmd *cmd, u32 cmd_param)
 240 {
 241         if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
 242                 writel(0, priv->base + SDMMC_CMD);
 243
 244         cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
 245         if (cmd->resp_type & MMC_RSP_PRESENT) {
 246                 if (cmd->resp_type & MMC_RSP_136)
 247                         cmd_param |= SDMMC_CMD_WAITRESP;
 248                 else if (cmd->resp_type & MMC_RSP_CRC)
 249                         cmd_param |= SDMMC_CMD_WAITRESP_0;
 250                 else
 251                         cmd_param |= SDMMC_CMD_WAITRESP_1;
 252         }
 253
 254         /* Clear flags */
 255         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 256
 257         /* Set SDMMC argument value */
 258         writel(cmd->cmdarg, priv->base + SDMMC_ARG);
 259
 260         /* Set SDMMC command parameters */
 261         writel(cmd_param, priv->base + SDMMC_CMD);
 262 }
 263
 264 static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
 265                                 struct mmc_cmd *cmd,
 266                                 struct stm32_sdmmc2_ctx *ctx)
 267 {
 268         u32 mask = SDMMC_STA_CTIMEOUT;
 269         u32 status;
 270         int ret;
 271
 272         if (cmd->resp_type & MMC_RSP_PRESENT) {
 273                 mask |= SDMMC_STA_CMDREND;
 274                 if (cmd->resp_type & MMC_RSP_CRC)
 275                         mask |= SDMMC_STA_CCRCFAIL;
 276         } else {
 277                 mask |= SDMMC_STA_CMDSENT;
 278         }
 279
 280         /* Polling status register */
 281         ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
 282                                  10000);
 283
 284         if (ret < 0) {
 285                 debug("%s: timeout reading SDMMC_STA register\n", __func__);
 286                 ctx->dpsm_abort = true;
 287                 return ret;
 288         }
 289
 290         /* Check status */
 291         if (status & SDMMC_STA_CTIMEOUT) {
 292                 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
 293                       __func__, status, cmd->cmdidx);
 294                 ctx->dpsm_abort = true;
 295                 return -ETIMEDOUT;
 296         }
 297
 298         if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
 299                 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
 300                       __func__, status, cmd->cmdidx);
 301                 ctx->dpsm_abort = true;
 302                 return -EILSEQ;
 303         }
 304
 305         if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
 306                 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
 307                 if (cmd->resp_type & MMC_RSP_136) {
 308                         cmd->response[1] = readl(priv->base + SDMMC_RESP2);
 309                         cmd->response[2] = readl(priv->base + SDMMC_RESP3);
 310                         cmd->response[3] = readl(priv->base + SDMMC_RESP4);
 311                 }
 312         }
 313
 314         return 0;
 315 }
 316
 317 static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
 318                                  struct mmc_cmd *cmd,
 319                                  struct mmc_data *data,
 320                                  struct stm32_sdmmc2_ctx *ctx)
 321 {
 322         u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 323                    SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 324         u32 status;
 325
 326         if (data->flags & MMC_DATA_READ)
 327                 mask |= SDMMC_STA_RXOVERR;
 328         else
 329                 mask |= SDMMC_STA_TXUNDERR;
 330
 331         status = readl(priv->base + SDMMC_STA);
 332         while (!(status & mask))
 333                 status = readl(priv->base + SDMMC_STA);
 334
 335         /*
 336          * Need invalidate the dcache again to avoid any
 337          * cache-refill during the DMA operations (pre-fetching)
 338          */
 339         if (data->flags & MMC_DATA_READ)
 340                 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
 341
 342         if (status & SDMMC_STA_DCRCFAIL) {
 343                 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
 344                       __func__, status, cmd->cmdidx);
 345                 if (readl(priv->base + SDMMC_DCOUNT))
 346                         ctx->dpsm_abort = true;
 347                 return -EILSEQ;
 348         }
 349
 350         if (status & SDMMC_STA_DTIMEOUT) {
 351                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
 352                       __func__, status, cmd->cmdidx);
 353                 ctx->dpsm_abort = true;
 354                 return -ETIMEDOUT;
 355         }
 356
 357         if (status & SDMMC_STA_TXUNDERR) {
 358                 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
 359                       __func__, status, cmd->cmdidx);
 360                 ctx->dpsm_abort = true;
 361                 return -EIO;
 362         }
 363
 364         if (status & SDMMC_STA_RXOVERR) {
 365                 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
 366                       __func__, status, cmd->cmdidx);
 367                 ctx->dpsm_abort = true;
 368                 return -EIO;
 369         }
 370
 371         if (status & SDMMC_STA_IDMATE) {
 372                 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
 373                       __func__, status, cmd->cmdidx);
 374                 ctx->dpsm_abort = true;
 375                 return -EIO;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 382                                  struct mmc_data *data)
 383 {
 384         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 385         struct stm32_sdmmc2_ctx ctx;
 386         u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
 387         int ret, retry = 3;
 388
 389 retry_cmd:
 390         ctx.data_length = 0;
 391         ctx.dpsm_abort = false;
 392
 393         if (data) {
 394                 ctx.data_length = data->blocks * data->blocksize;
 395                 stm32_sdmmc2_start_data(priv, data, &ctx);
 396         }
 397
 398         stm32_sdmmc2_start_cmd(priv, cmd, cmdat);
 399
 400         debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
 401               __func__, cmd->cmdidx,
 402               data ? ctx.data_length : 0, (unsigned int)data);
 403
 404         ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
 405
 406         if (data && !ret)
 407                 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
 408
 409         /* Clear flags */
 410         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 411         if (data)
 412                 writel(0x0, priv->base + SDMMC_IDMACTRL);
 413
 414         /*
 415          * To stop Data Path State Machine, a stop_transmission command
 416          * shall be send on cmd or data errors.
 417          */
 418         if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
 419                 struct mmc_cmd stop_cmd;
 420
 421                 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 422                 stop_cmd.cmdarg = 0;
 423                 stop_cmd.resp_type = MMC_RSP_R1b;
 424
 425                 debug("%s: send STOP command to abort dpsm treatments\n",
 426                       __func__);
 427
 428                 stm32_sdmmc2_start_cmd(priv, &stop_cmd, SDMMC_CMD_CMDSTOP);
 429                 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
 430
 431                 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 432         }
 433
 434         if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
 435                 printf("%s: cmd %d failed, retrying ...\n",
 436                        __func__, cmd->cmdidx);
 437                 retry--;
 438                 goto retry_cmd;
 439         }
 440
 441         debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
 442
 443         return ret;
 444 }
 445
 446 /*
 447  * Reset the SDMMC with the RCC.SDMMCxRST register bit.
 448  * This will reset the SDMMC to the reset state and the CPSM and DPSM
 449  * to the Idle state. SDMMC is disabled, Signals Hiz.
 450  */
 451 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
 452 {
 453         /* Reset */
 454         reset_assert(&priv->reset_ctl);
 455         udelay(2);
 456         reset_deassert(&priv->reset_ctl);
 457
 458         /* init the needed SDMMC register after reset */
 459         writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
 460 }
 461
 462 /*
 463  * Set the SDMMC in power-cycle state.
 464  * This will make that the SDMMC_D[7:0],
 465  * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
 466  * supplied through the signal lines.
 467  */
 468 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
 469 {
 470         if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
 471             SDMMC_POWER_PWRCTRL_CYCLE)
 472                 return;
 473
 474         stm32_sdmmc2_reset(priv);
 475         writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 476                priv->base + SDMMC_POWER);
 477 }
 478
 479 /*
 480  * set the SDMMC state Power-on: the card is clocked
 481  * manage the SDMMC state control:
 482  * Reset => Power-Cycle => Power-Off => Power
 483  *    PWRCTRL=10     PWCTRL=00    PWCTRL=11
 484  */
 485 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
 486 {
 487         u32 pwrctrl =
 488                 readl(priv->base + SDMMC_POWER) &  SDMMC_POWER_PWRCTRL_MASK;
 489
 490         if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
 491                 return;
 492
 493         /* warning: same PWRCTRL value after reset and for power-off state
 494          * it is the reset state here = the only managed by the driver
 495          */
 496         if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
 497                 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 498                        priv->base + SDMMC_POWER);
 499         }
 500
 501         /*
 502          * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
 503          * switch to Power-Off state: SDMCC disable, signals drive 1
 504          */
 505         writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
 506                priv->base + SDMMC_POWER);
 507
 508         /* After the 1ms delay set the SDMMC to power-on */
 509         mdelay(1);
 510         writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
 511                priv->base + SDMMC_POWER);
 512
 513         /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
 514 }
 515
 516 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
 517 static int stm32_sdmmc2_set_ios(struct udevice *dev)
 518 {
 519         struct mmc *mmc = mmc_get_mmc_dev(dev);
 520         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 521         u32 desired = mmc->clock;
 522         u32 sys_clock = clk_get_rate(&priv->clk);
 523         u32 clk = 0;
 524
 525         debug("%s: bus_with = %d, clock = %d\n", __func__,
 526               mmc->bus_width, mmc->clock);
 527
 528         if (mmc->clk_disable)
 529                 stm32_sdmmc2_pwrcycle(priv);
 530         else
 531                 stm32_sdmmc2_pwron(priv);
 532
 533         /*
 534          * clk_div = 0 => command and data generated on SDMMCCLK falling edge
 535          * clk_div > 0 and NEGEDGE = 0 => command and data generated on
 536          * SDMMCCLK rising edge
 537          * clk_div > 0 and NEGEDGE = 1 => command and data generated on
 538          * SDMMCCLK falling edge
 539          */
 540         if (desired && ((sys_clock > desired) ||
 541                         IS_RISING_EDGE(priv->clk_reg_msk))) {
 542                 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
 543                 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
 544                         clk = SDMMC_CLKCR_CLKDIV_MAX;
 545         }
 546
 547         if (mmc->bus_width == 4)
 548                 clk |= SDMMC_CLKCR_WIDBUS_4;
 549         if (mmc->bus_width == 8)
 550                 clk |= SDMMC_CLKCR_WIDBUS_8;
 551
 552         writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
 553                priv->base + SDMMC_CLKCR);
 554
 555         return 0;
 556 }
 557
 558 static int stm32_sdmmc2_getcd(struct udevice *dev)
 559 {
 560         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 561
 562         debug("stm32_sdmmc2_getcd called\n");
 563
 564         if (dm_gpio_is_valid(&priv->cd_gpio))
 565                 return dm_gpio_get_value(&priv->cd_gpio);
 566
 567         return 1;
 568 }
 569
 570 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
 571         .send_cmd = stm32_sdmmc2_send_cmd,
 572         .set_ios = stm32_sdmmc2_set_ios,
 573         .get_cd = stm32_sdmmc2_getcd,
 574 };
 575
 576 static int stm32_sdmmc2_probe(struct udevice *dev)
 577 {
 578         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 579         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 580         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 581         struct mmc_config *cfg = &plat->cfg;
 582         int ret;
 583
 584         priv->base = dev_read_addr(dev);
 585         if (priv->base == FDT_ADDR_T_NONE)
 586                 return -EINVAL;
 587
 588         if (dev_read_bool(dev, "st,negedge"))
 589                 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
 590         if (dev_read_bool(dev, "st,dirpol"))
 591                 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
 592         if (dev_read_bool(dev, "st,pin-ckin"))
 593                 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
 594
 595         ret = clk_get_by_index(dev, 0, &priv->clk);
 596         if (ret)
 597                 return ret;
 598
 599         ret = clk_enable(&priv->clk);
 600         if (ret)
 601                 goto clk_free;
 602
 603         ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
 604         if (ret)
 605                 goto clk_disable;
 606
 607         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 608                              GPIOD_IS_IN);
 609
 610         cfg->f_min = 400000;
 611         cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
 612         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 613         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 614         cfg->name = "STM32 SDMMC2";
 615
 616         cfg->host_caps = 0;
 617         if (cfg->f_max > 25000000)
 618                 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 619
 620         switch (dev_read_u32_default(dev, "bus-width", 1)) {
 621         case 8:
 622                 cfg->host_caps |= MMC_MODE_8BIT;
 623         case 4:
 624                 cfg->host_caps |= MMC_MODE_4BIT;
 625                 break;
 626         case 1:
 627                 break;
 628         default:
 629                 pr_err("invalid \"bus-width\" property, force to 1\n");
 630         }
 631
 632         upriv->mmc = &plat->mmc;
 633
 634         /* SDMMC init */
 635         stm32_sdmmc2_reset(priv);
 636         return 0;
 637
 638 clk_disable:
 639         clk_disable(&priv->clk);
 640 clk_free:
 641         clk_free(&priv->clk);
 642
 643         return ret;
 644 }
 645
 646 int stm32_sdmmc_bind(struct udevice *dev)
 647 {
 648         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 649
 650         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 651 }
 652
 653 static const struct udevice_id stm32_sdmmc2_ids[] = {
 654         { .compatible = "st,stm32-sdmmc2" },
 655         { }
 656 };
 657
 658 U_BOOT_DRIVER(stm32_sdmmc2) = {
 659         .name = "stm32_sdmmc2",
 660         .id = UCLASS_MMC,
 661         .of_match = stm32_sdmmc2_ids,
 662         .ops = &stm32_sdmmc2_ops,
 663         .probe = stm32_sdmmc2_probe,
 664         .bind = stm32_sdmmc_bind,
 665         .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
 666         .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
 667 };