drivers/mmc/stm32_sdmmc2.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   4  * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
   5  */
   6
   7 #include <common.h>
   8 #include <clk.h>
   9 #include <cpu_func.h>
  10 #include <dm.h>
  11 #include <fdtdec.h>
  12 #include <linux/libfdt.h>
  13 #include <mmc.h>
  14 #include <reset.h>
  15 #include <asm/io.h>
  16 #include <asm/gpio.h>
  17 #include <linux/iopoll.h>
  18 #include <watchdog.h>
  19
  20 struct stm32_sdmmc2_plat {
  21         struct mmc_config cfg;
  22         struct mmc mmc;
  23 };
  24
  25 struct stm32_sdmmc2_priv {
  26         fdt_addr_t base;
  27         struct clk clk;
  28         struct reset_ctl reset_ctl;
  29         struct gpio_desc cd_gpio;
  30         u32 clk_reg_msk;
  31         u32 pwr_reg_msk;
  32 };
  33
  34 struct stm32_sdmmc2_ctx {
  35         u32 cache_start;
  36         u32 cache_end;
  37         u32 data_length;
  38         bool dpsm_abort;
  39 };
  40
  41 /* SDMMC REGISTERS OFFSET */
  42 #define SDMMC_POWER             0x00    /* SDMMC power control             */
  43 #define SDMMC_CLKCR             0x04    /* SDMMC clock control             */
  44 #define SDMMC_ARG               0x08    /* SDMMC argument                  */
  45 #define SDMMC_CMD               0x0C    /* SDMMC command                   */
  46 #define SDMMC_RESP1             0x14    /* SDMMC response 1                */
  47 #define SDMMC_RESP2             0x18    /* SDMMC response 2                */
  48 #define SDMMC_RESP3             0x1C    /* SDMMC response 3                */
  49 #define SDMMC_RESP4             0x20    /* SDMMC response 4                */
  50 #define SDMMC_DTIMER            0x24    /* SDMMC data timer                */
  51 #define SDMMC_DLEN              0x28    /* SDMMC data length               */
  52 #define SDMMC_DCTRL             0x2C    /* SDMMC data control              */
  53 #define SDMMC_DCOUNT            0x30    /* SDMMC data counter              */
  54 #define SDMMC_STA               0x34    /* SDMMC status                    */
  55 #define SDMMC_ICR               0x38    /* SDMMC interrupt clear           */
  56 #define SDMMC_MASK              0x3C    /* SDMMC mask                      */
  57 #define SDMMC_IDMACTRL          0x50    /* SDMMC DMA control               */
  58 #define SDMMC_IDMABASE0         0x58    /* SDMMC DMA buffer 0 base address */
  59
  60 /* SDMMC_POWER register */
  61 #define SDMMC_POWER_PWRCTRL_MASK        GENMASK(1, 0)
  62 #define SDMMC_POWER_PWRCTRL_OFF         0
  63 #define SDMMC_POWER_PWRCTRL_CYCLE       2
  64 #define SDMMC_POWER_PWRCTRL_ON          3
  65 #define SDMMC_POWER_VSWITCH             BIT(2)
  66 #define SDMMC_POWER_VSWITCHEN           BIT(3)
  67 #define SDMMC_POWER_DIRPOL              BIT(4)
  68
  69 /* SDMMC_CLKCR register */
  70 #define SDMMC_CLKCR_CLKDIV              GENMASK(9, 0)
  71 #define SDMMC_CLKCR_CLKDIV_MAX          SDMMC_CLKCR_CLKDIV
  72 #define SDMMC_CLKCR_PWRSAV              BIT(12)
  73 #define SDMMC_CLKCR_WIDBUS_4            BIT(14)
  74 #define SDMMC_CLKCR_WIDBUS_8            BIT(15)
  75 #define SDMMC_CLKCR_NEGEDGE             BIT(16)
  76 #define SDMMC_CLKCR_HWFC_EN             BIT(17)
  77 #define SDMMC_CLKCR_DDR                 BIT(18)
  78 #define SDMMC_CLKCR_BUSSPEED            BIT(19)
  79 #define SDMMC_CLKCR_SELCLKRX_MASK       GENMASK(21, 20)
  80 #define SDMMC_CLKCR_SELCLKRX_CK         0
  81 #define SDMMC_CLKCR_SELCLKRX_CKIN       BIT(20)
  82 #define SDMMC_CLKCR_SELCLKRX_FBCK       BIT(21)
  83
  84 /* SDMMC_CMD register */
  85 #define SDMMC_CMD_CMDINDEX              GENMASK(5, 0)
  86 #define SDMMC_CMD_CMDTRANS              BIT(6)
  87 #define SDMMC_CMD_CMDSTOP               BIT(7)
  88 #define SDMMC_CMD_WAITRESP              GENMASK(9, 8)
  89 #define SDMMC_CMD_WAITRESP_0            BIT(8)
  90 #define SDMMC_CMD_WAITRESP_1            BIT(9)
  91 #define SDMMC_CMD_WAITINT               BIT(10)
  92 #define SDMMC_CMD_WAITPEND              BIT(11)
  93 #define SDMMC_CMD_CPSMEN                BIT(12)
  94 #define SDMMC_CMD_DTHOLD                BIT(13)
  95 #define SDMMC_CMD_BOOTMODE              BIT(14)
  96 #define SDMMC_CMD_BOOTEN                BIT(15)
  97 #define SDMMC_CMD_CMDSUSPEND            BIT(16)
  98
  99 /* SDMMC_DCTRL register */
 100 #define SDMMC_DCTRL_DTEN                BIT(0)
 101 #define SDMMC_DCTRL_DTDIR               BIT(1)
 102 #define SDMMC_DCTRL_DTMODE              GENMASK(3, 2)
 103 #define SDMMC_DCTRL_DBLOCKSIZE          GENMASK(7, 4)
 104 #define SDMMC_DCTRL_DBLOCKSIZE_SHIFT    4
 105 #define SDMMC_DCTRL_RWSTART             BIT(8)
 106 #define SDMMC_DCTRL_RWSTOP              BIT(9)
 107 #define SDMMC_DCTRL_RWMOD               BIT(10)
 108 #define SDMMC_DCTRL_SDMMCEN             BIT(11)
 109 #define SDMMC_DCTRL_BOOTACKEN           BIT(12)
 110 #define SDMMC_DCTRL_FIFORST             BIT(13)
 111
 112 /* SDMMC_STA register */
 113 #define SDMMC_STA_CCRCFAIL              BIT(0)
 114 #define SDMMC_STA_DCRCFAIL              BIT(1)
 115 #define SDMMC_STA_CTIMEOUT              BIT(2)
 116 #define SDMMC_STA_DTIMEOUT              BIT(3)
 117 #define SDMMC_STA_TXUNDERR              BIT(4)
 118 #define SDMMC_STA_RXOVERR               BIT(5)
 119 #define SDMMC_STA_CMDREND               BIT(6)
 120 #define SDMMC_STA_CMDSENT               BIT(7)
 121 #define SDMMC_STA_DATAEND               BIT(8)
 122 #define SDMMC_STA_DHOLD                 BIT(9)
 123 #define SDMMC_STA_DBCKEND               BIT(10)
 124 #define SDMMC_STA_DABORT                BIT(11)
 125 #define SDMMC_STA_DPSMACT               BIT(12)
 126 #define SDMMC_STA_CPSMACT               BIT(13)
 127 #define SDMMC_STA_TXFIFOHE              BIT(14)
 128 #define SDMMC_STA_RXFIFOHF              BIT(15)
 129 #define SDMMC_STA_TXFIFOF               BIT(16)
 130 #define SDMMC_STA_RXFIFOF               BIT(17)
 131 #define SDMMC_STA_TXFIFOE               BIT(18)
 132 #define SDMMC_STA_RXFIFOE               BIT(19)
 133 #define SDMMC_STA_BUSYD0                BIT(20)
 134 #define SDMMC_STA_BUSYD0END             BIT(21)
 135 #define SDMMC_STA_SDMMCIT               BIT(22)
 136 #define SDMMC_STA_ACKFAIL               BIT(23)
 137 #define SDMMC_STA_ACKTIMEOUT            BIT(24)
 138 #define SDMMC_STA_VSWEND                BIT(25)
 139 #define SDMMC_STA_CKSTOP                BIT(26)
 140 #define SDMMC_STA_IDMATE                BIT(27)
 141 #define SDMMC_STA_IDMABTC               BIT(28)
 142
 143 /* SDMMC_ICR register */
 144 #define SDMMC_ICR_CCRCFAILC             BIT(0)
 145 #define SDMMC_ICR_DCRCFAILC             BIT(1)
 146 #define SDMMC_ICR_CTIMEOUTC             BIT(2)
 147 #define SDMMC_ICR_DTIMEOUTC             BIT(3)
 148 #define SDMMC_ICR_TXUNDERRC             BIT(4)
 149 #define SDMMC_ICR_RXOVERRC              BIT(5)
 150 #define SDMMC_ICR_CMDRENDC              BIT(6)
 151 #define SDMMC_ICR_CMDSENTC              BIT(7)
 152 #define SDMMC_ICR_DATAENDC              BIT(8)
 153 #define SDMMC_ICR_DHOLDC                BIT(9)
 154 #define SDMMC_ICR_DBCKENDC              BIT(10)
 155 #define SDMMC_ICR_DABORTC               BIT(11)
 156 #define SDMMC_ICR_BUSYD0ENDC            BIT(21)
 157 #define SDMMC_ICR_SDMMCITC              BIT(22)
 158 #define SDMMC_ICR_ACKFAILC              BIT(23)
 159 #define SDMMC_ICR_ACKTIMEOUTC           BIT(24)
 160 #define SDMMC_ICR_VSWENDC               BIT(25)
 161 #define SDMMC_ICR_CKSTOPC               BIT(26)
 162 #define SDMMC_ICR_IDMATEC               BIT(27)
 163 #define SDMMC_ICR_IDMABTCC              BIT(28)
 164 #define SDMMC_ICR_STATIC_FLAGS          ((GENMASK(28, 21)) | (GENMASK(11, 0)))
 165
 166 /* SDMMC_MASK register */
 167 #define SDMMC_MASK_CCRCFAILIE           BIT(0)
 168 #define SDMMC_MASK_DCRCFAILIE           BIT(1)
 169 #define SDMMC_MASK_CTIMEOUTIE           BIT(2)
 170 #define SDMMC_MASK_DTIMEOUTIE           BIT(3)
 171 #define SDMMC_MASK_TXUNDERRIE           BIT(4)
 172 #define SDMMC_MASK_RXOVERRIE            BIT(5)
 173 #define SDMMC_MASK_CMDRENDIE            BIT(6)
 174 #define SDMMC_MASK_CMDSENTIE            BIT(7)
 175 #define SDMMC_MASK_DATAENDIE            BIT(8)
 176 #define SDMMC_MASK_DHOLDIE              BIT(9)
 177 #define SDMMC_MASK_DBCKENDIE            BIT(10)
 178 #define SDMMC_MASK_DABORTIE             BIT(11)
 179 #define SDMMC_MASK_TXFIFOHEIE           BIT(14)
 180 #define SDMMC_MASK_RXFIFOHFIE           BIT(15)
 181 #define SDMMC_MASK_RXFIFOFIE            BIT(17)
 182 #define SDMMC_MASK_TXFIFOEIE            BIT(18)
 183 #define SDMMC_MASK_BUSYD0ENDIE          BIT(21)
 184 #define SDMMC_MASK_SDMMCITIE            BIT(22)
 185 #define SDMMC_MASK_ACKFAILIE            BIT(23)
 186 #define SDMMC_MASK_ACKTIMEOUTIE         BIT(24)
 187 #define SDMMC_MASK_VSWENDIE             BIT(25)
 188 #define SDMMC_MASK_CKSTOPIE             BIT(26)
 189 #define SDMMC_MASK_IDMABTCIE            BIT(28)
 190
 191 /* SDMMC_IDMACTRL register */
 192 #define SDMMC_IDMACTRL_IDMAEN           BIT(0)
 193
 194 #define SDMMC_CMD_TIMEOUT               0xFFFFFFFF
 195 #define SDMMC_BUSYD0END_TIMEOUT_US      2000000
 196
 197 static void stm32_sdmmc2_start_data(struct stm32_sdmmc2_priv *priv,
 198                                     struct mmc_data *data,
 199                                     struct stm32_sdmmc2_ctx *ctx)
 200 {
 201         u32 data_ctrl, idmabase0;
 202
 203         /* Configure the SDMMC DPSM (Data Path State Machine) */
 204         data_ctrl = (__ilog2(data->blocksize) <<
 205                      SDMMC_DCTRL_DBLOCKSIZE_SHIFT) &
 206                     SDMMC_DCTRL_DBLOCKSIZE;
 207
 208         if (data->flags & MMC_DATA_READ) {
 209                 data_ctrl |= SDMMC_DCTRL_DTDIR;
 210                 idmabase0 = (u32)data->dest;
 211         } else {
 212                 idmabase0 = (u32)data->src;
 213         }
 214
 215         /* Set the SDMMC DataLength value */
 216         writel(ctx->data_length, priv->base + SDMMC_DLEN);
 217
 218         /* Write to SDMMC DCTRL */
 219         writel(data_ctrl, priv->base + SDMMC_DCTRL);
 220
 221         /* Cache align */
 222         ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN);
 223         ctx->cache_end = roundup(idmabase0 + ctx->data_length,
 224                                  ARCH_DMA_MINALIGN);
 225
 226         /*
 227          * Flush data cache before DMA start (clean and invalidate)
 228          * Clean also needed for read
 229          * Avoid issue on buffer not cached-aligned
 230          */
 231         flush_dcache_range(ctx->cache_start, ctx->cache_end);
 232
 233         /* Enable internal DMA */
 234         writel(idmabase0, priv->base + SDMMC_IDMABASE0);
 235         writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL);
 236 }
 237
 238 static void stm32_sdmmc2_start_cmd(struct stm32_sdmmc2_priv *priv,
 239                                    struct mmc_cmd *cmd, u32 cmd_param,
 240                                    struct stm32_sdmmc2_ctx *ctx)
 241 {
 242         u32 timeout = 0;
 243
 244         if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN)
 245                 writel(0, priv->base + SDMMC_CMD);
 246
 247         cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN;
 248         if (cmd->resp_type & MMC_RSP_PRESENT) {
 249                 if (cmd->resp_type & MMC_RSP_136)
 250                         cmd_param |= SDMMC_CMD_WAITRESP;
 251                 else if (cmd->resp_type & MMC_RSP_CRC)
 252                         cmd_param |= SDMMC_CMD_WAITRESP_0;
 253                 else
 254                         cmd_param |= SDMMC_CMD_WAITRESP_1;
 255         }
 256
 257         /*
 258          * SDMMC_DTIME must be set in two case:
 259          * - on data transfert.
 260          * - on busy request.
 261          * If not done or too short, the dtimeout flag occurs and DPSM stays
 262          * enabled/busy and waits for abort (stop transmission cmd).
 263          * Next data command is not possible whereas DPSM is activated.
 264          */
 265         if (ctx->data_length) {
 266                 timeout = SDMMC_CMD_TIMEOUT;
 267         } else {
 268                 writel(0, priv->base + SDMMC_DCTRL);
 269
 270                 if (cmd->resp_type & MMC_RSP_BUSY)
 271                         timeout = SDMMC_CMD_TIMEOUT;
 272         }
 273
 274         /* Set the SDMMC Data TimeOut value */
 275         writel(timeout, priv->base + SDMMC_DTIMER);
 276
 277         /* Clear flags */
 278         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 279
 280         /* Set SDMMC argument value */
 281         writel(cmd->cmdarg, priv->base + SDMMC_ARG);
 282
 283         /* Set SDMMC command parameters */
 284         writel(cmd_param, priv->base + SDMMC_CMD);
 285 }
 286
 287 static int stm32_sdmmc2_end_cmd(struct stm32_sdmmc2_priv *priv,
 288                                 struct mmc_cmd *cmd,
 289                                 struct stm32_sdmmc2_ctx *ctx)
 290 {
 291         u32 mask = SDMMC_STA_CTIMEOUT;
 292         u32 status;
 293         int ret;
 294
 295         if (cmd->resp_type & MMC_RSP_PRESENT) {
 296                 mask |= SDMMC_STA_CMDREND;
 297                 if (cmd->resp_type & MMC_RSP_CRC)
 298                         mask |= SDMMC_STA_CCRCFAIL;
 299         } else {
 300                 mask |= SDMMC_STA_CMDSENT;
 301         }
 302
 303         /* Polling status register */
 304         ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask,
 305                                  10000);
 306
 307         if (ret < 0) {
 308                 debug("%s: timeout reading SDMMC_STA register\n", __func__);
 309                 ctx->dpsm_abort = true;
 310                 return ret;
 311         }
 312
 313         /* Check status */
 314         if (status & SDMMC_STA_CTIMEOUT) {
 315                 debug("%s: error SDMMC_STA_CTIMEOUT (0x%x) for cmd %d\n",
 316                       __func__, status, cmd->cmdidx);
 317                 ctx->dpsm_abort = true;
 318                 return -ETIMEDOUT;
 319         }
 320
 321         if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) {
 322                 debug("%s: error SDMMC_STA_CCRCFAIL (0x%x) for cmd %d\n",
 323                       __func__, status, cmd->cmdidx);
 324                 ctx->dpsm_abort = true;
 325                 return -EILSEQ;
 326         }
 327
 328         if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) {
 329                 cmd->response[0] = readl(priv->base + SDMMC_RESP1);
 330                 if (cmd->resp_type & MMC_RSP_136) {
 331                         cmd->response[1] = readl(priv->base + SDMMC_RESP2);
 332                         cmd->response[2] = readl(priv->base + SDMMC_RESP3);
 333                         cmd->response[3] = readl(priv->base + SDMMC_RESP4);
 334                 }
 335
 336                 /* Wait for BUSYD0END flag if busy status is detected */
 337                 if (cmd->resp_type & MMC_RSP_BUSY &&
 338                     status & SDMMC_STA_BUSYD0) {
 339                         mask = SDMMC_STA_DTIMEOUT | SDMMC_STA_BUSYD0END;
 340
 341                         /* Polling status register */
 342                         ret = readl_poll_timeout(priv->base + SDMMC_STA,
 343                                                  status, status & mask,
 344                                                  SDMMC_BUSYD0END_TIMEOUT_US);
 345
 346                         if (ret < 0) {
 347                                 debug("%s: timeout reading SDMMC_STA\n",
 348                                       __func__);
 349                                 ctx->dpsm_abort = true;
 350                                 return ret;
 351                         }
 352
 353                         if (status & SDMMC_STA_DTIMEOUT) {
 354                                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x)\n",
 355                                       __func__, status);
 356                                 ctx->dpsm_abort = true;
 357                                 return -ETIMEDOUT;
 358                         }
 359                 }
 360         }
 361
 362         return 0;
 363 }
 364
 365 static int stm32_sdmmc2_end_data(struct stm32_sdmmc2_priv *priv,
 366                                  struct mmc_cmd *cmd,
 367                                  struct mmc_data *data,
 368                                  struct stm32_sdmmc2_ctx *ctx)
 369 {
 370         u32 mask = SDMMC_STA_DCRCFAIL | SDMMC_STA_DTIMEOUT |
 371                    SDMMC_STA_IDMATE | SDMMC_STA_DATAEND;
 372         u32 status;
 373
 374         if (data->flags & MMC_DATA_READ)
 375                 mask |= SDMMC_STA_RXOVERR;
 376         else
 377                 mask |= SDMMC_STA_TXUNDERR;
 378
 379         status = readl(priv->base + SDMMC_STA);
 380         while (!(status & mask))
 381                 status = readl(priv->base + SDMMC_STA);
 382
 383         /*
 384          * Need invalidate the dcache again to avoid any
 385          * cache-refill during the DMA operations (pre-fetching)
 386          */
 387         if (data->flags & MMC_DATA_READ)
 388                 invalidate_dcache_range(ctx->cache_start, ctx->cache_end);
 389
 390         if (status & SDMMC_STA_DCRCFAIL) {
 391                 debug("%s: error SDMMC_STA_DCRCFAIL (0x%x) for cmd %d\n",
 392                       __func__, status, cmd->cmdidx);
 393                 if (readl(priv->base + SDMMC_DCOUNT))
 394                         ctx->dpsm_abort = true;
 395                 return -EILSEQ;
 396         }
 397
 398         if (status & SDMMC_STA_DTIMEOUT) {
 399                 debug("%s: error SDMMC_STA_DTIMEOUT (0x%x) for cmd %d\n",
 400                       __func__, status, cmd->cmdidx);
 401                 ctx->dpsm_abort = true;
 402                 return -ETIMEDOUT;
 403         }
 404
 405         if (status & SDMMC_STA_TXUNDERR) {
 406                 debug("%s: error SDMMC_STA_TXUNDERR (0x%x) for cmd %d\n",
 407                       __func__, status, cmd->cmdidx);
 408                 ctx->dpsm_abort = true;
 409                 return -EIO;
 410         }
 411
 412         if (status & SDMMC_STA_RXOVERR) {
 413                 debug("%s: error SDMMC_STA_RXOVERR (0x%x) for cmd %d\n",
 414                       __func__, status, cmd->cmdidx);
 415                 ctx->dpsm_abort = true;
 416                 return -EIO;
 417         }
 418
 419         if (status & SDMMC_STA_IDMATE) {
 420                 debug("%s: error SDMMC_STA_IDMATE (0x%x) for cmd %d\n",
 421                       __func__, status, cmd->cmdidx);
 422                 ctx->dpsm_abort = true;
 423                 return -EIO;
 424         }
 425
 426         return 0;
 427 }
 428
 429 static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 430                                  struct mmc_data *data)
 431 {
 432         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 433         struct stm32_sdmmc2_ctx ctx;
 434         u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
 435         int ret, retry = 3;
 436
 437         WATCHDOG_RESET();
 438
 439 retry_cmd:
 440         ctx.data_length = 0;
 441         ctx.dpsm_abort = false;
 442
 443         if (data) {
 444                 ctx.data_length = data->blocks * data->blocksize;
 445                 stm32_sdmmc2_start_data(priv, data, &ctx);
 446         }
 447
 448         stm32_sdmmc2_start_cmd(priv, cmd, cmdat, &ctx);
 449
 450         debug("%s: send cmd %d data: 0x%x @ 0x%x\n",
 451               __func__, cmd->cmdidx,
 452               data ? ctx.data_length : 0, (unsigned int)data);
 453
 454         ret = stm32_sdmmc2_end_cmd(priv, cmd, &ctx);
 455
 456         if (data && !ret)
 457                 ret = stm32_sdmmc2_end_data(priv, cmd, data, &ctx);
 458
 459         /* Clear flags */
 460         writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 461         if (data)
 462                 writel(0x0, priv->base + SDMMC_IDMACTRL);
 463
 464         /*
 465          * To stop Data Path State Machine, a stop_transmission command
 466          * shall be send on cmd or data errors.
 467          */
 468         if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
 469                 struct mmc_cmd stop_cmd;
 470
 471                 stop_cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
 472                 stop_cmd.cmdarg = 0;
 473                 stop_cmd.resp_type = MMC_RSP_R1b;
 474
 475                 debug("%s: send STOP command to abort dpsm treatments\n",
 476                       __func__);
 477
 478                 ctx.data_length = 0;
 479
 480                 stm32_sdmmc2_start_cmd(priv, &stop_cmd,
 481                                        SDMMC_CMD_CMDSTOP, &ctx);
 482                 stm32_sdmmc2_end_cmd(priv, &stop_cmd, &ctx);
 483
 484                 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR);
 485         }
 486
 487         if ((ret != -ETIMEDOUT) && (ret != 0) && retry) {
 488                 printf("%s: cmd %d failed, retrying ...\n",
 489                        __func__, cmd->cmdidx);
 490                 retry--;
 491                 goto retry_cmd;
 492         }
 493
 494         debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret);
 495
 496         return ret;
 497 }
 498
 499 /*
 500  * Reset the SDMMC with the RCC.SDMMCxRST register bit.
 501  * This will reset the SDMMC to the reset state and the CPSM and DPSM
 502  * to the Idle state. SDMMC is disabled, Signals Hiz.
 503  */
 504 static void stm32_sdmmc2_reset(struct stm32_sdmmc2_priv *priv)
 505 {
 506         /* Reset */
 507         reset_assert(&priv->reset_ctl);
 508         udelay(2);
 509         reset_deassert(&priv->reset_ctl);
 510
 511         /* init the needed SDMMC register after reset */
 512         writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER);
 513 }
 514
 515 /*
 516  * Set the SDMMC in power-cycle state.
 517  * This will make that the SDMMC_D[7:0],
 518  * SDMMC_CMD and SDMMC_CK are driven low, to prevent the card from being
 519  * supplied through the signal lines.
 520  */
 521 static void stm32_sdmmc2_pwrcycle(struct stm32_sdmmc2_priv *priv)
 522 {
 523         if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) ==
 524             SDMMC_POWER_PWRCTRL_CYCLE)
 525                 return;
 526
 527         stm32_sdmmc2_reset(priv);
 528 }
 529
 530 /*
 531  * set the SDMMC state Power-on: the card is clocked
 532  * manage the SDMMC state control:
 533  * Reset => Power-Cycle => Power-Off => Power
 534  *    PWRCTRL=10     PWCTRL=00    PWCTRL=11
 535  */
 536 static void stm32_sdmmc2_pwron(struct stm32_sdmmc2_priv *priv)
 537 {
 538         u32 pwrctrl =
 539                 readl(priv->base + SDMMC_POWER) &  SDMMC_POWER_PWRCTRL_MASK;
 540
 541         if (pwrctrl == SDMMC_POWER_PWRCTRL_ON)
 542                 return;
 543
 544         /* warning: same PWRCTRL value after reset and for power-off state
 545          * it is the reset state here = the only managed by the driver
 546          */
 547         if (pwrctrl == SDMMC_POWER_PWRCTRL_OFF) {
 548                 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 549                        priv->base + SDMMC_POWER);
 550         }
 551
 552         /*
 553          * the remaining case is SDMMC_POWER_PWRCTRL_CYCLE
 554          * switch to Power-Off state: SDMCC disable, signals drive 1
 555          */
 556         writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk,
 557                priv->base + SDMMC_POWER);
 558
 559         /* After the 1ms delay set the SDMMC to power-on */
 560         mdelay(1);
 561         writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk,
 562                priv->base + SDMMC_POWER);
 563
 564         /* during the first 74 SDMMC_CK cycles the SDMMC is still disabled. */
 565 }
 566
 567 #define IS_RISING_EDGE(reg) (reg & SDMMC_CLKCR_NEGEDGE ? 0 : 1)
 568 static int stm32_sdmmc2_set_ios(struct udevice *dev)
 569 {
 570         struct mmc *mmc = mmc_get_mmc_dev(dev);
 571         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 572         u32 desired = mmc->clock;
 573         u32 sys_clock = clk_get_rate(&priv->clk);
 574         u32 clk = 0;
 575
 576         debug("%s: bus_with = %d, clock = %d\n", __func__,
 577               mmc->bus_width, mmc->clock);
 578
 579         if (mmc->clk_disable)
 580                 stm32_sdmmc2_pwrcycle(priv);
 581         else
 582                 stm32_sdmmc2_pwron(priv);
 583
 584         /*
 585          * clk_div = 0 => command and data generated on SDMMCCLK falling edge
 586          * clk_div > 0 and NEGEDGE = 0 => command and data generated on
 587          * SDMMCCLK rising edge
 588          * clk_div > 0 and NEGEDGE = 1 => command and data generated on
 589          * SDMMCCLK falling edge
 590          */
 591         if (desired && ((sys_clock > desired) ||
 592                         IS_RISING_EDGE(priv->clk_reg_msk))) {
 593                 clk = DIV_ROUND_UP(sys_clock, 2 * desired);
 594                 if (clk > SDMMC_CLKCR_CLKDIV_MAX)
 595                         clk = SDMMC_CLKCR_CLKDIV_MAX;
 596         }
 597
 598         if (mmc->bus_width == 4)
 599                 clk |= SDMMC_CLKCR_WIDBUS_4;
 600         if (mmc->bus_width == 8)
 601                 clk |= SDMMC_CLKCR_WIDBUS_8;
 602
 603         writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN,
 604                priv->base + SDMMC_CLKCR);
 605
 606         return 0;
 607 }
 608
 609 static int stm32_sdmmc2_getcd(struct udevice *dev)
 610 {
 611         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 612
 613         debug("stm32_sdmmc2_getcd called\n");
 614
 615         if (dm_gpio_is_valid(&priv->cd_gpio))
 616                 return dm_gpio_get_value(&priv->cd_gpio);
 617
 618         return 1;
 619 }
 620
 621 static int stm32_sdmmc2_host_power_cycle(struct udevice *dev)
 622 {
 623         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 624
 625         writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk,
 626                priv->base + SDMMC_POWER);
 627
 628         return 0;
 629 }
 630
 631 static const struct dm_mmc_ops stm32_sdmmc2_ops = {
 632         .send_cmd = stm32_sdmmc2_send_cmd,
 633         .set_ios = stm32_sdmmc2_set_ios,
 634         .get_cd = stm32_sdmmc2_getcd,
 635         .host_power_cycle = stm32_sdmmc2_host_power_cycle,
 636 };
 637
 638 static int stm32_sdmmc2_probe(struct udevice *dev)
 639 {
 640         struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 641         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 642         struct stm32_sdmmc2_priv *priv = dev_get_priv(dev);
 643         struct mmc_config *cfg = &plat->cfg;
 644         int ret;
 645
 646         priv->base = dev_read_addr(dev);
 647         if (priv->base == FDT_ADDR_T_NONE)
 648                 return -EINVAL;
 649
 650         if (dev_read_bool(dev, "st,neg-edge"))
 651                 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE;
 652         if (dev_read_bool(dev, "st,sig-dir"))
 653                 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL;
 654         if (dev_read_bool(dev, "st,use-ckin"))
 655                 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN;
 656
 657         ret = clk_get_by_index(dev, 0, &priv->clk);
 658         if (ret)
 659                 return ret;
 660
 661         ret = clk_enable(&priv->clk);
 662         if (ret)
 663                 goto clk_free;
 664
 665         ret = reset_get_by_index(dev, 0, &priv->reset_ctl);
 666         if (ret)
 667                 goto clk_disable;
 668
 669         gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
 670                              GPIOD_IS_IN);
 671
 672         cfg->f_min = 400000;
 673         cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000);
 674         cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 675         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 676         cfg->name = "STM32 SDMMC2";
 677
 678         cfg->host_caps = 0;
 679         if (cfg->f_max > 25000000)
 680                 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 681
 682         switch (dev_read_u32_default(dev, "bus-width", 1)) {
 683         case 8:
 684                 cfg->host_caps |= MMC_MODE_8BIT;
 685                 /* fall through */
 686         case 4:
 687                 cfg->host_caps |= MMC_MODE_4BIT;
 688                 break;
 689         case 1:
 690                 break;
 691         default:
 692                 pr_err("invalid \"bus-width\" property, force to 1\n");
 693         }
 694
 695         upriv->mmc = &plat->mmc;
 696
 697         /* SDMMC init */
 698         stm32_sdmmc2_reset(priv);
 699         return 0;
 700
 701 clk_disable:
 702         clk_disable(&priv->clk);
 703 clk_free:
 704         clk_free(&priv->clk);
 705
 706         return ret;
 707 }
 708
 709 static int stm32_sdmmc_bind(struct udevice *dev)
 710 {
 711         struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev);
 712
 713         return mmc_bind(dev, &plat->mmc, &plat->cfg);
 714 }
 715
 716 static const struct udevice_id stm32_sdmmc2_ids[] = {
 717         { .compatible = "st,stm32-sdmmc2" },
 718         { }
 719 };
 720
 721 U_BOOT_DRIVER(stm32_sdmmc2) = {
 722         .name = "stm32_sdmmc2",
 723         .id = UCLASS_MMC,
 724         .of_match = stm32_sdmmc2_ids,
 725         .ops = &stm32_sdmmc2_ops,
 726         .probe = stm32_sdmmc2_probe,
 727         .bind = stm32_sdmmc_bind,
 728         .priv_auto_alloc_size = sizeof(struct stm32_sdmmc2_priv),
 729         .platdata_auto_alloc_size = sizeof(struct stm32_sdmmc2_plat),
 730 };