drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <errno.h>
  12 #include <malloc.h>
  13 #include <mmc.h>
  14 #include <sdhci.h>
  15
  16 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  17 void *aligned_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  18 #else
  19 void *aligned_buffer;
  20 #endif
  21
  22 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  23 {
  24         unsigned long timeout;
  25
  26         /* Wait max 100 ms */
  27         timeout = 100;
  28         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  29         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  30                 if (timeout == 0) {
  31                         printf("%s: Reset 0x%x never completed.\n",
  32                                __func__, (int)mask);
  33                         return;
  34                 }
  35                 timeout--;
  36                 udelay(1000);
  37         }
  38 }
  39
  40 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  41 {
  42         int i;
  43         if (cmd->resp_type & MMC_RSP_136) {
  44                 /* CRC is stripped so we need to do some shifting. */
  45                 for (i = 0; i < 4; i++) {
  46                         cmd->response[i] = sdhci_readl(host,
  47                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  48                         if (i != 3)
  49                                 cmd->response[i] |= sdhci_readb(host,
  50                                                 SDHCI_RESPONSE + (3-i)*4-1);
  51                 }
  52         } else {
  53                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  54         }
  55 }
  56
  57 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  58 {
  59         int i;
  60         char *offs;
  61         for (i = 0; i < data->blocksize; i += 4) {
  62                 offs = data->dest + i;
  63                 if (data->flags == MMC_DATA_READ)
  64                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  65                 else
  66                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  67         }
  68 }
  69
  70 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  71 static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len,
  72                             bool end)
  73 {
  74         struct sdhci_adma_desc *desc;
  75         u8 attr;
  76
  77         desc = &host->adma_desc_table[host->desc_slot];
  78
  79         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  80         if (!end)
  81                 host->desc_slot++;
  82         else
  83                 attr |= ADMA_DESC_ATTR_END;
  84
  85         desc->attr = attr;
  86         desc->len = len;
  87         desc->reserved = 0;
  88         desc->addr_lo = (dma_addr_t)buf;
  89 #ifdef CONFIG_DMA_ADDR_T_64BIT
  90         desc->addr_hi = (u64)buf >> 32;
  91 #endif
  92 }
  93
  94 static void sdhci_prepare_adma_table(struct sdhci_host *host,
  95                                      struct mmc_data *data)
  96 {
  97         uint trans_bytes = data->blocksize * data->blocks;
  98         uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
  99         int i = desc_count;
 100         char *buf;
 101
 102         host->desc_slot = 0;
 103
 104         if (data->flags & MMC_DATA_READ)
 105                 buf = data->dest;
 106         else
 107                 buf = (char *)data->src;
 108
 109         while (--i) {
 110                 sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false);
 111                 buf += ADMA_MAX_LEN;
 112                 trans_bytes -= ADMA_MAX_LEN;
 113         }
 114
 115         sdhci_adma_desc(host, buf, trans_bytes, true);
 116
 117         flush_cache((dma_addr_t)host->adma_desc_table,
 118                     ROUND(desc_count * sizeof(struct sdhci_adma_desc),
 119                           ARCH_DMA_MINALIGN));
 120 }
 121 #elif defined(CONFIG_MMC_SDHCI_SDMA)
 122 static void sdhci_prepare_adma_table(struct sdhci_host *host,
 123                                      struct mmc_data *data)
 124 {}
 125 #endif
 126 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 127 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 128                               int *is_aligned, int trans_bytes)
 129 {
 130         unsigned char ctrl;
 131
 132         if (data->flags == MMC_DATA_READ)
 133                 host->start_addr = (dma_addr_t)data->dest;
 134         else
 135                 host->start_addr = (dma_addr_t)data->src;
 136
 137         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 138         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 139         if (host->flags & USE_ADMA64)
 140                 ctrl |= SDHCI_CTRL_ADMA64;
 141         else if (host->flags & USE_ADMA)
 142                 ctrl |= SDHCI_CTRL_ADMA32;
 143         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 144
 145         if (host->flags & USE_SDMA) {
 146                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 147                     (host->start_addr & 0x7) != 0x0) {
 148                         *is_aligned = 0;
 149                         host->start_addr = (unsigned long)aligned_buffer;
 150                         if (data->flags != MMC_DATA_READ)
 151                                 memcpy(aligned_buffer, data->src, trans_bytes);
 152                 }
 153
 154 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 155                 /*
 156                  * Always use this bounce-buffer when
 157                  * CONFIG_FIXED_SDHCI_ALIGNED_BUFFER is defined
 158                  */
 159                 *is_aligned = 0;
 160                 host->start_addr = (unsigned long)aligned_buffer;
 161                 if (data->flags != MMC_DATA_READ)
 162                         memcpy(aligned_buffer, data->src, trans_bytes);
 163 #endif
 164                 sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
 165
 166         } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 167                 sdhci_prepare_adma_table(host, data);
 168
 169                 sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS);
 170                 if (host->flags & USE_ADMA64)
 171                         sdhci_writel(host, (u64)host->adma_addr >> 32,
 172                                      SDHCI_ADMA_ADDRESS_HI);
 173         }
 174
 175         flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
 176 }
 177 #else
 178 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 179                               int *is_aligned, int trans_bytes)
 180 {}
 181 #endif
 182 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 183 {
 184         dma_addr_t start_addr = host->start_addr;
 185         unsigned int stat, rdy, mask, timeout, block = 0;
 186         bool transfer_done = false;
 187
 188         timeout = 1000000;
 189         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 190         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 191         do {
 192                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 193                 if (stat & SDHCI_INT_ERROR) {
 194                         pr_debug("%s: Error detected in status(0x%X)!\n",
 195                                  __func__, stat);
 196                         return -EIO;
 197                 }
 198                 if (!transfer_done && (stat & rdy)) {
 199                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 200                                 continue;
 201                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 202                         sdhci_transfer_pio(host, data);
 203                         data->dest += data->blocksize;
 204                         if (++block >= data->blocks) {
 205                                 /* Keep looping until the SDHCI_INT_DATA_END is
 206                                  * cleared, even if we finished sending all the
 207                                  * blocks.
 208                                  */
 209                                 transfer_done = true;
 210                                 continue;
 211                         }
 212                 }
 213                 if ((host->flags & USE_DMA) && !transfer_done &&
 214                     (stat & SDHCI_INT_DMA_END)) {
 215                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 216                         if (host->flags & USE_SDMA) {
 217                                 start_addr &=
 218                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 219                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 220                                 sdhci_writel(host, start_addr,
 221                                              SDHCI_DMA_ADDRESS);
 222                         }
 223                 }
 224                 if (timeout-- > 0)
 225                         udelay(10);
 226                 else {
 227                         printf("%s: Transfer data timeout\n", __func__);
 228                         return -ETIMEDOUT;
 229                 }
 230         } while (!(stat & SDHCI_INT_DATA_END));
 231         return 0;
 232 }
 233
 234 /*
 235  * No command will be sent by driver if card is busy, so driver must wait
 236  * for card ready state.
 237  * Every time when card is busy after timeout then (last) timeout value will be
 238  * increased twice but only if it doesn't exceed global defined maximum.
 239  * Each function call will use last timeout value.
 240  */
 241 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 242 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 243 #define SDHCI_READ_STATUS_TIMEOUT               1000
 244
 245 #ifdef CONFIG_DM_MMC
 246 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 247                               struct mmc_data *data)
 248 {
 249         struct mmc *mmc = mmc_get_mmc_dev(dev);
 250
 251 #else
 252 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 253                               struct mmc_data *data)
 254 {
 255 #endif
 256         struct sdhci_host *host = mmc->priv;
 257         unsigned int stat = 0;
 258         int ret = 0;
 259         int trans_bytes = 0, is_aligned = 1;
 260         u32 mask, flags, mode;
 261         unsigned int time = 0;
 262         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 263         ulong start = get_timer(0);
 264
 265         host->start_addr = 0;
 266         /* Timeout unit - ms */
 267         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 268
 269         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 270
 271         /* We shouldn't wait for data inihibit for stop commands, even
 272            though they might use busy signaling */
 273         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 274             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 275               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 276                 mask &= ~SDHCI_DATA_INHIBIT;
 277
 278         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 279                 if (time >= cmd_timeout) {
 280                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 281                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 282                                 cmd_timeout += cmd_timeout;
 283                                 printf("timeout increasing to: %u ms.\n",
 284                                        cmd_timeout);
 285                         } else {
 286                                 puts("timeout.\n");
 287                                 return -ECOMM;
 288                         }
 289                 }
 290                 time++;
 291                 udelay(1000);
 292         }
 293
 294         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 295
 296         mask = SDHCI_INT_RESPONSE;
 297         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 298              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 299                 mask = SDHCI_INT_DATA_AVAIL;
 300
 301         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 302                 flags = SDHCI_CMD_RESP_NONE;
 303         else if (cmd->resp_type & MMC_RSP_136)
 304                 flags = SDHCI_CMD_RESP_LONG;
 305         else if (cmd->resp_type & MMC_RSP_BUSY) {
 306                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 307                 if (data)
 308                         mask |= SDHCI_INT_DATA_END;
 309         } else
 310                 flags = SDHCI_CMD_RESP_SHORT;
 311
 312         if (cmd->resp_type & MMC_RSP_CRC)
 313                 flags |= SDHCI_CMD_CRC;
 314         if (cmd->resp_type & MMC_RSP_OPCODE)
 315                 flags |= SDHCI_CMD_INDEX;
 316         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 317             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 318                 flags |= SDHCI_CMD_DATA;
 319
 320         /* Set Transfer mode regarding to data flag */
 321         if (data) {
 322                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 323                 mode = SDHCI_TRNS_BLK_CNT_EN;
 324                 trans_bytes = data->blocks * data->blocksize;
 325                 if (data->blocks > 1)
 326                         mode |= SDHCI_TRNS_MULTI;
 327
 328                 if (data->flags == MMC_DATA_READ)
 329                         mode |= SDHCI_TRNS_READ;
 330
 331                 if (host->flags & USE_DMA) {
 332                         mode |= SDHCI_TRNS_DMA;
 333                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 334                 }
 335
 336                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 337                                 data->blocksize),
 338                                 SDHCI_BLOCK_SIZE);
 339                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 340                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 341         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 342                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 343         }
 344
 345         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 346         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 347         start = get_timer(0);
 348         do {
 349                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 350                 if (stat & SDHCI_INT_ERROR)
 351                         break;
 352
 353                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 354                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 355                                 return 0;
 356                         } else {
 357                                 printf("%s: Timeout for status update!\n",
 358                                        __func__);
 359                                 return -ETIMEDOUT;
 360                         }
 361                 }
 362         } while ((stat & mask) != mask);
 363
 364         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 365                 sdhci_cmd_done(host, cmd);
 366                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 367         } else
 368                 ret = -1;
 369
 370         if (!ret && data)
 371                 ret = sdhci_transfer_data(host, data);
 372
 373         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 374                 udelay(1000);
 375
 376         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 377         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 378         if (!ret) {
 379                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 380                                 !is_aligned && (data->flags == MMC_DATA_READ))
 381                         memcpy(data->dest, aligned_buffer, trans_bytes);
 382                 return 0;
 383         }
 384
 385         sdhci_reset(host, SDHCI_RESET_CMD);
 386         sdhci_reset(host, SDHCI_RESET_DATA);
 387         if (stat & SDHCI_INT_TIMEOUT)
 388                 return -ETIMEDOUT;
 389         else
 390                 return -ECOMM;
 391 }
 392
 393 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 394 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 395 {
 396         int err;
 397         struct mmc *mmc = mmc_get_mmc_dev(dev);
 398         struct sdhci_host *host = mmc->priv;
 399
 400         debug("%s\n", __func__);
 401
 402         if (host->ops && host->ops->platform_execute_tuning) {
 403                 err = host->ops->platform_execute_tuning(mmc, opcode);
 404                 if (err)
 405                         return err;
 406                 return 0;
 407         }
 408         return 0;
 409 }
 410 #endif
 411 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 412 {
 413         struct sdhci_host *host = mmc->priv;
 414         unsigned int div, clk = 0, timeout;
 415
 416         /* Wait max 20 ms */
 417         timeout = 200;
 418         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 419                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 420                 if (timeout == 0) {
 421                         printf("%s: Timeout to wait cmd & data inhibit\n",
 422                                __func__);
 423                         return -EBUSY;
 424                 }
 425
 426                 timeout--;
 427                 udelay(100);
 428         }
 429
 430         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 431
 432         if (clock == 0)
 433                 return 0;
 434
 435         if (host->ops && host->ops->set_delay)
 436                 host->ops->set_delay(host);
 437
 438         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 439                 /*
 440                  * Check if the Host Controller supports Programmable Clock
 441                  * Mode.
 442                  */
 443                 if (host->clk_mul) {
 444                         for (div = 1; div <= 1024; div++) {
 445                                 if ((host->max_clk / div) <= clock)
 446                                         break;
 447                         }
 448
 449                         /*
 450                          * Set Programmable Clock Mode in the Clock
 451                          * Control register.
 452                          */
 453                         clk = SDHCI_PROG_CLOCK_MODE;
 454                         div--;
 455                 } else {
 456                         /* Version 3.00 divisors must be a multiple of 2. */
 457                         if (host->max_clk <= clock) {
 458                                 div = 1;
 459                         } else {
 460                                 for (div = 2;
 461                                      div < SDHCI_MAX_DIV_SPEC_300;
 462                                      div += 2) {
 463                                         if ((host->max_clk / div) <= clock)
 464                                                 break;
 465                                 }
 466                         }
 467                         div >>= 1;
 468                 }
 469         } else {
 470                 /* Version 2.00 divisors must be a power of 2. */
 471                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 472                         if ((host->max_clk / div) <= clock)
 473                                 break;
 474                 }
 475                 div >>= 1;
 476         }
 477
 478         if (host->ops && host->ops->set_clock)
 479                 host->ops->set_clock(host, div);
 480
 481         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 482         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 483                 << SDHCI_DIVIDER_HI_SHIFT;
 484         clk |= SDHCI_CLOCK_INT_EN;
 485         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 486
 487         /* Wait max 20 ms */
 488         timeout = 20;
 489         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 490                 & SDHCI_CLOCK_INT_STABLE)) {
 491                 if (timeout == 0) {
 492                         printf("%s: Internal clock never stabilised.\n",
 493                                __func__);
 494                         return -EBUSY;
 495                 }
 496                 timeout--;
 497                 udelay(1000);
 498         }
 499
 500         clk |= SDHCI_CLOCK_CARD_EN;
 501         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 502         return 0;
 503 }
 504
 505 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 506 {
 507         u8 pwr = 0;
 508
 509         if (power != (unsigned short)-1) {
 510                 switch (1 << power) {
 511                 case MMC_VDD_165_195:
 512                         pwr = SDHCI_POWER_180;
 513                         break;
 514                 case MMC_VDD_29_30:
 515                 case MMC_VDD_30_31:
 516                         pwr = SDHCI_POWER_300;
 517                         break;
 518                 case MMC_VDD_32_33:
 519                 case MMC_VDD_33_34:
 520                         pwr = SDHCI_POWER_330;
 521                         break;
 522                 }
 523         }
 524
 525         if (pwr == 0) {
 526                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 527                 return;
 528         }
 529
 530         pwr |= SDHCI_POWER_ON;
 531
 532         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 533 }
 534
 535 #ifdef CONFIG_DM_MMC
 536 static int sdhci_set_ios(struct udevice *dev)
 537 {
 538         struct mmc *mmc = mmc_get_mmc_dev(dev);
 539 #else
 540 static int sdhci_set_ios(struct mmc *mmc)
 541 {
 542 #endif
 543         u32 ctrl;
 544         struct sdhci_host *host = mmc->priv;
 545
 546         if (host->ops && host->ops->set_control_reg)
 547                 host->ops->set_control_reg(host);
 548
 549         if (mmc->clock != host->clock)
 550                 sdhci_set_clock(mmc, mmc->clock);
 551
 552         if (mmc->clk_disable)
 553                 sdhci_set_clock(mmc, 0);
 554
 555         /* Set bus width */
 556         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 557         if (mmc->bus_width == 8) {
 558                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 559                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 560                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 561                         ctrl |= SDHCI_CTRL_8BITBUS;
 562         } else {
 563                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 564                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 565                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 566                 if (mmc->bus_width == 4)
 567                         ctrl |= SDHCI_CTRL_4BITBUS;
 568                 else
 569                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 570         }
 571
 572         if (mmc->clock > 26000000)
 573                 ctrl |= SDHCI_CTRL_HISPD;
 574         else
 575                 ctrl &= ~SDHCI_CTRL_HISPD;
 576
 577         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 578             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 579                 ctrl &= ~SDHCI_CTRL_HISPD;
 580
 581         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 582
 583         /* If available, call the driver specific "post" set_ios() function */
 584         if (host->ops && host->ops->set_ios_post)
 585                 host->ops->set_ios_post(host);
 586
 587         return 0;
 588 }
 589
 590 static int sdhci_init(struct mmc *mmc)
 591 {
 592         struct sdhci_host *host = mmc->priv;
 593
 594         sdhci_reset(host, SDHCI_RESET_ALL);
 595
 596         if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
 597                 aligned_buffer = memalign(8, 512*1024);
 598                 if (!aligned_buffer) {
 599                         printf("%s: Aligned buffer alloc failed!!!\n",
 600                                __func__);
 601                         return -ENOMEM;
 602                 }
 603         }
 604
 605         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 606
 607         if (host->ops && host->ops->get_cd)
 608                 host->ops->get_cd(host);
 609
 610         /* Enable only interrupts served by the SD controller */
 611         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 612                      SDHCI_INT_ENABLE);
 613         /* Mask all sdhci interrupt sources */
 614         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 615
 616         return 0;
 617 }
 618
 619 #ifdef CONFIG_DM_MMC
 620 int sdhci_probe(struct udevice *dev)
 621 {
 622         struct mmc *mmc = mmc_get_mmc_dev(dev);
 623
 624         return sdhci_init(mmc);
 625 }
 626
 627 const struct dm_mmc_ops sdhci_ops = {
 628         .send_cmd       = sdhci_send_command,
 629         .set_ios        = sdhci_set_ios,
 630 #ifdef MMC_SUPPORTS_TUNING
 631         .execute_tuning = sdhci_execute_tuning,
 632 #endif
 633 };
 634 #else
 635 static const struct mmc_ops sdhci_ops = {
 636         .send_cmd       = sdhci_send_command,
 637         .set_ios        = sdhci_set_ios,
 638         .init           = sdhci_init,
 639 };
 640 #endif
 641
 642 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 643                 u32 f_max, u32 f_min)
 644 {
 645         u32 caps, caps_1 = 0;
 646
 647         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 648
 649 #ifdef CONFIG_MMC_SDHCI_SDMA
 650         if (!(caps & SDHCI_CAN_DO_SDMA)) {
 651                 printf("%s: Your controller doesn't support SDMA!!\n",
 652                        __func__);
 653                 return -EINVAL;
 654         }
 655
 656         host->flags |= USE_SDMA;
 657 #endif
 658 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 659         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 660                 printf("%s: Your controller doesn't support SDMA!!\n",
 661                        __func__);
 662                 return -EINVAL;
 663         }
 664         host->adma_desc_table = (struct sdhci_adma_desc *)
 665                                 memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
 666
 667         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 668 #ifdef CONFIG_DMA_ADDR_T_64BIT
 669         host->flags |= USE_ADMA64;
 670 #else
 671         host->flags |= USE_ADMA;
 672 #endif
 673 #endif
 674         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 675                 host->version =
 676                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 677         else
 678                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 679
 680         cfg->name = host->name;
 681 #ifndef CONFIG_DM_MMC
 682         cfg->ops = &sdhci_ops;
 683 #endif
 684
 685         /* Check whether the clock multiplier is supported or not */
 686         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 687                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 688                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 689                                 SDHCI_CLOCK_MUL_SHIFT;
 690         }
 691
 692         if (host->max_clk == 0) {
 693                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 694                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 695                                 SDHCI_CLOCK_BASE_SHIFT;
 696                 else
 697                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 698                                 SDHCI_CLOCK_BASE_SHIFT;
 699                 host->max_clk *= 1000000;
 700                 if (host->clk_mul)
 701                         host->max_clk *= host->clk_mul;
 702         }
 703         if (host->max_clk == 0) {
 704                 printf("%s: Hardware doesn't specify base clock frequency\n",
 705                        __func__);
 706                 return -EINVAL;
 707         }
 708         if (f_max && (f_max < host->max_clk))
 709                 cfg->f_max = f_max;
 710         else
 711                 cfg->f_max = host->max_clk;
 712         if (f_min)
 713                 cfg->f_min = f_min;
 714         else {
 715                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 716                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 717                 else
 718                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 719         }
 720         cfg->voltages = 0;
 721         if (caps & SDHCI_CAN_VDD_330)
 722                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 723         if (caps & SDHCI_CAN_VDD_300)
 724                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 725         if (caps & SDHCI_CAN_VDD_180)
 726                 cfg->voltages |= MMC_VDD_165_195;
 727
 728         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 729                 cfg->voltages |= host->voltages;
 730
 731         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 732
 733         /* Since Host Controller Version3.0 */
 734         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 735                 if (!(caps & SDHCI_CAN_DO_8BIT))
 736                         cfg->host_caps &= ~MMC_MODE_8BIT;
 737         }
 738
 739         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 740                 cfg->host_caps &= ~MMC_MODE_HS;
 741                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 742         }
 743
 744         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 745                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 746
 747         if (!(cfg->voltages & MMC_VDD_165_195) ||
 748             (host->quirks & SDHCI_QUIRK_NO_1_8_V))
 749                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 750                             SDHCI_SUPPORT_DDR50);
 751
 752         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 753                       SDHCI_SUPPORT_DDR50))
 754                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 755
 756         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 757                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 758                 /*
 759                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 760                  * field can be promoted to support HS200.
 761                  */
 762                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 763         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 764                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 765         }
 766
 767         if (caps_1 & SDHCI_SUPPORT_DDR50)
 768                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 769
 770         if (host->host_caps)
 771                 cfg->host_caps |= host->host_caps;
 772
 773         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 774
 775         return 0;
 776 }
 777
 778 #ifdef CONFIG_BLK
 779 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 780 {
 781         return mmc_bind(dev, mmc, cfg);
 782 }
 783 #else
 784 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 785 {
 786         int ret;
 787
 788         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 789         if (ret)
 790                 return ret;
 791
 792         host->mmc = mmc_create(&host->cfg, host);
 793         if (host->mmc == NULL) {
 794                 printf("%s: mmc create fail!\n", __func__);
 795                 return -ENOMEM;
 796         }
 797
 798         return 0;
 799 }
 800 #endif