2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
5 * SPDX-License-Identifier: GPL-2.0+
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
18 static void sdhci_reset(struct sdhci_host *host, u8 mask)
20 unsigned long timeout;
24 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
25 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
27 printf("Reset 0x%x never completed.\n", (int)mask);
35 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
38 if (cmd->resp_type & MMC_RSP_136) {
39 /* CRC is stripped so we need to do some shifting. */
40 for (i = 0; i < 4; i++) {
41 cmd->response[i] = sdhci_readl(host,
42 SDHCI_RESPONSE + (3-i)*4) << 8;
44 cmd->response[i] |= sdhci_readb(host,
45 SDHCI_RESPONSE + (3-i)*4-1);
48 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
52 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
56 for (i = 0; i < data->blocksize; i += 4) {
57 offs = data->dest + i;
58 if (data->flags == MMC_DATA_READ)
59 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
61 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
65 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
66 unsigned int start_addr)
68 unsigned int stat, rdy, mask, timeout, block = 0;
69 #ifdef CONFIG_MMC_SDMA
71 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
72 ctrl &= ~SDHCI_CTRL_DMA_MASK;
73 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
77 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
78 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
80 stat = sdhci_readl(host, SDHCI_INT_STATUS);
81 if (stat & SDHCI_INT_ERROR) {
82 printf("Error detected in status(0x%X)!\n", stat);
86 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
88 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
89 sdhci_transfer_pio(host, data);
90 data->dest += data->blocksize;
91 if (++block >= data->blocks)
94 #ifdef CONFIG_MMC_SDMA
95 if (stat & SDHCI_INT_DMA_END) {
96 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
97 start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
98 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
99 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
105 printf("Transfer data timeout\n");
108 } while (!(stat & SDHCI_INT_DATA_END));
112 int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
113 struct mmc_data *data)
115 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
116 unsigned int stat = 0;
118 int trans_bytes = 0, is_aligned = 1;
119 u32 mask, flags, mode;
120 unsigned int timeout, start_addr = 0;
121 unsigned int retry = 10000;
126 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
127 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
129 /* We shouldn't wait for data inihibit for stop commands, even
130 though they might use busy signaling */
131 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
132 mask &= ~SDHCI_DATA_INHIBIT;
134 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
136 printf("Controller never released inhibit bit(s).\n");
143 mask = SDHCI_INT_RESPONSE;
144 if (!(cmd->resp_type & MMC_RSP_PRESENT))
145 flags = SDHCI_CMD_RESP_NONE;
146 else if (cmd->resp_type & MMC_RSP_136)
147 flags = SDHCI_CMD_RESP_LONG;
148 else if (cmd->resp_type & MMC_RSP_BUSY) {
149 flags = SDHCI_CMD_RESP_SHORT_BUSY;
150 mask |= SDHCI_INT_DATA_END;
152 flags = SDHCI_CMD_RESP_SHORT;
154 if (cmd->resp_type & MMC_RSP_CRC)
155 flags |= SDHCI_CMD_CRC;
156 if (cmd->resp_type & MMC_RSP_OPCODE)
157 flags |= SDHCI_CMD_INDEX;
159 flags |= SDHCI_CMD_DATA;
161 /*Set Transfer mode regarding to data flag*/
163 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
164 mode = SDHCI_TRNS_BLK_CNT_EN;
165 trans_bytes = data->blocks * data->blocksize;
166 if (data->blocks > 1)
167 mode |= SDHCI_TRNS_MULTI;
169 if (data->flags == MMC_DATA_READ)
170 mode |= SDHCI_TRNS_READ;
172 #ifdef CONFIG_MMC_SDMA
173 if (data->flags == MMC_DATA_READ)
174 start_addr = (unsigned int)data->dest;
176 start_addr = (unsigned int)data->src;
177 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
178 (start_addr & 0x7) != 0x0) {
180 start_addr = (unsigned int)aligned_buffer;
181 if (data->flags != MMC_DATA_READ)
182 memcpy(aligned_buffer, data->src, trans_bytes);
185 sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
186 mode |= SDHCI_TRNS_DMA;
188 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
191 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
192 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
195 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
196 #ifdef CONFIG_MMC_SDMA
197 flush_cache(start_addr, trans_bytes);
199 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
201 stat = sdhci_readl(host, SDHCI_INT_STATUS);
202 if (stat & SDHCI_INT_ERROR)
206 } while ((stat & mask) != mask);
209 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B)
212 printf("Timeout for status update!\n");
217 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
218 sdhci_cmd_done(host, cmd);
219 sdhci_writel(host, mask, SDHCI_INT_STATUS);
224 ret = sdhci_transfer_data(host, data, start_addr);
226 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
229 stat = sdhci_readl(host, SDHCI_INT_STATUS);
230 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
232 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
233 !is_aligned && (data->flags == MMC_DATA_READ))
234 memcpy(data->dest, aligned_buffer, trans_bytes);
238 sdhci_reset(host, SDHCI_RESET_CMD);
239 sdhci_reset(host, SDHCI_RESET_DATA);
240 if (stat & SDHCI_INT_TIMEOUT)
246 static int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
248 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
249 unsigned int div, clk, timeout;
251 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
256 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
257 /* Version 3.00 divisors must be a multiple of 2. */
258 if (mmc->f_max <= clock)
261 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
262 if ((mmc->f_max / div) <= clock)
267 /* Version 2.00 divisors must be a power of 2. */
268 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
269 if ((mmc->f_max / div) <= clock)
276 host->set_clock(host->index, div);
278 clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
279 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
280 << SDHCI_DIVIDER_HI_SHIFT;
281 clk |= SDHCI_CLOCK_INT_EN;
282 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
286 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
287 & SDHCI_CLOCK_INT_STABLE)) {
289 printf("Internal clock never stabilised.\n");
296 clk |= SDHCI_CLOCK_CARD_EN;
297 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
301 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
305 if (power != (unsigned short)-1) {
306 switch (1 << power) {
307 case MMC_VDD_165_195:
308 pwr = SDHCI_POWER_180;
312 pwr = SDHCI_POWER_300;
316 pwr = SDHCI_POWER_330;
322 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
326 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
327 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
329 pwr |= SDHCI_POWER_ON;
331 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
334 void sdhci_set_ios(struct mmc *mmc)
337 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
339 if (host->set_control_reg)
340 host->set_control_reg(host);
342 if (mmc->clock != host->clock)
343 sdhci_set_clock(mmc, mmc->clock);
346 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
347 if (mmc->bus_width == 8) {
348 ctrl &= ~SDHCI_CTRL_4BITBUS;
349 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
350 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
351 ctrl |= SDHCI_CTRL_8BITBUS;
353 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
354 ctrl &= ~SDHCI_CTRL_8BITBUS;
355 if (mmc->bus_width == 4)
356 ctrl |= SDHCI_CTRL_4BITBUS;
358 ctrl &= ~SDHCI_CTRL_4BITBUS;
361 if (mmc->clock > 26000000)
362 ctrl |= SDHCI_CTRL_HISPD;
364 ctrl &= ~SDHCI_CTRL_HISPD;
366 if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
367 ctrl &= ~SDHCI_CTRL_HISPD;
369 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
372 int sdhci_init(struct mmc *mmc)
374 struct sdhci_host *host = (struct sdhci_host *)mmc->priv;
376 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) && !aligned_buffer) {
377 aligned_buffer = memalign(8, 512*1024);
378 if (!aligned_buffer) {
379 printf("Aligned buffer alloc failed!!!");
384 sdhci_set_power(host, fls(mmc->voltages) - 1);
386 if (host->quirks & SDHCI_QUIRK_NO_CD) {
389 sdhci_writel(host, SDHCI_CTRL_CD_TEST_INS | SDHCI_CTRL_CD_TEST,
392 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
393 while ((!(status & SDHCI_CARD_PRESENT)) ||
394 (!(status & SDHCI_CARD_STATE_STABLE)) ||
395 (!(status & SDHCI_CARD_DETECT_PIN_LEVEL)))
396 status = sdhci_readl(host, SDHCI_PRESENT_STATE);
399 /* Enable only interrupts served by the SD controller */
400 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK
402 /* Mask all sdhci interrupt sources */
403 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
408 int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
413 mmc = malloc(sizeof(struct mmc));
415 printf("mmc malloc fail!\n");
422 sprintf(mmc->name, "%s", host->name);
423 mmc->send_cmd = sdhci_send_command;
424 mmc->set_ios = sdhci_set_ios;
425 mmc->init = sdhci_init;
429 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
430 #ifdef CONFIG_MMC_SDMA
431 if (!(caps & SDHCI_CAN_DO_SDMA)) {
432 printf("Your controller don't support sdma!!\n");
438 mmc->f_max = max_clk;
440 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
441 mmc->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK)
442 >> SDHCI_CLOCK_BASE_SHIFT;
444 mmc->f_max = (caps & SDHCI_CLOCK_BASE_MASK)
445 >> SDHCI_CLOCK_BASE_SHIFT;
446 mmc->f_max *= 1000000;
448 if (mmc->f_max == 0) {
449 printf("Hardware doesn't specify base clock frequency\n");
453 mmc->f_min = min_clk;
455 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
456 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_300;
458 mmc->f_min = mmc->f_max / SDHCI_MAX_DIV_SPEC_200;
462 if (caps & SDHCI_CAN_VDD_330)
463 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
464 if (caps & SDHCI_CAN_VDD_300)
465 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
466 if (caps & SDHCI_CAN_VDD_180)
467 mmc->voltages |= MMC_VDD_165_195;
469 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
470 mmc->voltages |= host->voltages;
472 mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
473 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
474 if (caps & SDHCI_CAN_DO_8BIT)
475 mmc->host_caps |= MMC_MODE_8BIT;
478 mmc->host_caps |= host->host_caps;
480 sdhci_reset(host, SDHCI_RESET_ALL);