1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
19 static void sdhci_reset(struct sdhci_host *host, u8 mask)
21 unsigned long timeout;
25 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
26 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
28 printf("%s: Reset 0x%x never completed.\n",
37 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
40 if (cmd->resp_type & MMC_RSP_136) {
41 /* CRC is stripped so we need to do some shifting. */
42 for (i = 0; i < 4; i++) {
43 cmd->response[i] = sdhci_readl(host,
44 SDHCI_RESPONSE + (3-i)*4) << 8;
46 cmd->response[i] |= sdhci_readb(host,
47 SDHCI_RESPONSE + (3-i)*4-1);
50 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
54 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
58 for (i = 0; i < data->blocksize; i += 4) {
59 offs = data->dest + i;
60 if (data->flags == MMC_DATA_READ)
61 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
63 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
67 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
68 static void sdhci_adma_desc(struct sdhci_host *host, char *buf, u16 len,
71 struct sdhci_adma_desc *desc;
74 desc = &host->adma_desc_table[host->desc_slot];
76 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
80 attr |= ADMA_DESC_ATTR_END;
85 desc->addr_lo = (dma_addr_t)buf;
86 #ifdef CONFIG_DMA_ADDR_T_64BIT
87 desc->addr_hi = (u64)buf >> 32;
91 static void sdhci_prepare_adma_table(struct sdhci_host *host,
92 struct mmc_data *data)
94 uint trans_bytes = data->blocksize * data->blocks;
95 uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
101 if (data->flags & MMC_DATA_READ)
104 buf = (char *)data->src;
107 sdhci_adma_desc(host, buf, ADMA_MAX_LEN, false);
109 trans_bytes -= ADMA_MAX_LEN;
112 sdhci_adma_desc(host, buf, trans_bytes, true);
114 flush_cache((dma_addr_t)host->adma_desc_table,
115 ROUND(desc_count * sizeof(struct sdhci_adma_desc),
118 #elif defined(CONFIG_MMC_SDHCI_SDMA)
119 static void sdhci_prepare_adma_table(struct sdhci_host *host,
120 struct mmc_data *data)
123 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
124 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
125 int *is_aligned, int trans_bytes)
129 if (data->flags == MMC_DATA_READ)
130 host->start_addr = (dma_addr_t)data->dest;
132 host->start_addr = (dma_addr_t)data->src;
134 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
135 ctrl &= ~SDHCI_CTRL_DMA_MASK;
136 if (host->flags & USE_ADMA64)
137 ctrl |= SDHCI_CTRL_ADMA64;
138 else if (host->flags & USE_ADMA)
139 ctrl |= SDHCI_CTRL_ADMA32;
140 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
142 if (host->flags & USE_SDMA) {
143 if (host->force_align_buffer ||
144 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
145 (host->start_addr & 0x7) != 0x0)) {
147 host->start_addr = (unsigned long)host->align_buffer;
148 if (data->flags != MMC_DATA_READ)
149 memcpy(host->align_buffer, data->src,
152 sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
153 } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
154 sdhci_prepare_adma_table(host, data);
156 sdhci_writel(host, (u32)host->adma_addr, SDHCI_ADMA_ADDRESS);
157 if (host->flags & USE_ADMA64)
158 sdhci_writel(host, (u64)host->adma_addr >> 32,
159 SDHCI_ADMA_ADDRESS_HI);
162 flush_cache(host->start_addr, ROUND(trans_bytes, ARCH_DMA_MINALIGN));
165 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
166 int *is_aligned, int trans_bytes)
169 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
171 dma_addr_t start_addr = host->start_addr;
172 unsigned int stat, rdy, mask, timeout, block = 0;
173 bool transfer_done = false;
176 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
177 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
179 stat = sdhci_readl(host, SDHCI_INT_STATUS);
180 if (stat & SDHCI_INT_ERROR) {
181 pr_debug("%s: Error detected in status(0x%X)!\n",
185 if (!transfer_done && (stat & rdy)) {
186 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
188 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
189 sdhci_transfer_pio(host, data);
190 data->dest += data->blocksize;
191 if (++block >= data->blocks) {
192 /* Keep looping until the SDHCI_INT_DATA_END is
193 * cleared, even if we finished sending all the
196 transfer_done = true;
200 if ((host->flags & USE_DMA) && !transfer_done &&
201 (stat & SDHCI_INT_DMA_END)) {
202 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
203 if (host->flags & USE_SDMA) {
205 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
206 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
207 sdhci_writel(host, start_addr,
214 printf("%s: Transfer data timeout\n", __func__);
217 } while (!(stat & SDHCI_INT_DATA_END));
222 * No command will be sent by driver if card is busy, so driver must wait
223 * for card ready state.
224 * Every time when card is busy after timeout then (last) timeout value will be
225 * increased twice but only if it doesn't exceed global defined maximum.
226 * Each function call will use last timeout value.
228 #define SDHCI_CMD_MAX_TIMEOUT 3200
229 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
230 #define SDHCI_READ_STATUS_TIMEOUT 1000
233 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
234 struct mmc_data *data)
236 struct mmc *mmc = mmc_get_mmc_dev(dev);
239 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
240 struct mmc_data *data)
243 struct sdhci_host *host = mmc->priv;
244 unsigned int stat = 0;
246 int trans_bytes = 0, is_aligned = 1;
247 u32 mask, flags, mode;
248 unsigned int time = 0;
249 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
250 ulong start = get_timer(0);
252 host->start_addr = 0;
253 /* Timeout unit - ms */
254 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
256 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
258 /* We shouldn't wait for data inihibit for stop commands, even
259 though they might use busy signaling */
260 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
261 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
262 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
263 mask &= ~SDHCI_DATA_INHIBIT;
265 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
266 if (time >= cmd_timeout) {
267 printf("%s: MMC: %d busy ", __func__, mmc_dev);
268 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
269 cmd_timeout += cmd_timeout;
270 printf("timeout increasing to: %u ms.\n",
281 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
283 mask = SDHCI_INT_RESPONSE;
284 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
285 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
286 mask = SDHCI_INT_DATA_AVAIL;
288 if (!(cmd->resp_type & MMC_RSP_PRESENT))
289 flags = SDHCI_CMD_RESP_NONE;
290 else if (cmd->resp_type & MMC_RSP_136)
291 flags = SDHCI_CMD_RESP_LONG;
292 else if (cmd->resp_type & MMC_RSP_BUSY) {
293 flags = SDHCI_CMD_RESP_SHORT_BUSY;
295 mask |= SDHCI_INT_DATA_END;
297 flags = SDHCI_CMD_RESP_SHORT;
299 if (cmd->resp_type & MMC_RSP_CRC)
300 flags |= SDHCI_CMD_CRC;
301 if (cmd->resp_type & MMC_RSP_OPCODE)
302 flags |= SDHCI_CMD_INDEX;
303 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
304 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
305 flags |= SDHCI_CMD_DATA;
307 /* Set Transfer mode regarding to data flag */
309 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
310 mode = SDHCI_TRNS_BLK_CNT_EN;
311 trans_bytes = data->blocks * data->blocksize;
312 if (data->blocks > 1)
313 mode |= SDHCI_TRNS_MULTI;
315 if (data->flags == MMC_DATA_READ)
316 mode |= SDHCI_TRNS_READ;
318 if (host->flags & USE_DMA) {
319 mode |= SDHCI_TRNS_DMA;
320 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
323 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
326 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
327 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
328 } else if (cmd->resp_type & MMC_RSP_BUSY) {
329 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
332 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
333 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
334 start = get_timer(0);
336 stat = sdhci_readl(host, SDHCI_INT_STATUS);
337 if (stat & SDHCI_INT_ERROR)
340 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
341 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
344 printf("%s: Timeout for status update!\n",
349 } while ((stat & mask) != mask);
351 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
352 sdhci_cmd_done(host, cmd);
353 sdhci_writel(host, mask, SDHCI_INT_STATUS);
358 ret = sdhci_transfer_data(host, data);
360 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
363 stat = sdhci_readl(host, SDHCI_INT_STATUS);
364 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
366 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
367 !is_aligned && (data->flags == MMC_DATA_READ))
368 memcpy(data->dest, host->align_buffer, trans_bytes);
372 sdhci_reset(host, SDHCI_RESET_CMD);
373 sdhci_reset(host, SDHCI_RESET_DATA);
374 if (stat & SDHCI_INT_TIMEOUT)
380 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
381 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
384 struct mmc *mmc = mmc_get_mmc_dev(dev);
385 struct sdhci_host *host = mmc->priv;
387 debug("%s\n", __func__);
389 if (host->ops && host->ops->platform_execute_tuning) {
390 err = host->ops->platform_execute_tuning(mmc, opcode);
398 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
400 struct sdhci_host *host = mmc->priv;
401 unsigned int div, clk = 0, timeout;
405 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
406 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
408 printf("%s: Timeout to wait cmd & data inhibit\n",
417 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
422 if (host->ops && host->ops->set_delay)
423 host->ops->set_delay(host);
425 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
427 * Check if the Host Controller supports Programmable Clock
431 for (div = 1; div <= 1024; div++) {
432 if ((host->max_clk / div) <= clock)
437 * Set Programmable Clock Mode in the Clock
440 clk = SDHCI_PROG_CLOCK_MODE;
443 /* Version 3.00 divisors must be a multiple of 2. */
444 if (host->max_clk <= clock) {
448 div < SDHCI_MAX_DIV_SPEC_300;
450 if ((host->max_clk / div) <= clock)
457 /* Version 2.00 divisors must be a power of 2. */
458 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
459 if ((host->max_clk / div) <= clock)
465 if (host->ops && host->ops->set_clock)
466 host->ops->set_clock(host, div);
468 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
469 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
470 << SDHCI_DIVIDER_HI_SHIFT;
471 clk |= SDHCI_CLOCK_INT_EN;
472 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
476 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
477 & SDHCI_CLOCK_INT_STABLE)) {
479 printf("%s: Internal clock never stabilised.\n",
487 clk |= SDHCI_CLOCK_CARD_EN;
488 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
492 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
496 if (power != (unsigned short)-1) {
497 switch (1 << power) {
498 case MMC_VDD_165_195:
499 pwr = SDHCI_POWER_180;
503 pwr = SDHCI_POWER_300;
507 pwr = SDHCI_POWER_330;
513 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
517 pwr |= SDHCI_POWER_ON;
519 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
522 void sdhci_set_uhs_timing(struct sdhci_host *host)
524 struct mmc *mmc = (struct mmc *)host->mmc;
527 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
528 reg &= ~SDHCI_CTRL_UHS_MASK;
530 switch (mmc->selected_mode) {
533 reg |= SDHCI_CTRL_UHS_SDR50;
537 reg |= SDHCI_CTRL_UHS_DDR50;
541 reg |= SDHCI_CTRL_UHS_SDR104;
544 reg |= SDHCI_CTRL_UHS_SDR12;
547 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
551 static int sdhci_set_ios(struct udevice *dev)
553 struct mmc *mmc = mmc_get_mmc_dev(dev);
555 static int sdhci_set_ios(struct mmc *mmc)
559 struct sdhci_host *host = mmc->priv;
561 if (host->ops && host->ops->set_control_reg)
562 host->ops->set_control_reg(host);
564 if (mmc->clock != host->clock)
565 sdhci_set_clock(mmc, mmc->clock);
567 if (mmc->clk_disable)
568 sdhci_set_clock(mmc, 0);
571 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
572 if (mmc->bus_width == 8) {
573 ctrl &= ~SDHCI_CTRL_4BITBUS;
574 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
575 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
576 ctrl |= SDHCI_CTRL_8BITBUS;
578 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
579 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
580 ctrl &= ~SDHCI_CTRL_8BITBUS;
581 if (mmc->bus_width == 4)
582 ctrl |= SDHCI_CTRL_4BITBUS;
584 ctrl &= ~SDHCI_CTRL_4BITBUS;
587 if (mmc->clock > 26000000)
588 ctrl |= SDHCI_CTRL_HISPD;
590 ctrl &= ~SDHCI_CTRL_HISPD;
592 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
593 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
594 ctrl &= ~SDHCI_CTRL_HISPD;
596 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
598 /* If available, call the driver specific "post" set_ios() function */
599 if (host->ops && host->ops->set_ios_post)
600 return host->ops->set_ios_post(host);
605 static int sdhci_init(struct mmc *mmc)
607 struct sdhci_host *host = mmc->priv;
608 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
609 struct udevice *dev = mmc->dev;
611 gpio_request_by_name(dev, "cd-gpios", 0,
612 &host->cd_gpio, GPIOD_IS_IN);
615 sdhci_reset(host, SDHCI_RESET_ALL);
617 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
618 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
620 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
623 host->force_align_buffer = true;
625 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
626 host->align_buffer = memalign(8, 512 * 1024);
627 if (!host->align_buffer) {
628 printf("%s: Aligned buffer alloc failed!!!\n",
635 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
637 if (host->ops && host->ops->get_cd)
638 host->ops->get_cd(host);
640 /* Enable only interrupts served by the SD controller */
641 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
643 /* Mask all sdhci interrupt sources */
644 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
650 int sdhci_probe(struct udevice *dev)
652 struct mmc *mmc = mmc_get_mmc_dev(dev);
654 return sdhci_init(mmc);
657 static int sdhci_get_cd(struct udevice *dev)
659 struct mmc *mmc = mmc_get_mmc_dev(dev);
660 struct sdhci_host *host = mmc->priv;
663 /* If nonremovable, assume that the card is always present. */
664 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
666 /* If polling, assume that the card is always present. */
667 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
670 #if CONFIG_IS_ENABLED(DM_GPIO)
671 value = dm_gpio_get_value(&host->cd_gpio);
673 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
679 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
681 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
687 const struct dm_mmc_ops sdhci_ops = {
688 .send_cmd = sdhci_send_command,
689 .set_ios = sdhci_set_ios,
690 .get_cd = sdhci_get_cd,
691 #ifdef MMC_SUPPORTS_TUNING
692 .execute_tuning = sdhci_execute_tuning,
696 static const struct mmc_ops sdhci_ops = {
697 .send_cmd = sdhci_send_command,
698 .set_ios = sdhci_set_ios,
703 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
704 u32 f_max, u32 f_min)
706 u32 caps, caps_1 = 0;
707 #if CONFIG_IS_ENABLED(DM_MMC)
708 u64 dt_caps, dt_caps_mask;
710 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
711 "sdhci-caps-mask", 0);
712 dt_caps = dev_read_u64_default(host->mmc->dev,
714 caps = ~(u32)dt_caps_mask &
715 sdhci_readl(host, SDHCI_CAPABILITIES);
716 caps |= (u32)dt_caps;
718 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
720 debug("%s, caps: 0x%x\n", __func__, caps);
722 #ifdef CONFIG_MMC_SDHCI_SDMA
723 if (!(caps & SDHCI_CAN_DO_SDMA)) {
724 printf("%s: Your controller doesn't support SDMA!!\n",
729 host->flags |= USE_SDMA;
731 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
732 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
733 printf("%s: Your controller doesn't support SDMA!!\n",
737 host->adma_desc_table = (struct sdhci_adma_desc *)
738 memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
740 host->adma_addr = (dma_addr_t)host->adma_desc_table;
741 #ifdef CONFIG_DMA_ADDR_T_64BIT
742 host->flags |= USE_ADMA64;
744 host->flags |= USE_ADMA;
747 if (host->quirks & SDHCI_QUIRK_REG32_RW)
749 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
751 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
753 cfg->name = host->name;
754 #ifndef CONFIG_DM_MMC
755 cfg->ops = &sdhci_ops;
758 /* Check whether the clock multiplier is supported or not */
759 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
760 #if CONFIG_IS_ENABLED(DM_MMC)
761 caps_1 = ~(u32)(dt_caps_mask >> 32) &
762 sdhci_readl(host, SDHCI_CAPABILITIES_1);
763 caps_1 |= (u32)(dt_caps >> 32);
765 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
767 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
768 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
769 SDHCI_CLOCK_MUL_SHIFT;
772 if (host->max_clk == 0) {
773 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
774 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
775 SDHCI_CLOCK_BASE_SHIFT;
777 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
778 SDHCI_CLOCK_BASE_SHIFT;
779 host->max_clk *= 1000000;
781 host->max_clk *= host->clk_mul;
783 if (host->max_clk == 0) {
784 printf("%s: Hardware doesn't specify base clock frequency\n",
788 if (f_max && (f_max < host->max_clk))
791 cfg->f_max = host->max_clk;
795 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
796 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
798 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
801 if (caps & SDHCI_CAN_VDD_330)
802 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
803 if (caps & SDHCI_CAN_VDD_300)
804 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
805 if (caps & SDHCI_CAN_VDD_180)
806 cfg->voltages |= MMC_VDD_165_195;
808 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
809 cfg->voltages |= host->voltages;
811 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
813 /* Since Host Controller Version3.0 */
814 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
815 if (!(caps & SDHCI_CAN_DO_8BIT))
816 cfg->host_caps &= ~MMC_MODE_8BIT;
819 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
820 cfg->host_caps &= ~MMC_MODE_HS;
821 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
824 if (!(cfg->voltages & MMC_VDD_165_195) ||
825 (host->quirks & SDHCI_QUIRK_NO_1_8_V))
826 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
827 SDHCI_SUPPORT_DDR50);
829 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
830 SDHCI_SUPPORT_DDR50))
831 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
833 if (caps_1 & SDHCI_SUPPORT_SDR104) {
834 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
836 * SD3.0: SDR104 is supported so (for eMMC) the caps2
837 * field can be promoted to support HS200.
839 cfg->host_caps |= MMC_CAP(MMC_HS_200);
840 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
841 cfg->host_caps |= MMC_CAP(UHS_SDR50);
844 if (caps_1 & SDHCI_SUPPORT_DDR50)
845 cfg->host_caps |= MMC_CAP(UHS_DDR50);
848 cfg->host_caps |= host->host_caps;
850 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
856 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
858 return mmc_bind(dev, mmc, cfg);
861 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
865 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
869 host->mmc = mmc_create(&host->cfg, host);
870 if (host->mmc == NULL) {
871 printf("%s: mmc create fail!\n", __func__);