drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <log.h>
  15 #include <malloc.h>
  16 #include <mmc.h>
  17 #include <sdhci.h>
  18 #include <dm.h>
  19 #include <asm/cache.h>
  20 #include <linux/bitops.h>
  21 #include <linux/delay.h>
  22 #include <linux/dma-mapping.h>
  23 #include <phys2bus.h>
  24
  25 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  26 {
  27         unsigned long timeout;
  28
  29         /* Wait max 100 ms */
  30         timeout = 100;
  31         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  32         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  33                 if (timeout == 0) {
  34                         printf("%s: Reset 0x%x never completed.\n",
  35                                __func__, (int)mask);
  36                         return;
  37                 }
  38                 timeout--;
  39                 udelay(1000);
  40         }
  41 }
  42
  43 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  44 {
  45         int i;
  46         if (cmd->resp_type & MMC_RSP_136) {
  47                 /* CRC is stripped so we need to do some shifting. */
  48                 for (i = 0; i < 4; i++) {
  49                         cmd->response[i] = sdhci_readl(host,
  50                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  51                         if (i != 3)
  52                                 cmd->response[i] |= sdhci_readb(host,
  53                                                 SDHCI_RESPONSE + (3-i)*4-1);
  54                 }
  55         } else {
  56                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  57         }
  58 }
  59
  60 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  61 {
  62         int i;
  63         char *offs;
  64         for (i = 0; i < data->blocksize; i += 4) {
  65                 offs = data->dest + i;
  66                 if (data->flags == MMC_DATA_READ)
  67                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  68                 else
  69                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  70         }
  71 }
  72
  73 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  74 static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
  75                             u16 len, bool end)
  76 {
  77         struct sdhci_adma_desc *desc;
  78         u8 attr;
  79
  80         desc = &host->adma_desc_table[host->desc_slot];
  81
  82         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  83         if (!end)
  84                 host->desc_slot++;
  85         else
  86                 attr |= ADMA_DESC_ATTR_END;
  87
  88         desc->attr = attr;
  89         desc->len = len;
  90         desc->reserved = 0;
  91         desc->addr_lo = lower_32_bits(dma_addr);
  92 #ifdef CONFIG_DMA_ADDR_T_64BIT
  93         desc->addr_hi = upper_32_bits(dma_addr);
  94 #endif
  95 }
  96
  97 static void sdhci_prepare_adma_table(struct sdhci_host *host,
  98                                      struct mmc_data *data)
  99 {
 100         uint trans_bytes = data->blocksize * data->blocks;
 101         uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
 102         int i = desc_count;
 103         dma_addr_t dma_addr = host->start_addr;
 104
 105         host->desc_slot = 0;
 106
 107         while (--i) {
 108                 sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
 109                 dma_addr += ADMA_MAX_LEN;
 110                 trans_bytes -= ADMA_MAX_LEN;
 111         }
 112
 113         sdhci_adma_desc(host, dma_addr, trans_bytes, true);
 114
 115         flush_cache((dma_addr_t)host->adma_desc_table,
 116                     ROUND(desc_count * sizeof(struct sdhci_adma_desc),
 117                           ARCH_DMA_MINALIGN));
 118 }
 119 #elif defined(CONFIG_MMC_SDHCI_SDMA)
 120 static void sdhci_prepare_adma_table(struct sdhci_host *host,
 121                                      struct mmc_data *data)
 122 {}
 123 #endif
 124 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 125 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 126                               int *is_aligned, int trans_bytes)
 127 {
 128         unsigned char ctrl;
 129         void *buf;
 130
 131         if (data->flags == MMC_DATA_READ)
 132                 buf = data->dest;
 133         else
 134                 buf = (void *)data->src;
 135
 136         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 137         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 138         if (host->flags & USE_ADMA64)
 139                 ctrl |= SDHCI_CTRL_ADMA64;
 140         else if (host->flags & USE_ADMA)
 141                 ctrl |= SDHCI_CTRL_ADMA32;
 142         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 143
 144         if (host->flags & USE_SDMA &&
 145             (host->force_align_buffer ||
 146              (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
 147               ((unsigned long)buf & 0x7) != 0x0))) {
 148                 *is_aligned = 0;
 149                 if (data->flags != MMC_DATA_READ)
 150                         memcpy(host->align_buffer, buf, trans_bytes);
 151                 buf = host->align_buffer;
 152         }
 153
 154         host->start_addr = dma_map_single(buf, trans_bytes,
 155                                           mmc_get_dma_dir(data));
 156
 157         if (host->flags & USE_SDMA) {
 158                 sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
 159                                 SDHCI_DMA_ADDRESS);
 160         } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 161                 sdhci_prepare_adma_table(host, data);
 162
 163                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 164                              SDHCI_ADMA_ADDRESS);
 165                 if (host->flags & USE_ADMA64)
 166                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 167                                      SDHCI_ADMA_ADDRESS_HI);
 168         }
 169 }
 170 #else
 171 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 172                               int *is_aligned, int trans_bytes)
 173 {}
 174 #endif
 175 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 176 {
 177         dma_addr_t start_addr = host->start_addr;
 178         unsigned int stat, rdy, mask, timeout, block = 0;
 179         bool transfer_done = false;
 180
 181         timeout = 1000000;
 182         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 183         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 184         do {
 185                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 186                 if (stat & SDHCI_INT_ERROR) {
 187                         pr_debug("%s: Error detected in status(0x%X)!\n",
 188                                  __func__, stat);
 189                         return -EIO;
 190                 }
 191                 if (!transfer_done && (stat & rdy)) {
 192                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 193                                 continue;
 194                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 195                         sdhci_transfer_pio(host, data);
 196                         data->dest += data->blocksize;
 197                         if (++block >= data->blocks) {
 198                                 /* Keep looping until the SDHCI_INT_DATA_END is
 199                                  * cleared, even if we finished sending all the
 200                                  * blocks.
 201                                  */
 202                                 transfer_done = true;
 203                                 continue;
 204                         }
 205                 }
 206                 if ((host->flags & USE_DMA) && !transfer_done &&
 207                     (stat & SDHCI_INT_DMA_END)) {
 208                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 209                         if (host->flags & USE_SDMA) {
 210                                 start_addr &=
 211                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 212                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 213                                 sdhci_writel(host, phys_to_bus((ulong)start_addr),
 214                                              SDHCI_DMA_ADDRESS);
 215                         }
 216                 }
 217                 if (timeout-- > 0)
 218                         udelay(10);
 219                 else {
 220                         printf("%s: Transfer data timeout\n", __func__);
 221                         return -ETIMEDOUT;
 222                 }
 223         } while (!(stat & SDHCI_INT_DATA_END));
 224
 225         dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
 226                          mmc_get_dma_dir(data));
 227
 228         return 0;
 229 }
 230
 231 /*
 232  * No command will be sent by driver if card is busy, so driver must wait
 233  * for card ready state.
 234  * Every time when card is busy after timeout then (last) timeout value will be
 235  * increased twice but only if it doesn't exceed global defined maximum.
 236  * Each function call will use last timeout value.
 237  */
 238 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 239 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 240 #define SDHCI_READ_STATUS_TIMEOUT               1000
 241
 242 #ifdef CONFIG_DM_MMC
 243 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 244                               struct mmc_data *data)
 245 {
 246         struct mmc *mmc = mmc_get_mmc_dev(dev);
 247
 248 #else
 249 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 250                               struct mmc_data *data)
 251 {
 252 #endif
 253         struct sdhci_host *host = mmc->priv;
 254         unsigned int stat = 0;
 255         int ret = 0;
 256         int trans_bytes = 0, is_aligned = 1;
 257         u32 mask, flags, mode;
 258         unsigned int time = 0;
 259         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 260         ulong start = get_timer(0);
 261
 262         host->start_addr = 0;
 263         /* Timeout unit - ms */
 264         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 265
 266         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 267
 268         /* We shouldn't wait for data inihibit for stop commands, even
 269            though they might use busy signaling */
 270         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 271             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 272               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 273                 mask &= ~SDHCI_DATA_INHIBIT;
 274
 275         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 276                 if (time >= cmd_timeout) {
 277                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 278                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 279                                 cmd_timeout += cmd_timeout;
 280                                 printf("timeout increasing to: %u ms.\n",
 281                                        cmd_timeout);
 282                         } else {
 283                                 puts("timeout.\n");
 284                                 return -ECOMM;
 285                         }
 286                 }
 287                 time++;
 288                 udelay(1000);
 289         }
 290
 291         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 292
 293         mask = SDHCI_INT_RESPONSE;
 294         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 295              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 296                 mask = SDHCI_INT_DATA_AVAIL;
 297
 298         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 299                 flags = SDHCI_CMD_RESP_NONE;
 300         else if (cmd->resp_type & MMC_RSP_136)
 301                 flags = SDHCI_CMD_RESP_LONG;
 302         else if (cmd->resp_type & MMC_RSP_BUSY) {
 303                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 304                 if (data)
 305                         mask |= SDHCI_INT_DATA_END;
 306         } else
 307                 flags = SDHCI_CMD_RESP_SHORT;
 308
 309         if (cmd->resp_type & MMC_RSP_CRC)
 310                 flags |= SDHCI_CMD_CRC;
 311         if (cmd->resp_type & MMC_RSP_OPCODE)
 312                 flags |= SDHCI_CMD_INDEX;
 313         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 314             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 315                 flags |= SDHCI_CMD_DATA;
 316
 317         /* Set Transfer mode regarding to data flag */
 318         if (data) {
 319                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 320                 mode = SDHCI_TRNS_BLK_CNT_EN;
 321                 trans_bytes = data->blocks * data->blocksize;
 322                 if (data->blocks > 1)
 323                         mode |= SDHCI_TRNS_MULTI;
 324
 325                 if (data->flags == MMC_DATA_READ)
 326                         mode |= SDHCI_TRNS_READ;
 327
 328                 if (host->flags & USE_DMA) {
 329                         mode |= SDHCI_TRNS_DMA;
 330                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 331                 }
 332
 333                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 334                                 data->blocksize),
 335                                 SDHCI_BLOCK_SIZE);
 336                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 337                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 338         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 339                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 340         }
 341
 342         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 343         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 344         start = get_timer(0);
 345         do {
 346                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 347                 if (stat & SDHCI_INT_ERROR)
 348                         break;
 349
 350                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 351                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 352                                 return 0;
 353                         } else {
 354                                 printf("%s: Timeout for status update!\n",
 355                                        __func__);
 356                                 return -ETIMEDOUT;
 357                         }
 358                 }
 359         } while ((stat & mask) != mask);
 360
 361         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 362                 sdhci_cmd_done(host, cmd);
 363                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 364         } else
 365                 ret = -1;
 366
 367         if (!ret && data)
 368                 ret = sdhci_transfer_data(host, data);
 369
 370         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 371                 udelay(1000);
 372
 373         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 374         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 375         if (!ret) {
 376                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 377                                 !is_aligned && (data->flags == MMC_DATA_READ))
 378                         memcpy(data->dest, host->align_buffer, trans_bytes);
 379                 return 0;
 380         }
 381
 382         sdhci_reset(host, SDHCI_RESET_CMD);
 383         sdhci_reset(host, SDHCI_RESET_DATA);
 384         if (stat & SDHCI_INT_TIMEOUT)
 385                 return -ETIMEDOUT;
 386         else
 387                 return -ECOMM;
 388 }
 389
 390 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 391 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 392 {
 393         int err;
 394         struct mmc *mmc = mmc_get_mmc_dev(dev);
 395         struct sdhci_host *host = mmc->priv;
 396
 397         debug("%s\n", __func__);
 398
 399         if (host->ops && host->ops->platform_execute_tuning) {
 400                 err = host->ops->platform_execute_tuning(mmc, opcode);
 401                 if (err)
 402                         return err;
 403                 return 0;
 404         }
 405         return 0;
 406 }
 407 #endif
 408 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 409 {
 410         struct sdhci_host *host = mmc->priv;
 411         unsigned int div, clk = 0, timeout;
 412
 413         /* Wait max 20 ms */
 414         timeout = 200;
 415         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 416                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 417                 if (timeout == 0) {
 418                         printf("%s: Timeout to wait cmd & data inhibit\n",
 419                                __func__);
 420                         return -EBUSY;
 421                 }
 422
 423                 timeout--;
 424                 udelay(100);
 425         }
 426
 427         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 428
 429         if (clock == 0)
 430                 return 0;
 431
 432         if (host->ops && host->ops->set_delay)
 433                 host->ops->set_delay(host);
 434
 435         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 436                 /*
 437                  * Check if the Host Controller supports Programmable Clock
 438                  * Mode.
 439                  */
 440                 if (host->clk_mul) {
 441                         for (div = 1; div <= 1024; div++) {
 442                                 if ((host->max_clk / div) <= clock)
 443                                         break;
 444                         }
 445
 446                         /*
 447                          * Set Programmable Clock Mode in the Clock
 448                          * Control register.
 449                          */
 450                         clk = SDHCI_PROG_CLOCK_MODE;
 451                         div--;
 452                 } else {
 453                         /* Version 3.00 divisors must be a multiple of 2. */
 454                         if (host->max_clk <= clock) {
 455                                 div = 1;
 456                         } else {
 457                                 for (div = 2;
 458                                      div < SDHCI_MAX_DIV_SPEC_300;
 459                                      div += 2) {
 460                                         if ((host->max_clk / div) <= clock)
 461                                                 break;
 462                                 }
 463                         }
 464                         div >>= 1;
 465                 }
 466         } else {
 467                 /* Version 2.00 divisors must be a power of 2. */
 468                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 469                         if ((host->max_clk / div) <= clock)
 470                                 break;
 471                 }
 472                 div >>= 1;
 473         }
 474
 475         if (host->ops && host->ops->set_clock)
 476                 host->ops->set_clock(host, div);
 477
 478         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 479         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 480                 << SDHCI_DIVIDER_HI_SHIFT;
 481         clk |= SDHCI_CLOCK_INT_EN;
 482         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 483
 484         /* Wait max 20 ms */
 485         timeout = 20;
 486         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 487                 & SDHCI_CLOCK_INT_STABLE)) {
 488                 if (timeout == 0) {
 489                         printf("%s: Internal clock never stabilised.\n",
 490                                __func__);
 491                         return -EBUSY;
 492                 }
 493                 timeout--;
 494                 udelay(1000);
 495         }
 496
 497         clk |= SDHCI_CLOCK_CARD_EN;
 498         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 499         return 0;
 500 }
 501
 502 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 503 {
 504         u8 pwr = 0;
 505
 506         if (power != (unsigned short)-1) {
 507                 switch (1 << power) {
 508                 case MMC_VDD_165_195:
 509                         pwr = SDHCI_POWER_180;
 510                         break;
 511                 case MMC_VDD_29_30:
 512                 case MMC_VDD_30_31:
 513                         pwr = SDHCI_POWER_300;
 514                         break;
 515                 case MMC_VDD_32_33:
 516                 case MMC_VDD_33_34:
 517                         pwr = SDHCI_POWER_330;
 518                         break;
 519                 }
 520         }
 521
 522         if (pwr == 0) {
 523                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 524                 return;
 525         }
 526
 527         pwr |= SDHCI_POWER_ON;
 528
 529         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 530 }
 531
 532 void sdhci_set_uhs_timing(struct sdhci_host *host)
 533 {
 534         struct mmc *mmc = host->mmc;
 535         u32 reg;
 536
 537         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 538         reg &= ~SDHCI_CTRL_UHS_MASK;
 539
 540         switch (mmc->selected_mode) {
 541         case UHS_SDR50:
 542         case MMC_HS_52:
 543                 reg |= SDHCI_CTRL_UHS_SDR50;
 544                 break;
 545         case UHS_DDR50:
 546         case MMC_DDR_52:
 547                 reg |= SDHCI_CTRL_UHS_DDR50;
 548                 break;
 549         case UHS_SDR104:
 550         case MMC_HS_200:
 551                 reg |= SDHCI_CTRL_UHS_SDR104;
 552                 break;
 553         default:
 554                 reg |= SDHCI_CTRL_UHS_SDR12;
 555         }
 556
 557         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 558 }
 559
 560 #ifdef CONFIG_DM_MMC
 561 static int sdhci_set_ios(struct udevice *dev)
 562 {
 563         struct mmc *mmc = mmc_get_mmc_dev(dev);
 564 #else
 565 static int sdhci_set_ios(struct mmc *mmc)
 566 {
 567 #endif
 568         u32 ctrl;
 569         struct sdhci_host *host = mmc->priv;
 570
 571         if (host->ops && host->ops->set_control_reg)
 572                 host->ops->set_control_reg(host);
 573
 574         if (mmc->clock != host->clock)
 575                 sdhci_set_clock(mmc, mmc->clock);
 576
 577         if (mmc->clk_disable)
 578                 sdhci_set_clock(mmc, 0);
 579
 580         /* Set bus width */
 581         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 582         if (mmc->bus_width == 8) {
 583                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 584                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 585                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 586                         ctrl |= SDHCI_CTRL_8BITBUS;
 587         } else {
 588                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 589                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 590                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 591                 if (mmc->bus_width == 4)
 592                         ctrl |= SDHCI_CTRL_4BITBUS;
 593                 else
 594                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 595         }
 596
 597         if (mmc->clock > 26000000)
 598                 ctrl |= SDHCI_CTRL_HISPD;
 599         else
 600                 ctrl &= ~SDHCI_CTRL_HISPD;
 601
 602         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 603             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 604                 ctrl &= ~SDHCI_CTRL_HISPD;
 605
 606         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 607
 608         /* If available, call the driver specific "post" set_ios() function */
 609         if (host->ops && host->ops->set_ios_post)
 610                 return host->ops->set_ios_post(host);
 611
 612         return 0;
 613 }
 614
 615 static int sdhci_init(struct mmc *mmc)
 616 {
 617         struct sdhci_host *host = mmc->priv;
 618 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 619         struct udevice *dev = mmc->dev;
 620
 621         gpio_request_by_name(dev, "cd-gpios", 0,
 622                              &host->cd_gpio, GPIOD_IS_IN);
 623 #endif
 624
 625         sdhci_reset(host, SDHCI_RESET_ALL);
 626
 627 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 628         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 629         /*
 630          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 631          * is defined.
 632          */
 633         host->force_align_buffer = true;
 634 #else
 635         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 636                 host->align_buffer = memalign(8, 512 * 1024);
 637                 if (!host->align_buffer) {
 638                         printf("%s: Aligned buffer alloc failed!!!\n",
 639                                __func__);
 640                         return -ENOMEM;
 641                 }
 642         }
 643 #endif
 644
 645         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 646
 647         if (host->ops && host->ops->get_cd)
 648                 host->ops->get_cd(host);
 649
 650         /* Enable only interrupts served by the SD controller */
 651         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 652                      SDHCI_INT_ENABLE);
 653         /* Mask all sdhci interrupt sources */
 654         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 655
 656         return 0;
 657 }
 658
 659 #ifdef CONFIG_DM_MMC
 660 int sdhci_probe(struct udevice *dev)
 661 {
 662         struct mmc *mmc = mmc_get_mmc_dev(dev);
 663
 664         return sdhci_init(mmc);
 665 }
 666
 667 static int sdhci_deferred_probe(struct udevice *dev)
 668 {
 669         int err;
 670         struct mmc *mmc = mmc_get_mmc_dev(dev);
 671         struct sdhci_host *host = mmc->priv;
 672
 673         if (host->ops && host->ops->deferred_probe) {
 674                 err = host->ops->deferred_probe(host);
 675                 if (err)
 676                         return err;
 677         }
 678         return 0;
 679 }
 680
 681 static int sdhci_get_cd(struct udevice *dev)
 682 {
 683         struct mmc *mmc = mmc_get_mmc_dev(dev);
 684         struct sdhci_host *host = mmc->priv;
 685         int value;
 686
 687         /* If nonremovable, assume that the card is always present. */
 688         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 689                 return 1;
 690         /* If polling, assume that the card is always present. */
 691         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 692                 return 1;
 693
 694 #if CONFIG_IS_ENABLED(DM_GPIO)
 695         value = dm_gpio_get_value(&host->cd_gpio);
 696         if (value >= 0) {
 697                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 698                         return !value;
 699                 else
 700                         return value;
 701         }
 702 #endif
 703         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 704                    SDHCI_CARD_PRESENT);
 705         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 706                 return !value;
 707         else
 708                 return value;
 709 }
 710
 711 const struct dm_mmc_ops sdhci_ops = {
 712         .send_cmd       = sdhci_send_command,
 713         .set_ios        = sdhci_set_ios,
 714         .get_cd         = sdhci_get_cd,
 715         .deferred_probe = sdhci_deferred_probe,
 716 #ifdef MMC_SUPPORTS_TUNING
 717         .execute_tuning = sdhci_execute_tuning,
 718 #endif
 719 };
 720 #else
 721 static const struct mmc_ops sdhci_ops = {
 722         .send_cmd       = sdhci_send_command,
 723         .set_ios        = sdhci_set_ios,
 724         .init           = sdhci_init,
 725 };
 726 #endif
 727
 728 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 729                 u32 f_max, u32 f_min)
 730 {
 731         u32 caps, caps_1 = 0;
 732 #if CONFIG_IS_ENABLED(DM_MMC)
 733         u64 dt_caps, dt_caps_mask;
 734
 735         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 736                                             "sdhci-caps-mask", 0);
 737         dt_caps = dev_read_u64_default(host->mmc->dev,
 738                                        "sdhci-caps", 0);
 739         caps = ~(u32)dt_caps_mask &
 740                sdhci_readl(host, SDHCI_CAPABILITIES);
 741         caps |= (u32)dt_caps;
 742 #else
 743         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 744 #endif
 745         debug("%s, caps: 0x%x\n", __func__, caps);
 746
 747 #ifdef CONFIG_MMC_SDHCI_SDMA
 748         if ((caps & SDHCI_CAN_DO_SDMA)) {
 749                 host->flags |= USE_SDMA;
 750         } else {
 751                 debug("%s: Your controller doesn't support SDMA!!\n",
 752                       __func__);
 753         }
 754 #endif
 755 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 756         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 757                 printf("%s: Your controller doesn't support SDMA!!\n",
 758                        __func__);
 759                 return -EINVAL;
 760         }
 761         host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
 762
 763         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 764 #ifdef CONFIG_DMA_ADDR_T_64BIT
 765         host->flags |= USE_ADMA64;
 766 #else
 767         host->flags |= USE_ADMA;
 768 #endif
 769 #endif
 770         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 771                 host->version =
 772                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 773         else
 774                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 775
 776         cfg->name = host->name;
 777 #ifndef CONFIG_DM_MMC
 778         cfg->ops = &sdhci_ops;
 779 #endif
 780
 781         /* Check whether the clock multiplier is supported or not */
 782         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 783 #if CONFIG_IS_ENABLED(DM_MMC)
 784                 caps_1 = ~(u32)(dt_caps_mask >> 32) &
 785                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 786                 caps_1 |= (u32)(dt_caps >> 32);
 787 #else
 788                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 789 #endif
 790                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 791                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 792                                 SDHCI_CLOCK_MUL_SHIFT;
 793         }
 794
 795         if (host->max_clk == 0) {
 796                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 797                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 798                                 SDHCI_CLOCK_BASE_SHIFT;
 799                 else
 800                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 801                                 SDHCI_CLOCK_BASE_SHIFT;
 802                 host->max_clk *= 1000000;
 803                 if (host->clk_mul)
 804                         host->max_clk *= host->clk_mul;
 805         }
 806         if (host->max_clk == 0) {
 807                 printf("%s: Hardware doesn't specify base clock frequency\n",
 808                        __func__);
 809                 return -EINVAL;
 810         }
 811         if (f_max && (f_max < host->max_clk))
 812                 cfg->f_max = f_max;
 813         else
 814                 cfg->f_max = host->max_clk;
 815         if (f_min)
 816                 cfg->f_min = f_min;
 817         else {
 818                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 819                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 820                 else
 821                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 822         }
 823         cfg->voltages = 0;
 824         if (caps & SDHCI_CAN_VDD_330)
 825                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 826         if (caps & SDHCI_CAN_VDD_300)
 827                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 828         if (caps & SDHCI_CAN_VDD_180)
 829                 cfg->voltages |= MMC_VDD_165_195;
 830
 831         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 832                 cfg->voltages |= host->voltages;
 833
 834         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 835
 836         /* Since Host Controller Version3.0 */
 837         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 838                 if (!(caps & SDHCI_CAN_DO_8BIT))
 839                         cfg->host_caps &= ~MMC_MODE_8BIT;
 840         }
 841
 842         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 843                 cfg->host_caps &= ~MMC_MODE_HS;
 844                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 845         }
 846
 847         if (!(cfg->voltages & MMC_VDD_165_195))
 848                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 849                             SDHCI_SUPPORT_DDR50);
 850
 851         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 852                       SDHCI_SUPPORT_DDR50))
 853                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 854
 855         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 856                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 857                 /*
 858                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 859                  * field can be promoted to support HS200.
 860                  */
 861                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 862         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 863                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 864         }
 865
 866         if (caps_1 & SDHCI_SUPPORT_DDR50)
 867                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 868
 869         if (host->host_caps)
 870                 cfg->host_caps |= host->host_caps;
 871
 872         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 873
 874         return 0;
 875 }
 876
 877 #ifdef CONFIG_BLK
 878 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 879 {
 880         return mmc_bind(dev, mmc, cfg);
 881 }
 882 #else
 883 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 884 {
 885         int ret;
 886
 887         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 888         if (ret)
 889                 return ret;
 890
 891         host->mmc = mmc_create(&host->cfg, host);
 892         if (host->mmc == NULL) {
 893                 printf("%s: mmc create fail!\n", __func__);
 894                 return -ENOMEM;
 895         }
 896
 897         return 0;
 898 }
 899 #endif