drivers/mmc/sdhci.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2011, Marvell Semiconductor Inc.
   4  * Lei Wen <leiwen@marvell.com>
   5  *
   6  * Back ported to the 8xx platform (from the 8260 platform) by
   7  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
   8  */
   9
  10 #include <common.h>
  11 #include <cpu_func.h>
  12 #include <dm.h>
  13 #include <errno.h>
  14 #include <malloc.h>
  15 #include <mmc.h>
  16 #include <sdhci.h>
  17 #include <dm.h>
  18 #include <asm/cache.h>
  19 #include <linux/dma-mapping.h>
  20 #include <phys2bus.h>
  21
  22 static void sdhci_reset(struct sdhci_host *host, u8 mask)
  23 {
  24         unsigned long timeout;
  25
  26         /* Wait max 100 ms */
  27         timeout = 100;
  28         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  29         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  30                 if (timeout == 0) {
  31                         printf("%s: Reset 0x%x never completed.\n",
  32                                __func__, (int)mask);
  33                         return;
  34                 }
  35                 timeout--;
  36                 udelay(1000);
  37         }
  38 }
  39
  40 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  41 {
  42         int i;
  43         if (cmd->resp_type & MMC_RSP_136) {
  44                 /* CRC is stripped so we need to do some shifting. */
  45                 for (i = 0; i < 4; i++) {
  46                         cmd->response[i] = sdhci_readl(host,
  47                                         SDHCI_RESPONSE + (3-i)*4) << 8;
  48                         if (i != 3)
  49                                 cmd->response[i] |= sdhci_readb(host,
  50                                                 SDHCI_RESPONSE + (3-i)*4-1);
  51                 }
  52         } else {
  53                 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  54         }
  55 }
  56
  57 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  58 {
  59         int i;
  60         char *offs;
  61         for (i = 0; i < data->blocksize; i += 4) {
  62                 offs = data->dest + i;
  63                 if (data->flags == MMC_DATA_READ)
  64                         *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  65                 else
  66                         sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  67         }
  68 }
  69
  70 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  71 static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
  72                             u16 len, bool end)
  73 {
  74         struct sdhci_adma_desc *desc;
  75         u8 attr;
  76
  77         desc = &host->adma_desc_table[host->desc_slot];
  78
  79         attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  80         if (!end)
  81                 host->desc_slot++;
  82         else
  83                 attr |= ADMA_DESC_ATTR_END;
  84
  85         desc->attr = attr;
  86         desc->len = len;
  87         desc->reserved = 0;
  88         desc->addr_lo = lower_32_bits(dma_addr);
  89 #ifdef CONFIG_DMA_ADDR_T_64BIT
  90         desc->addr_hi = upper_32_bits(dma_addr);
  91 #endif
  92 }
  93
  94 static void sdhci_prepare_adma_table(struct sdhci_host *host,
  95                                      struct mmc_data *data)
  96 {
  97         uint trans_bytes = data->blocksize * data->blocks;
  98         uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
  99         int i = desc_count;
 100         dma_addr_t dma_addr = host->start_addr;
 101
 102         host->desc_slot = 0;
 103
 104         while (--i) {
 105                 sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
 106                 dma_addr += ADMA_MAX_LEN;
 107                 trans_bytes -= ADMA_MAX_LEN;
 108         }
 109
 110         sdhci_adma_desc(host, dma_addr, trans_bytes, true);
 111
 112         flush_cache((dma_addr_t)host->adma_desc_table,
 113                     ROUND(desc_count * sizeof(struct sdhci_adma_desc),
 114                           ARCH_DMA_MINALIGN));
 115 }
 116 #elif defined(CONFIG_MMC_SDHCI_SDMA)
 117 static void sdhci_prepare_adma_table(struct sdhci_host *host,
 118                                      struct mmc_data *data)
 119 {}
 120 #endif
 121 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
 122 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 123                               int *is_aligned, int trans_bytes)
 124 {
 125         unsigned char ctrl;
 126         void *buf;
 127
 128         if (data->flags == MMC_DATA_READ)
 129                 buf = data->dest;
 130         else
 131                 buf = (void *)data->src;
 132
 133         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 134         ctrl &= ~SDHCI_CTRL_DMA_MASK;
 135         if (host->flags & USE_ADMA64)
 136                 ctrl |= SDHCI_CTRL_ADMA64;
 137         else if (host->flags & USE_ADMA)
 138                 ctrl |= SDHCI_CTRL_ADMA32;
 139         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 140
 141         if (host->flags & USE_SDMA &&
 142             (host->force_align_buffer ||
 143              (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
 144               ((unsigned long)buf & 0x7) != 0x0))) {
 145                 *is_aligned = 0;
 146                 if (data->flags != MMC_DATA_READ)
 147                         memcpy(host->align_buffer, buf, trans_bytes);
 148                 buf = host->align_buffer;
 149         }
 150
 151         host->start_addr = dma_map_single(buf, trans_bytes,
 152                                           mmc_get_dma_dir(data));
 153
 154         if (host->flags & USE_SDMA) {
 155                 sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
 156                                 SDHCI_DMA_ADDRESS);
 157         } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
 158                 sdhci_prepare_adma_table(host, data);
 159
 160                 sdhci_writel(host, lower_32_bits(host->adma_addr),
 161                              SDHCI_ADMA_ADDRESS);
 162                 if (host->flags & USE_ADMA64)
 163                         sdhci_writel(host, upper_32_bits(host->adma_addr),
 164                                      SDHCI_ADMA_ADDRESS_HI);
 165         }
 166 }
 167 #else
 168 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
 169                               int *is_aligned, int trans_bytes)
 170 {}
 171 #endif
 172 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
 173 {
 174         dma_addr_t start_addr = host->start_addr;
 175         unsigned int stat, rdy, mask, timeout, block = 0;
 176         bool transfer_done = false;
 177
 178         timeout = 1000000;
 179         rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 180         mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 181         do {
 182                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 183                 if (stat & SDHCI_INT_ERROR) {
 184                         pr_debug("%s: Error detected in status(0x%X)!\n",
 185                                  __func__, stat);
 186                         return -EIO;
 187                 }
 188                 if (!transfer_done && (stat & rdy)) {
 189                         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
 190                                 continue;
 191                         sdhci_writel(host, rdy, SDHCI_INT_STATUS);
 192                         sdhci_transfer_pio(host, data);
 193                         data->dest += data->blocksize;
 194                         if (++block >= data->blocks) {
 195                                 /* Keep looping until the SDHCI_INT_DATA_END is
 196                                  * cleared, even if we finished sending all the
 197                                  * blocks.
 198                                  */
 199                                 transfer_done = true;
 200                                 continue;
 201                         }
 202                 }
 203                 if ((host->flags & USE_DMA) && !transfer_done &&
 204                     (stat & SDHCI_INT_DMA_END)) {
 205                         sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
 206                         if (host->flags & USE_SDMA) {
 207                                 start_addr &=
 208                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 209                                 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 210                                 sdhci_writel(host, phys_to_bus((ulong)start_addr),
 211                                              SDHCI_DMA_ADDRESS);
 212                         }
 213                 }
 214                 if (timeout-- > 0)
 215                         udelay(10);
 216                 else {
 217                         printf("%s: Transfer data timeout\n", __func__);
 218                         return -ETIMEDOUT;
 219                 }
 220         } while (!(stat & SDHCI_INT_DATA_END));
 221
 222         dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
 223                          mmc_get_dma_dir(data));
 224
 225         return 0;
 226 }
 227
 228 /*
 229  * No command will be sent by driver if card is busy, so driver must wait
 230  * for card ready state.
 231  * Every time when card is busy after timeout then (last) timeout value will be
 232  * increased twice but only if it doesn't exceed global defined maximum.
 233  * Each function call will use last timeout value.
 234  */
 235 #define SDHCI_CMD_MAX_TIMEOUT                   3200
 236 #define SDHCI_CMD_DEFAULT_TIMEOUT               100
 237 #define SDHCI_READ_STATUS_TIMEOUT               1000
 238
 239 #ifdef CONFIG_DM_MMC
 240 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
 241                               struct mmc_data *data)
 242 {
 243         struct mmc *mmc = mmc_get_mmc_dev(dev);
 244
 245 #else
 246 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 247                               struct mmc_data *data)
 248 {
 249 #endif
 250         struct sdhci_host *host = mmc->priv;
 251         unsigned int stat = 0;
 252         int ret = 0;
 253         int trans_bytes = 0, is_aligned = 1;
 254         u32 mask, flags, mode;
 255         unsigned int time = 0;
 256         int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
 257         ulong start = get_timer(0);
 258
 259         host->start_addr = 0;
 260         /* Timeout unit - ms */
 261         static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
 262
 263         mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
 264
 265         /* We shouldn't wait for data inihibit for stop commands, even
 266            though they might use busy signaling */
 267         if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
 268             ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 269               cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
 270                 mask &= ~SDHCI_DATA_INHIBIT;
 271
 272         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 273                 if (time >= cmd_timeout) {
 274                         printf("%s: MMC: %d busy ", __func__, mmc_dev);
 275                         if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
 276                                 cmd_timeout += cmd_timeout;
 277                                 printf("timeout increasing to: %u ms.\n",
 278                                        cmd_timeout);
 279                         } else {
 280                                 puts("timeout.\n");
 281                                 return -ECOMM;
 282                         }
 283                 }
 284                 time++;
 285                 udelay(1000);
 286         }
 287
 288         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 289
 290         mask = SDHCI_INT_RESPONSE;
 291         if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
 292              cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
 293                 mask = SDHCI_INT_DATA_AVAIL;
 294
 295         if (!(cmd->resp_type & MMC_RSP_PRESENT))
 296                 flags = SDHCI_CMD_RESP_NONE;
 297         else if (cmd->resp_type & MMC_RSP_136)
 298                 flags = SDHCI_CMD_RESP_LONG;
 299         else if (cmd->resp_type & MMC_RSP_BUSY) {
 300                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 301                 if (data)
 302                         mask |= SDHCI_INT_DATA_END;
 303         } else
 304                 flags = SDHCI_CMD_RESP_SHORT;
 305
 306         if (cmd->resp_type & MMC_RSP_CRC)
 307                 flags |= SDHCI_CMD_CRC;
 308         if (cmd->resp_type & MMC_RSP_OPCODE)
 309                 flags |= SDHCI_CMD_INDEX;
 310         if (data || cmd->cmdidx ==  MMC_CMD_SEND_TUNING_BLOCK ||
 311             cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
 312                 flags |= SDHCI_CMD_DATA;
 313
 314         /* Set Transfer mode regarding to data flag */
 315         if (data) {
 316                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 317                 mode = SDHCI_TRNS_BLK_CNT_EN;
 318                 trans_bytes = data->blocks * data->blocksize;
 319                 if (data->blocks > 1)
 320                         mode |= SDHCI_TRNS_MULTI;
 321
 322                 if (data->flags == MMC_DATA_READ)
 323                         mode |= SDHCI_TRNS_READ;
 324
 325                 if (host->flags & USE_DMA) {
 326                         mode |= SDHCI_TRNS_DMA;
 327                         sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
 328                 }
 329
 330                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 331                                 data->blocksize),
 332                                 SDHCI_BLOCK_SIZE);
 333                 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 334                 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 335         } else if (cmd->resp_type & MMC_RSP_BUSY) {
 336                 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
 337         }
 338
 339         sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 340         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 341         start = get_timer(0);
 342         do {
 343                 stat = sdhci_readl(host, SDHCI_INT_STATUS);
 344                 if (stat & SDHCI_INT_ERROR)
 345                         break;
 346
 347                 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
 348                         if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
 349                                 return 0;
 350                         } else {
 351                                 printf("%s: Timeout for status update!\n",
 352                                        __func__);
 353                                 return -ETIMEDOUT;
 354                         }
 355                 }
 356         } while ((stat & mask) != mask);
 357
 358         if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
 359                 sdhci_cmd_done(host, cmd);
 360                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
 361         } else
 362                 ret = -1;
 363
 364         if (!ret && data)
 365                 ret = sdhci_transfer_data(host, data);
 366
 367         if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
 368                 udelay(1000);
 369
 370         stat = sdhci_readl(host, SDHCI_INT_STATUS);
 371         sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
 372         if (!ret) {
 373                 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
 374                                 !is_aligned && (data->flags == MMC_DATA_READ))
 375                         memcpy(data->dest, host->align_buffer, trans_bytes);
 376                 return 0;
 377         }
 378
 379         sdhci_reset(host, SDHCI_RESET_CMD);
 380         sdhci_reset(host, SDHCI_RESET_DATA);
 381         if (stat & SDHCI_INT_TIMEOUT)
 382                 return -ETIMEDOUT;
 383         else
 384                 return -ECOMM;
 385 }
 386
 387 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
 388 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
 389 {
 390         int err;
 391         struct mmc *mmc = mmc_get_mmc_dev(dev);
 392         struct sdhci_host *host = mmc->priv;
 393
 394         debug("%s\n", __func__);
 395
 396         if (host->ops && host->ops->platform_execute_tuning) {
 397                 err = host->ops->platform_execute_tuning(mmc, opcode);
 398                 if (err)
 399                         return err;
 400                 return 0;
 401         }
 402         return 0;
 403 }
 404 #endif
 405 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
 406 {
 407         struct sdhci_host *host = mmc->priv;
 408         unsigned int div, clk = 0, timeout;
 409
 410         /* Wait max 20 ms */
 411         timeout = 200;
 412         while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
 413                            (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
 414                 if (timeout == 0) {
 415                         printf("%s: Timeout to wait cmd & data inhibit\n",
 416                                __func__);
 417                         return -EBUSY;
 418                 }
 419
 420                 timeout--;
 421                 udelay(100);
 422         }
 423
 424         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
 425
 426         if (clock == 0)
 427                 return 0;
 428
 429         if (host->ops && host->ops->set_delay)
 430                 host->ops->set_delay(host);
 431
 432         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 433                 /*
 434                  * Check if the Host Controller supports Programmable Clock
 435                  * Mode.
 436                  */
 437                 if (host->clk_mul) {
 438                         for (div = 1; div <= 1024; div++) {
 439                                 if ((host->max_clk / div) <= clock)
 440                                         break;
 441                         }
 442
 443                         /*
 444                          * Set Programmable Clock Mode in the Clock
 445                          * Control register.
 446                          */
 447                         clk = SDHCI_PROG_CLOCK_MODE;
 448                         div--;
 449                 } else {
 450                         /* Version 3.00 divisors must be a multiple of 2. */
 451                         if (host->max_clk <= clock) {
 452                                 div = 1;
 453                         } else {
 454                                 for (div = 2;
 455                                      div < SDHCI_MAX_DIV_SPEC_300;
 456                                      div += 2) {
 457                                         if ((host->max_clk / div) <= clock)
 458                                                 break;
 459                                 }
 460                         }
 461                         div >>= 1;
 462                 }
 463         } else {
 464                 /* Version 2.00 divisors must be a power of 2. */
 465                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
 466                         if ((host->max_clk / div) <= clock)
 467                                 break;
 468                 }
 469                 div >>= 1;
 470         }
 471
 472         if (host->ops && host->ops->set_clock)
 473                 host->ops->set_clock(host, div);
 474
 475         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
 476         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
 477                 << SDHCI_DIVIDER_HI_SHIFT;
 478         clk |= SDHCI_CLOCK_INT_EN;
 479         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 480
 481         /* Wait max 20 ms */
 482         timeout = 20;
 483         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
 484                 & SDHCI_CLOCK_INT_STABLE)) {
 485                 if (timeout == 0) {
 486                         printf("%s: Internal clock never stabilised.\n",
 487                                __func__);
 488                         return -EBUSY;
 489                 }
 490                 timeout--;
 491                 udelay(1000);
 492         }
 493
 494         clk |= SDHCI_CLOCK_CARD_EN;
 495         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
 496         return 0;
 497 }
 498
 499 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
 500 {
 501         u8 pwr = 0;
 502
 503         if (power != (unsigned short)-1) {
 504                 switch (1 << power) {
 505                 case MMC_VDD_165_195:
 506                         pwr = SDHCI_POWER_180;
 507                         break;
 508                 case MMC_VDD_29_30:
 509                 case MMC_VDD_30_31:
 510                         pwr = SDHCI_POWER_300;
 511                         break;
 512                 case MMC_VDD_32_33:
 513                 case MMC_VDD_33_34:
 514                         pwr = SDHCI_POWER_330;
 515                         break;
 516                 }
 517         }
 518
 519         if (pwr == 0) {
 520                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
 521                 return;
 522         }
 523
 524         pwr |= SDHCI_POWER_ON;
 525
 526         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
 527 }
 528
 529 void sdhci_set_uhs_timing(struct sdhci_host *host)
 530 {
 531         struct mmc *mmc = host->mmc;
 532         u32 reg;
 533
 534         reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 535         reg &= ~SDHCI_CTRL_UHS_MASK;
 536
 537         switch (mmc->selected_mode) {
 538         case UHS_SDR50:
 539         case MMC_HS_52:
 540                 reg |= SDHCI_CTRL_UHS_SDR50;
 541                 break;
 542         case UHS_DDR50:
 543         case MMC_DDR_52:
 544                 reg |= SDHCI_CTRL_UHS_DDR50;
 545                 break;
 546         case UHS_SDR104:
 547         case MMC_HS_200:
 548                 reg |= SDHCI_CTRL_UHS_SDR104;
 549                 break;
 550         default:
 551                 reg |= SDHCI_CTRL_UHS_SDR12;
 552         }
 553
 554         sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 555 }
 556
 557 #ifdef CONFIG_DM_MMC
 558 static int sdhci_set_ios(struct udevice *dev)
 559 {
 560         struct mmc *mmc = mmc_get_mmc_dev(dev);
 561 #else
 562 static int sdhci_set_ios(struct mmc *mmc)
 563 {
 564 #endif
 565         u32 ctrl;
 566         struct sdhci_host *host = mmc->priv;
 567
 568         if (host->ops && host->ops->set_control_reg)
 569                 host->ops->set_control_reg(host);
 570
 571         if (mmc->clock != host->clock)
 572                 sdhci_set_clock(mmc, mmc->clock);
 573
 574         if (mmc->clk_disable)
 575                 sdhci_set_clock(mmc, 0);
 576
 577         /* Set bus width */
 578         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 579         if (mmc->bus_width == 8) {
 580                 ctrl &= ~SDHCI_CTRL_4BITBUS;
 581                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 582                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 583                         ctrl |= SDHCI_CTRL_8BITBUS;
 584         } else {
 585                 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
 586                                 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
 587                         ctrl &= ~SDHCI_CTRL_8BITBUS;
 588                 if (mmc->bus_width == 4)
 589                         ctrl |= SDHCI_CTRL_4BITBUS;
 590                 else
 591                         ctrl &= ~SDHCI_CTRL_4BITBUS;
 592         }
 593
 594         if (mmc->clock > 26000000)
 595                 ctrl |= SDHCI_CTRL_HISPD;
 596         else
 597                 ctrl &= ~SDHCI_CTRL_HISPD;
 598
 599         if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
 600             (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
 601                 ctrl &= ~SDHCI_CTRL_HISPD;
 602
 603         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 604
 605         /* If available, call the driver specific "post" set_ios() function */
 606         if (host->ops && host->ops->set_ios_post)
 607                 return host->ops->set_ios_post(host);
 608
 609         return 0;
 610 }
 611
 612 static int sdhci_init(struct mmc *mmc)
 613 {
 614         struct sdhci_host *host = mmc->priv;
 615 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
 616         struct udevice *dev = mmc->dev;
 617
 618         gpio_request_by_name(dev, "cd-gpios", 0,
 619                              &host->cd_gpio, GPIOD_IS_IN);
 620 #endif
 621
 622         sdhci_reset(host, SDHCI_RESET_ALL);
 623
 624 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
 625         host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
 626         /*
 627          * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
 628          * is defined.
 629          */
 630         host->force_align_buffer = true;
 631 #else
 632         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
 633                 host->align_buffer = memalign(8, 512 * 1024);
 634                 if (!host->align_buffer) {
 635                         printf("%s: Aligned buffer alloc failed!!!\n",
 636                                __func__);
 637                         return -ENOMEM;
 638                 }
 639         }
 640 #endif
 641
 642         sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
 643
 644         if (host->ops && host->ops->get_cd)
 645                 host->ops->get_cd(host);
 646
 647         /* Enable only interrupts served by the SD controller */
 648         sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
 649                      SDHCI_INT_ENABLE);
 650         /* Mask all sdhci interrupt sources */
 651         sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
 652
 653         return 0;
 654 }
 655
 656 #ifdef CONFIG_DM_MMC
 657 int sdhci_probe(struct udevice *dev)
 658 {
 659         struct mmc *mmc = mmc_get_mmc_dev(dev);
 660
 661         return sdhci_init(mmc);
 662 }
 663
 664 static int sdhci_deferred_probe(struct udevice *dev)
 665 {
 666         int err;
 667         struct mmc *mmc = mmc_get_mmc_dev(dev);
 668         struct sdhci_host *host = mmc->priv;
 669
 670         if (host->ops && host->ops->deferred_probe) {
 671                 err = host->ops->deferred_probe(host);
 672                 if (err)
 673                         return err;
 674         }
 675         return 0;
 676 }
 677
 678 static int sdhci_get_cd(struct udevice *dev)
 679 {
 680         struct mmc *mmc = mmc_get_mmc_dev(dev);
 681         struct sdhci_host *host = mmc->priv;
 682         int value;
 683
 684         /* If nonremovable, assume that the card is always present. */
 685         if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
 686                 return 1;
 687         /* If polling, assume that the card is always present. */
 688         if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
 689                 return 1;
 690
 691 #if CONFIG_IS_ENABLED(DM_GPIO)
 692         value = dm_gpio_get_value(&host->cd_gpio);
 693         if (value >= 0) {
 694                 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 695                         return !value;
 696                 else
 697                         return value;
 698         }
 699 #endif
 700         value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 701                    SDHCI_CARD_PRESENT);
 702         if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
 703                 return !value;
 704         else
 705                 return value;
 706 }
 707
 708 const struct dm_mmc_ops sdhci_ops = {
 709         .send_cmd       = sdhci_send_command,
 710         .set_ios        = sdhci_set_ios,
 711         .get_cd         = sdhci_get_cd,
 712         .deferred_probe = sdhci_deferred_probe,
 713 #ifdef MMC_SUPPORTS_TUNING
 714         .execute_tuning = sdhci_execute_tuning,
 715 #endif
 716 };
 717 #else
 718 static const struct mmc_ops sdhci_ops = {
 719         .send_cmd       = sdhci_send_command,
 720         .set_ios        = sdhci_set_ios,
 721         .init           = sdhci_init,
 722 };
 723 #endif
 724
 725 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
 726                 u32 f_max, u32 f_min)
 727 {
 728         u32 caps, caps_1 = 0;
 729 #if CONFIG_IS_ENABLED(DM_MMC)
 730         u64 dt_caps, dt_caps_mask;
 731
 732         dt_caps_mask = dev_read_u64_default(host->mmc->dev,
 733                                             "sdhci-caps-mask", 0);
 734         dt_caps = dev_read_u64_default(host->mmc->dev,
 735                                        "sdhci-caps", 0);
 736         caps = ~(u32)dt_caps_mask &
 737                sdhci_readl(host, SDHCI_CAPABILITIES);
 738         caps |= (u32)dt_caps;
 739 #else
 740         caps = sdhci_readl(host, SDHCI_CAPABILITIES);
 741 #endif
 742         debug("%s, caps: 0x%x\n", __func__, caps);
 743
 744 #ifdef CONFIG_MMC_SDHCI_SDMA
 745         if ((caps & SDHCI_CAN_DO_SDMA)) {
 746                 host->flags |= USE_SDMA;
 747         } else {
 748                 debug("%s: Your controller doesn't support SDMA!!\n",
 749                       __func__);
 750         }
 751 #endif
 752 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 753         if (!(caps & SDHCI_CAN_DO_ADMA2)) {
 754                 printf("%s: Your controller doesn't support SDMA!!\n",
 755                        __func__);
 756                 return -EINVAL;
 757         }
 758         host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
 759
 760         host->adma_addr = (dma_addr_t)host->adma_desc_table;
 761 #ifdef CONFIG_DMA_ADDR_T_64BIT
 762         host->flags |= USE_ADMA64;
 763 #else
 764         host->flags |= USE_ADMA;
 765 #endif
 766 #endif
 767         if (host->quirks & SDHCI_QUIRK_REG32_RW)
 768                 host->version =
 769                         sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
 770         else
 771                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 772
 773         cfg->name = host->name;
 774 #ifndef CONFIG_DM_MMC
 775         cfg->ops = &sdhci_ops;
 776 #endif
 777
 778         /* Check whether the clock multiplier is supported or not */
 779         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 780 #if CONFIG_IS_ENABLED(DM_MMC)
 781                 caps_1 = ~(u32)(dt_caps_mask >> 32) &
 782                          sdhci_readl(host, SDHCI_CAPABILITIES_1);
 783                 caps_1 |= (u32)(dt_caps >> 32);
 784 #else
 785                 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
 786 #endif
 787                 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
 788                 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
 789                                 SDHCI_CLOCK_MUL_SHIFT;
 790         }
 791
 792         if (host->max_clk == 0) {
 793                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 794                         host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
 795                                 SDHCI_CLOCK_BASE_SHIFT;
 796                 else
 797                         host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
 798                                 SDHCI_CLOCK_BASE_SHIFT;
 799                 host->max_clk *= 1000000;
 800                 if (host->clk_mul)
 801                         host->max_clk *= host->clk_mul;
 802         }
 803         if (host->max_clk == 0) {
 804                 printf("%s: Hardware doesn't specify base clock frequency\n",
 805                        __func__);
 806                 return -EINVAL;
 807         }
 808         if (f_max && (f_max < host->max_clk))
 809                 cfg->f_max = f_max;
 810         else
 811                 cfg->f_max = host->max_clk;
 812         if (f_min)
 813                 cfg->f_min = f_min;
 814         else {
 815                 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
 816                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
 817                 else
 818                         cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
 819         }
 820         cfg->voltages = 0;
 821         if (caps & SDHCI_CAN_VDD_330)
 822                 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
 823         if (caps & SDHCI_CAN_VDD_300)
 824                 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 825         if (caps & SDHCI_CAN_VDD_180)
 826                 cfg->voltages |= MMC_VDD_165_195;
 827
 828         if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
 829                 cfg->voltages |= host->voltages;
 830
 831         cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 832
 833         /* Since Host Controller Version3.0 */
 834         if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
 835                 if (!(caps & SDHCI_CAN_DO_8BIT))
 836                         cfg->host_caps &= ~MMC_MODE_8BIT;
 837         }
 838
 839         if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
 840                 cfg->host_caps &= ~MMC_MODE_HS;
 841                 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
 842         }
 843
 844         if (!(cfg->voltages & MMC_VDD_165_195))
 845                 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 846                             SDHCI_SUPPORT_DDR50);
 847
 848         if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
 849                       SDHCI_SUPPORT_DDR50))
 850                 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
 851
 852         if (caps_1 & SDHCI_SUPPORT_SDR104) {
 853                 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
 854                 /*
 855                  * SD3.0: SDR104 is supported so (for eMMC) the caps2
 856                  * field can be promoted to support HS200.
 857                  */
 858                 cfg->host_caps |= MMC_CAP(MMC_HS_200);
 859         } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
 860                 cfg->host_caps |= MMC_CAP(UHS_SDR50);
 861         }
 862
 863         if (caps_1 & SDHCI_SUPPORT_DDR50)
 864                 cfg->host_caps |= MMC_CAP(UHS_DDR50);
 865
 866         if (host->host_caps)
 867                 cfg->host_caps |= host->host_caps;
 868
 869         cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 870
 871         return 0;
 872 }
 873
 874 #ifdef CONFIG_BLK
 875 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
 876 {
 877         return mmc_bind(dev, mmc, cfg);
 878 }
 879 #else
 880 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
 881 {
 882         int ret;
 883
 884         ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
 885         if (ret)
 886                 return ret;
 887
 888         host->mmc = mmc_create(&host->cfg, host);
 889         if (host->mmc == NULL) {
 890                 printf("%s: mmc create fail!\n", __func__);
 891                 return -ENOMEM;
 892         }
 893
 894         return 0;
 895 }
 896 #endif